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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License version 2 as |
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6 | | - * published by the Free Software Foundation. |
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7 | 4 | */ |
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8 | 5 | |
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9 | 6 | #include <linux/of.h> |
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.. | .. |
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12 | 9 | #include <dt-bindings/memory/tegra30-mc.h> |
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13 | 10 | |
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14 | 11 | #include "mc.h" |
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| 12 | + |
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| 13 | +static const unsigned long tegra30_mc_emem_regs[] = { |
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| 14 | + MC_EMEM_ARB_CFG, |
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| 15 | + MC_EMEM_ARB_OUTSTANDING_REQ, |
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| 16 | + MC_EMEM_ARB_TIMING_RCD, |
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| 17 | + MC_EMEM_ARB_TIMING_RP, |
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| 18 | + MC_EMEM_ARB_TIMING_RC, |
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| 19 | + MC_EMEM_ARB_TIMING_RAS, |
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| 20 | + MC_EMEM_ARB_TIMING_FAW, |
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| 21 | + MC_EMEM_ARB_TIMING_RRD, |
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| 22 | + MC_EMEM_ARB_TIMING_RAP2PRE, |
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| 23 | + MC_EMEM_ARB_TIMING_WAP2PRE, |
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| 24 | + MC_EMEM_ARB_TIMING_R2R, |
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| 25 | + MC_EMEM_ARB_TIMING_W2W, |
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| 26 | + MC_EMEM_ARB_TIMING_R2W, |
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| 27 | + MC_EMEM_ARB_TIMING_W2R, |
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| 28 | + MC_EMEM_ARB_DA_TURNS, |
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| 29 | + MC_EMEM_ARB_DA_COVERS, |
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| 30 | + MC_EMEM_ARB_MISC0, |
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| 31 | + MC_EMEM_ARB_RING1_THROTTLE, |
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| 32 | +}; |
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15 | 33 | |
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16 | 34 | static const struct tegra_mc_client tegra30_mc_clients[] = { |
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17 | 35 | { |
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.. | .. |
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726 | 744 | }, |
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727 | 745 | }, { |
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728 | 746 | .id = 0x34, |
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729 | | - .name = "fdcwr2", |
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| 747 | + .name = "fdcdwr2", |
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730 | 748 | .swgroup = TEGRA_SWGROUP_NV2, |
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731 | 749 | .smmu = { |
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732 | 750 | .reg = 0x22c, |
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.. | .. |
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934 | 952 | { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, |
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935 | 953 | }; |
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936 | 954 | |
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937 | | -static const unsigned int tegra30_group_display[] = { |
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| 955 | +static const unsigned int tegra30_group_drm[] = { |
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938 | 956 | TEGRA_SWGROUP_DC, |
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939 | 957 | TEGRA_SWGROUP_DCB, |
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| 958 | + TEGRA_SWGROUP_G2, |
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| 959 | + TEGRA_SWGROUP_NV, |
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| 960 | + TEGRA_SWGROUP_NV2, |
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940 | 961 | }; |
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941 | 962 | |
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942 | 963 | static const struct tegra_smmu_group_soc tegra30_groups[] = { |
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943 | 964 | { |
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944 | | - .name = "display", |
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945 | | - .swgroups = tegra30_group_display, |
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946 | | - .num_swgroups = ARRAY_SIZE(tegra30_group_display), |
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| 965 | + .name = "drm", |
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| 966 | + .swgroups = tegra30_group_drm, |
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| 967 | + .num_swgroups = ARRAY_SIZE(tegra30_group_drm), |
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947 | 968 | }, |
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948 | 969 | }; |
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949 | 970 | |
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.. | .. |
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997 | 1018 | .atom_size = 16, |
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998 | 1019 | .client_id_mask = 0x7f, |
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999 | 1020 | .smmu = &tegra30_smmu_soc, |
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| 1021 | + .emem_regs = tegra30_mc_emem_regs, |
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| 1022 | + .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs), |
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1000 | 1023 | .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | |
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1001 | 1024 | MC_INT_DECERR_EMEM, |
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1002 | | - .reset_ops = &terga_mc_reset_ops_common, |
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| 1025 | + .reset_ops = &tegra_mc_reset_ops_common, |
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1003 | 1026 | .resets = tegra30_mc_resets, |
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1004 | 1027 | .num_resets = ARRAY_SIZE(tegra30_mc_resets), |
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1005 | 1028 | }; |
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