forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/memory/tegra/tegra30.c
....@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
74 */
85
96 #include <linux/of.h>
....@@ -12,6 +9,27 @@
129 #include <dt-bindings/memory/tegra30-mc.h>
1310
1411 #include "mc.h"
12
+
13
+static const unsigned long tegra30_mc_emem_regs[] = {
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+ MC_EMEM_ARB_CFG,
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+ MC_EMEM_ARB_OUTSTANDING_REQ,
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+ MC_EMEM_ARB_TIMING_RCD,
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+ MC_EMEM_ARB_TIMING_RP,
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+ MC_EMEM_ARB_TIMING_RC,
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+ MC_EMEM_ARB_TIMING_RAS,
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+ MC_EMEM_ARB_TIMING_FAW,
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+ MC_EMEM_ARB_TIMING_RRD,
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+ MC_EMEM_ARB_TIMING_RAP2PRE,
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+ MC_EMEM_ARB_TIMING_WAP2PRE,
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+ MC_EMEM_ARB_TIMING_R2R,
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+ MC_EMEM_ARB_TIMING_W2W,
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+ MC_EMEM_ARB_TIMING_R2W,
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+ MC_EMEM_ARB_TIMING_W2R,
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+ MC_EMEM_ARB_DA_TURNS,
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+ MC_EMEM_ARB_DA_COVERS,
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+ MC_EMEM_ARB_MISC0,
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+ MC_EMEM_ARB_RING1_THROTTLE,
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+};
1533
1634 static const struct tegra_mc_client tegra30_mc_clients[] = {
1735 {
....@@ -726,7 +744,7 @@
726744 },
727745 }, {
728746 .id = 0x34,
729
- .name = "fdcwr2",
747
+ .name = "fdcdwr2",
730748 .swgroup = TEGRA_SWGROUP_NV2,
731749 .smmu = {
732750 .reg = 0x22c,
....@@ -934,16 +952,19 @@
934952 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
935953 };
936954
937
-static const unsigned int tegra30_group_display[] = {
955
+static const unsigned int tegra30_group_drm[] = {
938956 TEGRA_SWGROUP_DC,
939957 TEGRA_SWGROUP_DCB,
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+ TEGRA_SWGROUP_G2,
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+ TEGRA_SWGROUP_NV,
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+ TEGRA_SWGROUP_NV2,
940961 };
941962
942963 static const struct tegra_smmu_group_soc tegra30_groups[] = {
943964 {
944
- .name = "display",
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- .swgroups = tegra30_group_display,
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- .num_swgroups = ARRAY_SIZE(tegra30_group_display),
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+ .name = "drm",
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+ .swgroups = tegra30_group_drm,
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+ .num_swgroups = ARRAY_SIZE(tegra30_group_drm),
947968 },
948969 };
949970
....@@ -997,9 +1018,11 @@
9971018 .atom_size = 16,
9981019 .client_id_mask = 0x7f,
9991020 .smmu = &tegra30_smmu_soc,
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+ .emem_regs = tegra30_mc_emem_regs,
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+ .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
10001023 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
10011024 MC_INT_DECERR_EMEM,
1002
- .reset_ops = &terga_mc_reset_ops_common,
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+ .reset_ops = &tegra_mc_reset_ops_common,
10031026 .resets = tegra30_mc_resets,
10041027 .num_resets = ARRAY_SIZE(tegra30_mc_resets),
10051028 };