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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * Driver for Mediatek IR Receiver Controller |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or |
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7 | | - * modify it under the terms of the GNU General Public License as |
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8 | | - * published by the Free Software Foundation; either version 2 of |
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9 | | - * the License, or (at your option) any later version. |
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10 | | - * |
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11 | | - * This program is distributed in the hope that it will be useful, |
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12 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | | - * GNU General Public License for more details. |
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15 | 6 | */ |
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16 | 7 | |
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17 | 8 | #include <linux/clk.h> |
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.. | .. |
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61 | 52 | #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) |
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62 | 53 | /* Number of registers to record the pulse width */ |
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63 | 54 | #define MTK_CHKDATA_SZ 17 |
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64 | | -/* Sample period in ns */ |
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65 | | -#define MTK_IR_SAMPLE 46000 |
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| 55 | +/* Sample period in us */ |
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| 56 | +#define MTK_IR_SAMPLE 46 |
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66 | 57 | |
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67 | 58 | enum mtk_fields { |
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68 | 59 | /* Register to setting software sampling period */ |
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.. | .. |
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160 | 151 | { |
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161 | 152 | u32 val; |
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162 | 153 | |
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163 | | - /* Period of raw software sampling in ns */ |
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164 | | - val = DIV_ROUND_CLOSEST(1000000000ul, |
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165 | | - clk_get_rate(ir->bus) / ir->data->div); |
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166 | | - |
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167 | 154 | /* |
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168 | 155 | * Period for software decoder used in the |
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169 | 156 | * unit of raw software sampling |
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170 | 157 | */ |
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171 | | - val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val); |
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| 158 | + val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), |
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| 159 | + USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); |
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172 | 160 | |
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173 | 161 | dev_dbg(ir->dev, "@pwm clk = \t%lu\n", |
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174 | 162 | clk_get_rate(ir->bus) / ir->data->div); |
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.. | .. |
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217 | 205 | struct mtk_ir *ir = dev_id; |
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218 | 206 | u8 wid = 0; |
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219 | 207 | u32 i, j, val; |
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220 | | - DEFINE_IR_RAW_EVENT(rawir); |
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| 208 | + struct ir_raw_event rawir = {}; |
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221 | 209 | |
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222 | 210 | /* |
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223 | 211 | * Reset decoder state machine explicitly is required |
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.. | .. |
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334 | 322 | |
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335 | 323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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336 | 324 | ir->base = devm_ioremap_resource(dev, res); |
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337 | | - if (IS_ERR(ir->base)) { |
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338 | | - dev_err(dev, "failed to map registers\n"); |
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| 325 | + if (IS_ERR(ir->base)) |
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339 | 326 | return PTR_ERR(ir->base); |
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340 | | - } |
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341 | 327 | |
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342 | 328 | ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); |
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343 | 329 | if (!ir->rc) { |
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.. | .. |
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356 | 342 | ir->rc->map_name = map_name ?: RC_MAP_EMPTY; |
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357 | 343 | ir->rc->dev.parent = dev; |
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358 | 344 | ir->rc->driver_name = MTK_IR_DEV; |
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359 | | - ir->rc->allowed_protocols = RC_PROTO_BIT_ALL; |
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| 345 | + ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
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360 | 346 | ir->rc->rx_resolution = MTK_IR_SAMPLE; |
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361 | 347 | ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); |
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362 | 348 | |
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.. | .. |
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369 | 355 | platform_set_drvdata(pdev, ir); |
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370 | 356 | |
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371 | 357 | ir->irq = platform_get_irq(pdev, 0); |
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372 | | - if (ir->irq < 0) { |
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373 | | - dev_err(dev, "no irq resource\n"); |
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| 358 | + if (ir->irq < 0) |
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374 | 359 | return -ENODEV; |
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375 | | - } |
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376 | 360 | |
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377 | 361 | if (clk_prepare_enable(ir->clk)) { |
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378 | 362 | dev_err(dev, "try to enable ir_clk failed\n"); |
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.. | .. |
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425 | 409 | mtk_irq_enable(ir, MTK_IRINT_EN); |
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426 | 410 | |
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427 | 411 | dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", |
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428 | | - DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000)); |
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| 412 | + MTK_IR_SAMPLE); |
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429 | 413 | |
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430 | 414 | return 0; |
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431 | 415 | |
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