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| 1 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
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1 | 2 | /* |
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2 | 3 | * Driver for Analog Devices ADV748X video decoder and HDMI receiver |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2017 Renesas Electronics Corp. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify it |
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7 | | - * under the terms of the GNU General Public License as published by the |
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8 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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9 | | - * option) any later version. |
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10 | 6 | * |
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11 | 7 | * Authors: |
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12 | 8 | * Koji Matsuoka <koji.matsuoka.xm@renesas.com> |
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.. | .. |
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43 | 39 | ADV748X_PAGE_MAX, |
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44 | 40 | |
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45 | 41 | /* Fake pages for register sequences */ |
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46 | | - ADV748X_PAGE_WAIT, /* Wait x msec */ |
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47 | 42 | ADV748X_PAGE_EOR, /* End Mark */ |
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48 | 43 | }; |
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49 | 44 | |
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.. | .. |
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83 | 78 | struct v4l2_mbus_framefmt format; |
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84 | 79 | unsigned int page; |
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85 | 80 | unsigned int port; |
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| 81 | + unsigned int num_lanes; |
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| 82 | + unsigned int active_lanes; |
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86 | 83 | |
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87 | 84 | struct media_pad pads[ADV748X_CSI2_NR_PADS]; |
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88 | 85 | struct v4l2_ctrl_handler ctrl_hdl; |
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89 | 86 | struct v4l2_ctrl *pixel_rate; |
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| 87 | + struct v4l2_subdev *src; |
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90 | 88 | struct v4l2_subdev sd; |
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91 | 89 | }; |
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92 | 90 | |
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93 | 91 | #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier) |
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94 | 92 | #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd) |
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| 93 | + |
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95 | 94 | #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL) |
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| 95 | +#define is_txa(_tx) ((_tx) == &(_tx)->state->txa) |
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| 96 | +#define is_txb(_tx) ((_tx) == &(_tx)->state->txb) |
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| 97 | +#define is_tx(_tx) (is_txa(_tx) || is_txb(_tx)) |
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| 98 | + |
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| 99 | +#define is_afe_enabled(_state) \ |
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| 100 | + ((_state)->endpoints[ADV748X_PORT_AIN0] != NULL || \ |
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| 101 | + (_state)->endpoints[ADV748X_PORT_AIN1] != NULL || \ |
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| 102 | + (_state)->endpoints[ADV748X_PORT_AIN2] != NULL || \ |
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| 103 | + (_state)->endpoints[ADV748X_PORT_AIN3] != NULL || \ |
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| 104 | + (_state)->endpoints[ADV748X_PORT_AIN4] != NULL || \ |
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| 105 | + (_state)->endpoints[ADV748X_PORT_AIN5] != NULL || \ |
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| 106 | + (_state)->endpoints[ADV748X_PORT_AIN6] != NULL || \ |
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| 107 | + (_state)->endpoints[ADV748X_PORT_AIN7] != NULL) |
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| 108 | +#define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL) |
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96 | 109 | |
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97 | 110 | enum adv748x_hdmi_pads { |
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98 | 111 | ADV748X_HDMI_SINK, |
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.. | .. |
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108 | 121 | |
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109 | 122 | struct v4l2_dv_timings timings; |
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110 | 123 | struct v4l2_fract aspect_ratio; |
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| 124 | + |
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| 125 | + struct adv748x_csi2 *tx; |
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111 | 126 | |
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112 | 127 | struct { |
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113 | 128 | u8 edid[512]; |
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.. | .. |
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138 | 153 | struct v4l2_ctrl_handler ctrl_hdl; |
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139 | 154 | struct v4l2_subdev sd; |
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140 | 155 | struct v4l2_mbus_framefmt format; |
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| 156 | + |
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| 157 | + struct adv748x_csi2 *tx; |
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141 | 158 | |
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142 | 159 | bool streaming; |
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143 | 160 | v4l2_std_id curr_norm; |
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.. | .. |
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194 | 211 | #define ADV748X_IO_PD 0x00 /* power down controls */ |
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195 | 212 | #define ADV748X_IO_PD_RX_EN BIT(6) |
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196 | 213 | |
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| 214 | +#define ADV748X_IO_REG_01 0x01 /* pwrdn{2}b, prog_xtal_freq */ |
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| 215 | +#define ADV748X_IO_REG_01_PWRDN_MASK (BIT(7) | BIT(6)) |
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| 216 | +#define ADV748X_IO_REG_01_PWRDN2B BIT(7) /* CEC Wakeup Support */ |
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| 217 | +#define ADV748X_IO_REG_01_PWRDNB BIT(6) /* CEC Wakeup Support */ |
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| 218 | + |
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197 | 219 | #define ADV748X_IO_REG_04 0x04 |
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198 | 220 | #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */ |
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199 | 221 | |
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.. | .. |
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207 | 229 | #define ADV748X_IO_10_CSI4_EN BIT(7) |
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208 | 230 | #define ADV748X_IO_10_CSI1_EN BIT(6) |
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209 | 231 | #define ADV748X_IO_10_PIX_OUT_EN BIT(5) |
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| 232 | +#define ADV748X_IO_10_CSI4_IN_SEL_AFE BIT(3) |
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210 | 233 | |
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211 | 234 | #define ADV748X_IO_CHIP_REV_ID_1 0xdf |
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212 | 235 | #define ADV748X_IO_CHIP_REV_ID_2 0xe0 |
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213 | 236 | |
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| 237 | +#define ADV748X_IO_REG_F2 0xf2 |
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| 238 | +#define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0) |
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| 239 | + |
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| 240 | +/* For PAGE slave address offsets */ |
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214 | 241 | #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2 |
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| 242 | + |
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| 243 | +/* |
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| 244 | + * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and |
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| 245 | + * 0xff as examples for performing a software reset. |
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| 246 | + */ |
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| 247 | +#define ADV748X_IO_REG_FF 0xff |
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| 248 | +#define ADV748X_IO_REG_FF_MAIN_RESET 0xff |
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215 | 249 | |
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216 | 250 | /* HDMI RX Map */ |
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217 | 251 | #define ADV748X_HDMI_LW1 0x07 /* line width_1 */ |
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.. | .. |
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378 | 412 | #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v) |
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379 | 413 | #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v)) |
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380 | 414 | |
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381 | | -#define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r) |
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382 | | -#define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r) |
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383 | | - |
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384 | 415 | #define tx_read(t, r) adv748x_read(t->state, t->page, r) |
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385 | 416 | #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v) |
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386 | 417 | |
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.. | .. |
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400 | 431 | int adv748x_register_subdevs(struct adv748x_state *state, |
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401 | 432 | struct v4l2_device *v4l2_dev); |
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402 | 433 | |
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403 | | -int adv748x_txa_power(struct adv748x_state *state, bool on); |
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404 | | -int adv748x_txb_power(struct adv748x_state *state, bool on); |
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| 434 | +int adv748x_tx_power(struct adv748x_csi2 *tx, bool on); |
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405 | 435 | |
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406 | 436 | int adv748x_afe_init(struct adv748x_afe *afe); |
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407 | 437 | void adv748x_afe_cleanup(struct adv748x_afe *afe); |
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