| .. | .. |
|---|
| 425 | 425 | *active_width = IB_WIDTH_2X; |
|---|
| 426 | 426 | *active_speed = IB_SPEED_HDR; |
|---|
| 427 | 427 | break; |
|---|
| 428 | + case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): |
|---|
| 429 | + *active_width = IB_WIDTH_1X; |
|---|
| 430 | + *active_speed = IB_SPEED_NDR; |
|---|
| 431 | + break; |
|---|
| 428 | 432 | case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): |
|---|
| 429 | 433 | *active_width = IB_WIDTH_4X; |
|---|
| 430 | 434 | *active_speed = IB_SPEED_HDR; |
|---|
| 435 | + break; |
|---|
| 436 | + case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): |
|---|
| 437 | + *active_width = IB_WIDTH_2X; |
|---|
| 438 | + *active_speed = IB_SPEED_NDR; |
|---|
| 439 | + break; |
|---|
| 440 | + case MLX5E_PROT_MASK(MLX5E_400GAUI_8): |
|---|
| 441 | + *active_width = IB_WIDTH_8X; |
|---|
| 442 | + *active_speed = IB_SPEED_HDR; |
|---|
| 443 | + break; |
|---|
| 444 | + case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): |
|---|
| 445 | + *active_width = IB_WIDTH_4X; |
|---|
| 446 | + *active_speed = IB_SPEED_NDR; |
|---|
| 431 | 447 | break; |
|---|
| 432 | 448 | default: |
|---|
| 433 | 449 | return -EINVAL; |
|---|
| .. | .. |
|---|
| 2053 | 2069 | case MLX5_IB_MMAP_DEVICE_MEM: |
|---|
| 2054 | 2070 | return "Device Memory"; |
|---|
| 2055 | 2071 | default: |
|---|
| 2056 | | - return NULL; |
|---|
| 2072 | + return "Unknown"; |
|---|
| 2057 | 2073 | } |
|---|
| 2058 | 2074 | } |
|---|
| 2059 | 2075 | |
|---|
| .. | .. |
|---|
| 4164 | 4180 | (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | |
|---|
| 4165 | 4181 | (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | |
|---|
| 4166 | 4182 | (1ull << IB_USER_VERBS_CMD_OPEN_QP); |
|---|
| 4167 | | - dev->ib_dev.uverbs_ex_cmd_mask = |
|---|
| 4168 | | - (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | |
|---|
| 4183 | + dev->ib_dev.uverbs_ex_cmd_mask |= |
|---|
| 4169 | 4184 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | |
|---|
| 4170 | 4185 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | |
|---|
| 4171 | | - (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | |
|---|
| 4172 | | - (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | |
|---|
| 4173 | | - (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | |
|---|
| 4174 | | - (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); |
|---|
| 4186 | + (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); |
|---|
| 4175 | 4187 | |
|---|
| 4176 | 4188 | if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && |
|---|
| 4177 | 4189 | IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) |
|---|
| .. | .. |
|---|
| 4274 | 4286 | ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); |
|---|
| 4275 | 4287 | |
|---|
| 4276 | 4288 | if (ll == IB_LINK_LAYER_ETHERNET) { |
|---|
| 4277 | | - dev->ib_dev.uverbs_ex_cmd_mask |= |
|---|
| 4278 | | - (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | |
|---|
| 4279 | | - (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | |
|---|
| 4280 | | - (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | |
|---|
| 4281 | | - (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | |
|---|
| 4282 | | - (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); |
|---|
| 4283 | 4289 | ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); |
|---|
| 4284 | 4290 | |
|---|
| 4285 | 4291 | port_num = mlx5_core_native_port_num(dev->mdev) - 1; |
|---|
| .. | .. |
|---|
| 4730 | 4736 | STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, |
|---|
| 4731 | 4737 | mlx5_ib_stage_post_ib_reg_umr_init, |
|---|
| 4732 | 4738 | NULL), |
|---|
| 4739 | + STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, |
|---|
| 4740 | + mlx5_ib_stage_delay_drop_init, |
|---|
| 4741 | + mlx5_ib_stage_delay_drop_cleanup), |
|---|
| 4733 | 4742 | STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, |
|---|
| 4734 | 4743 | mlx5_ib_restrack_init, |
|---|
| 4735 | 4744 | NULL), |
|---|