~hc/RK356X_SDK_RELEASE.git

..	..	@@ -36,6 +36,7 @@
36	36	#include <linux/bitops.h>
37	37
38	38	#define HNS_ROCE_VF_QPC_BT_NUM 256
	39	+#define HNS_ROCE_VF_SCCC_BT_NUM 64
39	40	#define HNS_ROCE_VF_SRQC_BT_NUM 64
40	41	#define HNS_ROCE_VF_CQC_BT_NUM 64
41	42	#define HNS_ROCE_VF_MPT_BT_NUM 64
..	..	@@ -44,49 +45,79 @@
44	45	#define HNS_ROCE_VF_SGID_NUM 32
45	46	#define HNS_ROCE_VF_SL_NUM 8
46	47
47		-#define HNS_ROCE_V2_MAX_QP_NUM 0x2000
	48	+#define HNS_ROCE_V2_MAX_QP_NUM 0x100000
	49	+#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
48	50	#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
49		-#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
50		-#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
51		-#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
52		-#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
	51	+#define HNS_ROCE_V2_MAX_SRQ 0x100000
	52	+#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
	53	+#define HNS_ROCE_V2_MAX_SRQ_SGE 64
	54	+#define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
	55	+#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
	56	+#define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
	57	+#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
	58	+#define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
	59	+#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64
	60	+#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64
53	61	#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
54	62	#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
	63	+#define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32
55	64	#define HNS_ROCE_V2_UAR_NUM 256
56	65	#define HNS_ROCE_V2_PHY_UAR_NUM 1
57	66	#define HNS_ROCE_V2_MAX_IRQ_NUM 65
58	67	#define HNS_ROCE_V2_COMP_VEC_NUM 63
59	68	#define HNS_ROCE_V2_AEQE_VEC_NUM 1
60	69	#define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
61		-#define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
	70	+#define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
62	71	#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
63	72	#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
	73	+#define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
	74	+#define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
64	75	#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
65	76	#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
66	77	#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
67	78	#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
68	79	#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
69	80	#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
70		-#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
71	81	#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
72	82	#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
	83	+#define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100
73	84	#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
	85	+#define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
74	86	#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
75	87	#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
76		-#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
77		-#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
	88	+#define HNS_ROCE_V2_IDX_ENTRY_SZ 4
	89	+
	90	+#define HNS_ROCE_V2_SCCC_SZ 32
	91	+#define HNS_ROCE_V3_SCCC_SZ 64
	92	+
	93	+#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
	94	+#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
	95	+#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFF000
78	96	#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
79	97	#define HNS_ROCE_INVALID_LKEY 0x100
80	98	#define HNS_ROCE_CMQ_TX_TIMEOUT 30000
81	99	#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
82	100	#define HNS_ROCE_V2_RSV_QPS 8
83	101
	102	+#define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
	103	+#define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
	104	+
	105	+#define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
	106	+
84	107	#define HNS_ROCE_CONTEXT_HOP_NUM 1
	108	+#define HNS_ROCE_SCCC_HOP_NUM 1
85	109	#define HNS_ROCE_MTT_HOP_NUM 1
86	110	#define HNS_ROCE_CQE_HOP_NUM 1
	111	+#define HNS_ROCE_SRQWQE_HOP_NUM 1
87	112	#define HNS_ROCE_PBL_HOP_NUM 2
88	113	#define HNS_ROCE_EQE_HOP_NUM 2
	114	+#define HNS_ROCE_IDX_HOP_NUM 1
	115	+#define HNS_ROCE_SQWQE_HOP_NUM 2
	116	+#define HNS_ROCE_EXT_SGE_HOP_NUM 1
	117	+#define HNS_ROCE_RQWQE_HOP_NUM 2
89	118
	119	+#define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6
	120	+#define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2
90	121	#define HNS_ROCE_V2_GID_INDEX_NUM 256
91	122
92	123	#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
..	..	@@ -106,13 +137,15 @@
106	137	#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
107	138
108	139	#define HNS_ROCE_CMQ_DESC_NUM_S 3
109		-#define HNS_ROCE_CMQ_EN_B 16
110		-#define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
	140	+
	141	+#define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
111	142
112	143	#define check_whether_last_step(hop_num, step_idx) \
113	144	((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) \|\| \
114	145	(step_idx == 1 && hop_num == 1) \|\| \
115	146	(step_idx == 2 && hop_num == 2))
	147	+#define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
	148	+#define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
116	149
117	150	#define CMD_CSQ_DESC_NUM 1024
118	151	#define CMD_CRQ_DESC_NUM 1024
..	..	@@ -131,7 +164,7 @@
131	164
132	165	#define GID_LEN_V2 16
133	166
134		-#define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
	167	+#define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff
135	168
136	169	enum {
137	170	HNS_ROCE_V2_WQE_OP_SEND = 0x0,
..	..	@@ -146,24 +179,8 @@
146	179	HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
147	180	HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
148	181	HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
149		- HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
	182	+ HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
150	183	HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
151		-};
152		-
153		-enum {
154		- HNS_ROCE_SQ_OPCODE_SEND = 0x0,
155		- HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
156		- HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
157		- HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
158		- HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
159		- HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
160		- HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
161		- HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
162		- HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
163		- HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
164		- HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
165		- HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
166		- HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
167	184	};
168	185
169	186	enum {
..	..	@@ -197,12 +214,14 @@
197	214	HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
198	215	HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
199	216	HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
	217	+ HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
200	218
201	219	HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
202	220	};
203	221
204	222	/* CMQ command */
205	223	enum hns_roce_opcode_type {
	224	+ HNS_QUERY_FW_VER = 0x0001,
206	225	HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
207	226	HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
208	227	HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
..	..	@@ -210,9 +229,19 @@
210	229	HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
211	230	HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
212	231	HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
	232	+ HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
	233	+ HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
	234	+ HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
213	235	HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
214	236	HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
	237	+ HNS_ROCE_OPC_POST_MB = 0x8504,
	238	+ HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
215	239	HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
	240	+ HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
	241	+ HNS_ROCE_OPC_CLR_SCCC = 0x8509,
	242	+ HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
	243	+ HNS_ROCE_OPC_RESET_SCCC = 0x850b,
	244	+ HNS_SWITCH_PARAMETER_CFG = 0x1033,
216	245	};
217	246
218	247	enum {
..	..	@@ -283,6 +312,9 @@
283	312	#define V2_CQC_BYTE_8_CQN_S 0
284	313	#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
285	314
	315	+#define V2_CQC_BYTE_8_CQE_SIZE_S 27
	316	+#define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
	317	+
286	318	#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
287	319	#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
288	320
..	..	@@ -324,8 +356,93 @@
324	356	#define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
325	357	#define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
326	358
327		-enum{
	359	+struct hns_roce_srq_context {
	360	+ __le32 byte_4_srqn_srqst;
	361	+ __le32 byte_8_limit_wl;
	362	+ __le32 byte_12_xrcd;
	363	+ __le32 byte_16_pi_ci;
	364	+ __le32 wqe_bt_ba;
	365	+ __le32 byte_24_wqe_bt_ba;
	366	+ __le32 byte_28_rqws_pd;
	367	+ __le32 idx_bt_ba;
	368	+ __le32 rsv_idx_bt_ba;
	369	+ __le32 idx_cur_blk_addr;
	370	+ __le32 byte_44_idxbufpgsz_addr;
	371	+ __le32 idx_nxt_blk_addr;
	372	+ __le32 rsv_idxnxtblkaddr;
	373	+ __le32 byte_56_xrc_cqn;
	374	+ __le32 db_record_addr_record_en;
	375	+ __le32 db_record_addr;
	376	+};
	377	+
	378	+#define SRQC_BYTE_4_SRQ_ST_S 0
	379	+#define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
	380	+
	381	+#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
	382	+#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
	383	+
	384	+#define SRQC_BYTE_4_SRQ_SHIFT_S 4
	385	+#define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
	386	+
	387	+#define SRQC_BYTE_4_SRQN_S 8
	388	+#define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
	389	+
	390	+#define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
	391	+#define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
	392	+
	393	+#define SRQC_BYTE_12_SRQ_XRCD_S 0
	394	+#define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
	395	+
	396	+#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
	397	+#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
	398	+
	399	+#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
	400	+#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
	401	+
	402	+#define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
	403	+#define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
	404	+
	405	+#define SRQC_BYTE_28_PD_S 0
	406	+#define SRQC_BYTE_28_PD_M GENMASK(23, 0)
	407	+
	408	+#define SRQC_BYTE_28_RQWS_S 24
	409	+#define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
	410	+
	411	+#define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
	412	+#define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
	413	+
	414	+#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
	415	+#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
	416	+
	417	+#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
	418	+#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
	419	+
	420	+#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
	421	+#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
	422	+
	423	+#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
	424	+#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
	425	+
	426	+#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
	427	+#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
	428	+
	429	+#define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
	430	+#define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
	431	+
	432	+#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
	433	+#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
	434	+
	435	+#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
	436	+#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
	437	+
	438	+#define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
	439	+
	440	+#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
	441	+#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
	442	+
	443	+enum {
328	444	V2_MPT_ST_VALID = 0x1,
	445	+ V2_MPT_ST_FREE = 0x2,
329	446	};
330	447
331	448	enum hns_roce_v2_qp_state {
..	..	@@ -333,8 +450,8 @@
333	450	HNS_ROCE_QP_ST_INIT,
334	451	HNS_ROCE_QP_ST_RTR,
335	452	HNS_ROCE_QP_ST_RTS,
336		- HNS_ROCE_QP_ST_SQER,
337	453	HNS_ROCE_QP_ST_SQD,
	454	+ HNS_ROCE_QP_ST_SQER,
338	455	HNS_ROCE_QP_ST_ERR,
339	456	HNS_ROCE_QP_ST_SQ_DRAINING,
340	457	HNS_ROCE_QP_NUM_ST
..	..	@@ -352,7 +469,7 @@
352	469	__le32 dmac;
353	470	__le32 byte_52_udpspn_dmac;
354	471	__le32 byte_56_dqpn_err;
355		- __le32 byte_60_qpst_mapid;
	472	+ __le32 byte_60_qpst_tempid;
356	473	__le32 qkey_xrcd;
357	474	__le32 byte_68_rq_db;
358	475	__le32 rq_db_record_addr;
..	..	@@ -401,6 +518,7 @@
401	518	__le32 byte_248_ack_psn;
402	519	__le32 byte_252_err_txcqn;
403	520	__le32 byte_256_sqflush_rqcqe;
	521	+ __le32 ext[64];
404	522	};
405	523
406	524	#define V2_QPC_BYTE_4_TST_S 0
..	..	@@ -494,26 +612,15 @@
494	612	#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
495	613	#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
496	614
497		-#define V2_QPC_BYTE_60_MAPID_S 0
498		-#define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0)
	615	+#define V2_QPC_BYTE_60_TEMPID_S 0
	616	+#define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
499	617
500		-#define V2_QPC_BYTE_60_INNER_MAP_IND_S 13
	618	+#define V2_QPC_BYTE_60_SCC_TOKEN_S 8
	619	+#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
501	620
502		-#define V2_QPC_BYTE_60_SQ_MAP_IND_S 14
	621	+#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
503	622
504		-#define V2_QPC_BYTE_60_RQ_MAP_IND_S 15
505		-
506		-#define V2_QPC_BYTE_60_TEMPID_S 16
507		-#define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16)
508		-
509		-#define V2_QPC_BYTE_60_EXT_MAP_IND_S 23
510		-
511		-#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24
512		-#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24)
513		-
514		-#define V2_QPC_BYTE_60_SQ_RLS_IND_S 27
515		-
516		-#define V2_QPC_BYTE_60_SQ_EXT_IND_S 28
	623	+#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
517	624
518	625	#define V2_QPC_BYTE_60_QP_ST_S 29
519	626	#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
..	..	@@ -535,7 +642,8 @@
535	642	#define V2_QPC_BYTE_76_ATE_S 27
536	643
537	644	#define V2_QPC_BYTE_76_RQIE_S 28
538		-
	645	+#define V2_QPC_BYTE_76_EXT_ATE_S 29
	646	+#define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
539	647	#define V2_QPC_BYTE_80_RX_CQN_S 0
540	648	#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
541	649
..	..	@@ -590,7 +698,7 @@
590	698	#define V2_QPC_BYTE_140_RR_MAX_S 12
591	699	#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
592	700
593		-#define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15
	701	+#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
594	702
595	703	#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
596	704	#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
..	..	@@ -600,8 +708,6 @@
600	708
601	709	#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
602	710	#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
603		-
604		-#define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24
605	711
606	712	#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
607	713	#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
..	..	@@ -614,8 +720,8 @@
614	720	#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
615	721	#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
616	722
617		-#define V2_QPC_BYTE_152_RAQ_PSN_S 8
618		-#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8)
	723	+#define V2_QPC_BYTE_152_RAQ_PSN_S 0
	724	+#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
619	725
620	726	#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
621	727	#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
..	..	@@ -639,9 +745,10 @@
639	745	#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
640	746	#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
641	747
642		-#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
643		-#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)
644		-
	748	+#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
	749	+#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
	750	+#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
	751	+#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
645	752	#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
646	753	#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
647	754
..	..	@@ -727,6 +834,10 @@
727	834	#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
728	835	#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
729	836
	837	+#define V2_QPC_BYTE_232_SO_LP_VLD_S 29
	838	+#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
	839	+#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
	840	+
730	841	#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
731	842	#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
732	843
..	..	@@ -744,6 +855,9 @@
744	855
745	856	#define V2_QPC_BYTE_244_RNR_CNT_S 27
746	857	#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
	858	+
	859	+#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
	860	+#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
747	861
748	862	#define V2_QPC_BYTE_248_IRRL_PSN_S 0
749	863	#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
..	..	@@ -773,6 +887,10 @@
773	887	#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
774	888	#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
775	889
	890	+#define V2_QP_RWE_S 1 /* rdma write enable */
	891	+#define V2_QP_RRE_S 2 /* rdma read enable */
	892	+#define V2_QP_ATE_S 3 /* rdma atomic enable */
	893	+
776	894	struct hns_roce_v2_cqe {
777	895	__le32 byte_4;
778	896	union {
..	..	@@ -785,6 +903,7 @@
785	903	u8 smac[4];
786	904	__le32 byte_28;
787	905	__le32 byte_32;
	906	+ __le32 rsv[8];
788	907	};
789	908
790	909	#define V2_CQE_BYTE_4_OPCODE_S 0
..	..	@@ -819,6 +938,11 @@
819	938
820	939	#define V2_CQE_BYTE_28_PORT_TYPE_S 16
821	940	#define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
	941	+
	942	+#define V2_CQE_BYTE_28_VID_S 18
	943	+#define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
	944	+
	945	+#define V2_CQE_BYTE_28_VID_VLD_S 30
822	946
823	947	#define V2_CQE_BYTE_32_RMT_QPN_S 0
824	948	#define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
..	..	@@ -880,7 +1004,18 @@
880	1004
881	1005	#define V2_MPT_BYTE_8_LW_EN_S 7
882	1006
	1007	+#define V2_MPT_BYTE_8_MW_CNT_S 8
	1008	+#define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
	1009	+
	1010	+#define V2_MPT_BYTE_12_FRE_S 0
	1011	+
883	1012	#define V2_MPT_BYTE_12_PA_S 1
	1013	+
	1014	+#define V2_MPT_BYTE_12_MR_MW_S 4
	1015	+
	1016	+#define V2_MPT_BYTE_12_BPD_S 5
	1017	+
	1018	+#define V2_MPT_BYTE_12_BQP_S 6
884	1019
885	1020	#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
886	1021
..	..	@@ -913,11 +1048,6 @@
913	1048	#define V2_DB_PARAMETER_SL_S 16
914	1049	#define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
915	1050
916		-struct hns_roce_v2_cq_db {
917		- __le32 byte_4;
918		- __le32 parameter;
919		-};
920		-
921	1051	#define V2_CQ_DB_BYTE_4_TAG_S 0
922	1052	#define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
923	1053
..	..	@@ -946,9 +1076,9 @@
946	1076	__le32 dmac;
947	1077	__le32 byte_48;
948	1078	u8 dgid[GID_LEN_V2];
949		-
950	1079	};
951		-#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
	1080	+
	1081	+#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
952	1082	#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
953	1083
954	1084	#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
..	..	@@ -989,6 +1119,8 @@
989	1119
990	1120	#define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
991	1121	#define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
	1122	+
	1123	+#define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
992	1124
993	1125	#define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
994	1126
..	..	@@ -1044,6 +1176,16 @@
1044	1176
1045	1177	#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1046	1178
	1179	+#define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
	1180	+
	1181	+#define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
	1182	+
	1183	+#define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
	1184	+
	1185	+#define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
	1186	+
	1187	+#define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
	1188	+
1047	1189	#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1048	1190	#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1049	1191
..	..	@@ -1052,6 +1194,18 @@
1052	1194
1053	1195	#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1054	1196	#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
	1197	+
	1198	+#define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
	1199	+
	1200	+struct hns_roce_wqe_frmr_seg {
	1201	+ __le32 pbl_size;
	1202	+ __le32 mode_buf_pg_sz;
	1203	+};
	1204	+
	1205	+#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
	1206	+#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
	1207	+
	1208	+#define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1055	1209
1056	1210	struct hns_roce_v2_wqe_data_seg {
1057	1211	__le32 len;
..	..	@@ -1069,6 +1223,26 @@
1069	1223	__le16 rocee_hw_version;
1070	1224	__le32 rsv[5];
1071	1225	};
	1226	+
	1227	+struct hns_roce_query_fw_info {
	1228	+ __le32 fw_ver;
	1229	+ __le32 rsv[5];
	1230	+};
	1231	+
	1232	+struct hns_roce_func_clear {
	1233	+ __le32 rst_funcid_en;
	1234	+ __le32 func_done;
	1235	+ __le32 rsv[4];
	1236	+};
	1237	+
	1238	+#define FUNC_CLEAR_RST_FUN_DONE_S 0
	1239	+/* Each physical function manages up to 248 virtual functions, it takes up to
	1240	+ * 100ms for each function to execute clear. If an abnormal reset occurs, it is
	1241	+ * executed twice at most, so it takes up to 249 * 2 * 100ms.
	1242	+ */
	1243	+#define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
	1244	+#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
	1245	+#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
1072	1246
1073	1247	struct hns_roce_cfg_llm_a {
1074	1248	__le32 base_addr_l;
..	..	@@ -1159,7 +1333,8 @@
1159	1333	__le32 smac_idx_num;
1160	1334	__le32 sgid_idx_num;
1161	1335	__le32 qid_idx_sl_num;
1162		- __le32 rsv[2];
	1336	+ __le32 sccc_bt_idx_num;
	1337	+ __le32 rsv;
1163	1338	};
1164	1339
1165	1340	#define PF_RES_DATA_1_PF_SMAC_IDX_S 0
..	..	@@ -1179,6 +1354,31 @@
1179	1354
1180	1355	#define PF_RES_DATA_3_PF_SL_NUM_S 16
1181	1356	#define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
	1357	+
	1358	+#define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
	1359	+#define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
	1360	+
	1361	+#define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9
	1362	+#define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
	1363	+
	1364	+struct hns_roce_pf_timer_res_a {
	1365	+ __le32 rsv0;
	1366	+ __le32 qpc_timer_bt_idx_num;
	1367	+ __le32 cqc_timer_bt_idx_num;
	1368	+ __le32 rsv[3];
	1369	+};
	1370	+
	1371	+#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
	1372	+#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
	1373	+
	1374	+#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16
	1375	+#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
	1376	+
	1377	+#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
	1378	+#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
	1379	+
	1380	+#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16
	1381	+#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
1182	1382
1183	1383	struct hns_roce_vf_res_a {
1184	1384	__le32 vf_id;
..	..	@@ -1224,7 +1424,8 @@
1224	1424	__le32 vf_smac_idx_num;
1225	1425	__le32 vf_sgid_idx_num;
1226	1426	__le32 vf_qid_idx_sl_num;
1227		- __le32 rsv[2];
	1427	+ __le32 vf_sccc_idx_num;
	1428	+ __le32 rsv1;
1228	1429	};
1229	1430
1230	1431	#define VF_RES_B_DATA_0_VF_ID_S 0
..	..	@@ -1248,12 +1449,49 @@
1248	1449	#define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1249	1450	#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1250	1451
	1452	+#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
	1453	+#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
	1454	+
	1455	+#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9
	1456	+#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
	1457	+
	1458	+struct hns_roce_vf_switch {
	1459	+ __le32 rocee_sel;
	1460	+ __le32 fun_id;
	1461	+ __le32 cfg;
	1462	+ __le32 resv1;
	1463	+ __le32 resv2;
	1464	+ __le32 resv3;
	1465	+};
	1466	+
	1467	+#define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
	1468	+#define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
	1469	+
	1470	+#define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
	1471	+#define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
	1472	+#define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
	1473	+
	1474	+struct hns_roce_post_mbox {
	1475	+ __le32 in_param_l;
	1476	+ __le32 in_param_h;
	1477	+ __le32 out_param_l;
	1478	+ __le32 out_param_h;
	1479	+ __le32 cmd_tag;
	1480	+ __le32 token_event_en;
	1481	+};
	1482	+
	1483	+struct hns_roce_mbox_status {
	1484	+ __le32 mb_status_hw_run;
	1485	+ __le32 rsv[5];
	1486	+};
	1487	+
1251	1488	struct hns_roce_cfg_bt_attr {
1252	1489	__le32 vf_qpc_cfg;
1253	1490	__le32 vf_srqc_cfg;
1254	1491	__le32 vf_cqc_cfg;
1255	1492	__le32 vf_mpt_cfg;
1256		- __le32 rsv[2];
	1493	+ __le32 vf_sccc_cfg;
	1494	+ __le32 rsv;
1257	1495	};
1258	1496
1259	1497	#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
..	..	@@ -1292,6 +1530,15 @@
1292	1530	#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1293	1531	#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1294	1532
	1533	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
	1534	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
	1535	+
	1536	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4
	1537	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
	1538	+
	1539	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8
	1540	+#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
	1541	+
1295	1542	struct hns_roce_cfg_sgid_tb {
1296	1543	__le32 table_idx_rsv;
1297	1544	__le32 vf_sgid_l;
..	..	@@ -1300,6 +1547,18 @@
1300	1547	__le32 vf_sgid_h;
1301	1548	__le32 vf_sgid_type_rsv;
1302	1549	};
	1550	+
	1551	+enum {
	1552	+ HNS_ROCE_CFG_QPC_SIZE = BIT(0),
	1553	+ HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
	1554	+};
	1555	+
	1556	+struct hns_roce_cfg_entry_size {
	1557	+ __le32 type;
	1558	+ __le32 rsv[4];
	1559	+ __le32 size;
	1560	+};
	1561	+
1303	1562	#define CFG_SGID_TB_TABLE_IDX_S 0
1304	1563	#define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1305	1564
..	..	@@ -1318,6 +1577,155 @@
1318	1577	#define CFG_SMAC_TB_VF_SMAC_H_S 0
1319	1578	#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1320	1579
	1580	+#define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
	1581	+struct hns_roce_query_pf_caps_a {
	1582	+ u8 number_ports;
	1583	+ u8 local_ca_ack_delay;
	1584	+ __le16 max_sq_sg;
	1585	+ __le16 max_sq_inline;
	1586	+ __le16 max_rq_sg;
	1587	+ __le32 max_extend_sg;
	1588	+ __le16 num_qpc_timer;
	1589	+ __le16 num_cqc_timer;
	1590	+ __le16 max_srq_sges;
	1591	+ u8 num_aeq_vectors;
	1592	+ u8 num_other_vectors;
	1593	+ u8 max_sq_desc_sz;
	1594	+ u8 max_rq_desc_sz;
	1595	+ u8 max_srq_desc_sz;
	1596	+ u8 cqe_sz;
	1597	+};
	1598	+
	1599	+struct hns_roce_query_pf_caps_b {
	1600	+ u8 mtpt_entry_sz;
	1601	+ u8 irrl_entry_sz;
	1602	+ u8 trrl_entry_sz;
	1603	+ u8 cqc_entry_sz;
	1604	+ u8 srqc_entry_sz;
	1605	+ u8 idx_entry_sz;
	1606	+ u8 sccc_sz;
	1607	+ u8 max_mtu;
	1608	+ __le16 qpc_sz;
	1609	+ __le16 qpc_timer_entry_sz;
	1610	+ __le16 cqc_timer_entry_sz;
	1611	+ u8 min_cqes;
	1612	+ u8 min_wqes;
	1613	+ __le32 page_size_cap;
	1614	+ u8 pkey_table_len;
	1615	+ u8 phy_num_uars;
	1616	+ u8 ctx_hop_num;
	1617	+ u8 pbl_hop_num;
	1618	+};
	1619	+
	1620	+struct hns_roce_query_pf_caps_c {
	1621	+ __le32 cap_flags_num_pds;
	1622	+ __le32 max_gid_num_cqs;
	1623	+ __le32 cq_depth;
	1624	+ __le32 num_mrws;
	1625	+ __le32 ord_num_qps;
	1626	+ __le16 sq_depth;
	1627	+ __le16 rq_depth;
	1628	+};
	1629	+
	1630	+#define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
	1631	+#define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
	1632	+
	1633	+#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
	1634	+#define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
	1635	+
	1636	+#define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
	1637	+#define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
	1638	+
	1639	+#define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
	1640	+#define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
	1641	+
	1642	+#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
	1643	+#define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
	1644	+
	1645	+#define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
	1646	+#define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
	1647	+
	1648	+#define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
	1649	+#define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
	1650	+
	1651	+#define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
	1652	+#define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
	1653	+
	1654	+struct hns_roce_query_pf_caps_d {
	1655	+ __le32 wq_hop_num_max_srqs;
	1656	+ __le16 srq_depth;
	1657	+ __le16 cap_flags_ex;
	1658	+ __le32 num_ceqs_ceq_depth;
	1659	+ __le32 arm_st_aeq_depth;
	1660	+ __le32 num_uars_rsv_pds;
	1661	+ __le32 rsv_uars_rsv_qps;
	1662	+};
	1663	+#define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
	1664	+#define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
	1665	+
	1666	+#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
	1667	+#define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
	1668	+
	1669	+#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
	1670	+#define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
	1671	+
	1672	+#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
	1673	+#define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
	1674	+
	1675	+
	1676	+#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
	1677	+#define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
	1678	+
	1679	+#define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
	1680	+#define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
	1681	+
	1682	+#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
	1683	+#define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
	1684	+
	1685	+#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
	1686	+#define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
	1687	+
	1688	+#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
	1689	+#define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
	1690	+
	1691	+#define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
	1692	+#define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
	1693	+
	1694	+#define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
	1695	+#define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
	1696	+
	1697	+#define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
	1698	+#define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
	1699	+
	1700	+#define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
	1701	+#define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
	1702	+
	1703	+struct hns_roce_query_pf_caps_e {
	1704	+ __le32 chunk_size_shift_rsv_mrws;
	1705	+ __le32 rsv_cqs;
	1706	+ __le32 rsv_srqs;
	1707	+ __le32 rsv_lkey;
	1708	+ __le16 ceq_max_cnt;
	1709	+ __le16 ceq_period;
	1710	+ __le16 aeq_max_cnt;
	1711	+ __le16 aeq_period;
	1712	+};
	1713	+
	1714	+#define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
	1715	+#define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
	1716	+
	1717	+#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
	1718	+#define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
	1719	+
	1720	+#define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
	1721	+#define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
	1722	+
	1723	+#define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
	1724	+#define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
	1725	+
	1726	+#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
	1727	+#define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
	1728	+
1321	1729	struct hns_roce_cmq_desc {
1322	1730	__le16 opcode;
1323	1731	__le16 flag;
..	..	@@ -1330,18 +1738,6 @@
1330	1738
1331	1739	#define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1332	1740	#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1333		-
1334		-#define HNS_ROCE_VF_MB4_TAG_MASK 0xFFFFFF00
1335		-#define HNS_ROCE_VF_MB4_TAG_SHIFT 8
1336		-
1337		-#define HNS_ROCE_VF_MB4_CMD_MASK 0xFF
1338		-#define HNS_ROCE_VF_MB4_CMD_SHIFT 0
1339		-
1340		-#define HNS_ROCE_VF_MB5_EVENT_MASK 0x10000
1341		-#define HNS_ROCE_VF_MB5_EVENT_SHIFT 16
1342		-
1343		-#define HNS_ROCE_VF_MB5_TOKEN_MASK 0xFFFF
1344		-#define HNS_ROCE_VF_MB5_TOKEN_SHIFT 0
1345	1741
1346	1742	struct hns_roce_v2_cmq_ring {
1347	1743	dma_addr_t desc_dma_addr;
..	..	@@ -1387,6 +1783,7 @@
1387	1783	#define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1388	1784
1389	1785	struct hns_roce_v2_priv {
	1786	+ struct hnae3_handle *handle;
1390	1787	struct hns_roce_v2_cmq cmq;
1391	1788	struct hns_roce_link_table tsq;
1392	1789	struct hns_roce_link_table tpq;
..	..	@@ -1402,8 +1799,8 @@
1402	1799	__le32 byte_28;
1403	1800	__le32 byte_32;
1404	1801	__le32 byte_36;
1405		- __le32 nxt_eqe_ba0;
1406		- __le32 nxt_eqe_ba1;
	1802	+ __le32 byte_40;
	1803	+ __le32 byte_44;
1407	1804	__le32 rsv[5];
1408	1805	};
1409	1806
..	..	@@ -1545,6 +1942,9 @@
1545	1942	#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1546	1943	#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1547	1944
	1945	+#define HNS_ROCE_EQC_EQE_SIZE_S 20
	1946	+#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
	1947	+
1548	1948	#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1549	1949	#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1550	1950
..	..	@@ -1566,4 +1966,35 @@
1566	1966	#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1567	1967	#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1568	1968
	1969	+#define MAX_SERVICE_LEVEL 0x7
	1970	+
	1971	+struct hns_roce_wqe_atomic_seg {
	1972	+ __le64 fetchadd_swap_data;
	1973	+ __le64 cmp_data;
	1974	+};
	1975	+
	1976	+struct hns_roce_sccc_clr {
	1977	+ __le32 qpn;
	1978	+ __le32 rsv[5];
	1979	+};
	1980	+
	1981	+struct hns_roce_sccc_clr_done {
	1982	+ __le32 clr_done;
	1983	+ __le32 rsv[5];
	1984	+};
	1985	+
	1986	+int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
	1987	+ int *buffer);
	1988	+
	1989	+static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
	1990	+ void __iomem *dest)
	1991	+{
	1992	+ struct hns_roce_v2_priv *priv = hr_dev->priv;
	1993	+ struct hnae3_handle *handle = priv->handle;
	1994	+ const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
	1995	+
	1996	+ if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
	1997	+ hns_roce_write64_k(val, dest);
	1998	+}
	1999	+
1569	2000	#endif