forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
....@@ -57,9 +57,11 @@
5757 
5858 #define VMW_BINDING_RT_BIT     0
5959 #define VMW_BINDING_PS_BIT     1
60
-#define VMW_BINDING_SO_BIT     2
60
+#define VMW_BINDING_SO_T_BIT   2
6161 #define VMW_BINDING_VB_BIT     3
62
-#define VMW_BINDING_NUM_BITS   4
62
+#define VMW_BINDING_UAV_BIT    4
63
+#define VMW_BINDING_CS_UAV_BIT 5
64
+#define VMW_BINDING_NUM_BITS   6
6365 
6466 #define VMW_BINDING_PS_SR_BIT  0
6567 
....@@ -75,6 +77,8 @@
7577  * @vertex_buffers: Vertex buffer bindings.
7678  * @index_buffer: Index buffer binding.
7779  * @per_shader: Per shader-type bindings.
80
+ * @ua_views: UAV bindings.
81
+ * @so_state: StreamOutput bindings.
7882  * @dirty: Bitmap tracking per binding-type changes that have not yet
7983  * been emitted to the device.
8084  * @dirty_vb: Bitmap tracking individual vertex buffer binding changes that
....@@ -95,10 +99,12 @@
9599 	struct vmw_ctx_bindinfo_view render_targets[SVGA3D_RT_MAX];
96100 	struct vmw_ctx_bindinfo_tex texture_units[SVGA3D_NUM_TEXTURE_UNITS];
97101 	struct vmw_ctx_bindinfo_view ds_view;
98
-	struct vmw_ctx_bindinfo_so so_targets[SVGA3D_DX_MAX_SOTARGETS];
102
+	struct vmw_ctx_bindinfo_so_target so_targets[SVGA3D_DX_MAX_SOTARGETS];
99103 	struct vmw_ctx_bindinfo_vb vertex_buffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
100104 	struct vmw_ctx_bindinfo_ib index_buffer;
101
-	struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE_DX10];
105
+	struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE];
106
+	struct vmw_ctx_bindinfo_uav ua_views[VMW_MAX_UAV_BIND_TYPE];
107
+	struct vmw_ctx_bindinfo_so so_state;
102108 
103109 	unsigned long dirty;
104110 	DECLARE_BITMAP(dirty_vb, SVGA3D_DX_MAX_VERTEXBUFFERS);
....@@ -115,12 +121,16 @@
115121 static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind);
116122 static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind);
117123 static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind);
118
-static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind);
124
+static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind);
119125 static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs);
120126 static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi,
121127 				       bool rebind);
122128 static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind);
123129 static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind);
130
+static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
131
+static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
132
+static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind);
133
+
124134 static void vmw_binding_build_asserts(void) __attribute__ ((unused));
125135 
126136 typedef int (*vmw_scrub_func)(struct vmw_ctx_bindinfo *, bool);
....@@ -151,6 +161,9 @@
151161 	offsetof(struct vmw_ctx_binding_state, per_shader[0].shader),
152162 	offsetof(struct vmw_ctx_binding_state, per_shader[1].shader),
153163 	offsetof(struct vmw_ctx_binding_state, per_shader[2].shader),
164
+	offsetof(struct vmw_ctx_binding_state, per_shader[3].shader),
165
+	offsetof(struct vmw_ctx_binding_state, per_shader[4].shader),
166
+	offsetof(struct vmw_ctx_binding_state, per_shader[5].shader),
154167 };
155168 static const size_t vmw_binding_rt_offsets[] = {
156169 	offsetof(struct vmw_ctx_binding_state, render_targets),
....@@ -162,6 +175,9 @@
162175 	offsetof(struct vmw_ctx_binding_state, per_shader[0].const_buffers),
163176 	offsetof(struct vmw_ctx_binding_state, per_shader[1].const_buffers),
164177 	offsetof(struct vmw_ctx_binding_state, per_shader[2].const_buffers),
178
+	offsetof(struct vmw_ctx_binding_state, per_shader[3].const_buffers),
179
+	offsetof(struct vmw_ctx_binding_state, per_shader[4].const_buffers),
180
+	offsetof(struct vmw_ctx_binding_state, per_shader[5].const_buffers),
165181 };
166182 static const size_t vmw_binding_dx_ds_offsets[] = {
167183 	offsetof(struct vmw_ctx_binding_state, ds_view),
....@@ -170,8 +186,11 @@
170186 	offsetof(struct vmw_ctx_binding_state, per_shader[0].shader_res),
171187 	offsetof(struct vmw_ctx_binding_state, per_shader[1].shader_res),
172188 	offsetof(struct vmw_ctx_binding_state, per_shader[2].shader_res),
189
+	offsetof(struct vmw_ctx_binding_state, per_shader[3].shader_res),
190
+	offsetof(struct vmw_ctx_binding_state, per_shader[4].shader_res),
191
+	offsetof(struct vmw_ctx_binding_state, per_shader[5].shader_res),
173192 };
174
-static const size_t vmw_binding_so_offsets[] = {
193
+static const size_t vmw_binding_so_target_offsets[] = {
175194 	offsetof(struct vmw_ctx_binding_state, so_targets),
176195 };
177196 static const size_t vmw_binding_vb_offsets[] = {
....@@ -179,6 +198,15 @@
179198 };
180199 static const size_t vmw_binding_ib_offsets[] = {
181200 	offsetof(struct vmw_ctx_binding_state, index_buffer),
201
+};
202
+static const size_t vmw_binding_uav_offsets[] = {
203
+	offsetof(struct vmw_ctx_binding_state, ua_views[0].views),
204
+};
205
+static const size_t vmw_binding_cs_uav_offsets[] = {
206
+	offsetof(struct vmw_ctx_binding_state, ua_views[1].views),
207
+};
208
+static const size_t vmw_binding_so_offsets[] = {
209
+	offsetof(struct vmw_ctx_binding_state, so_state),
182210 };
183211 
184212 static const struct vmw_binding_info vmw_binding_infos[] = {
....@@ -214,10 +242,10 @@
214242 		.size = sizeof(struct vmw_ctx_bindinfo_view),
215243 		.offsets = vmw_binding_dx_ds_offsets,
216244 		.scrub_func = vmw_binding_scrub_dx_rt},
217
-	[vmw_ctx_binding_so] = {
218
-		.size = sizeof(struct vmw_ctx_bindinfo_so),
219
-		.offsets = vmw_binding_so_offsets,
220
-		.scrub_func = vmw_binding_scrub_so},
245
+	[vmw_ctx_binding_so_target] = {
246
+		.size = sizeof(struct vmw_ctx_bindinfo_so_target),
247
+		.offsets = vmw_binding_so_target_offsets,
248
+		.scrub_func = vmw_binding_scrub_so_target},
221249 	[vmw_ctx_binding_vb] = {
222250 		.size = sizeof(struct vmw_ctx_bindinfo_vb),
223251 		.offsets = vmw_binding_vb_offsets,
....@@ -226,6 +254,18 @@
226254 		.size = sizeof(struct vmw_ctx_bindinfo_ib),
227255 		.offsets = vmw_binding_ib_offsets,
228256 		.scrub_func = vmw_binding_scrub_ib},
257
+	[vmw_ctx_binding_uav] = {
258
+		.size = sizeof(struct vmw_ctx_bindinfo_view),
259
+		.offsets = vmw_binding_uav_offsets,
260
+		.scrub_func = vmw_binding_scrub_uav},
261
+	[vmw_ctx_binding_cs_uav] = {
262
+		.size = sizeof(struct vmw_ctx_bindinfo_view),
263
+		.offsets = vmw_binding_cs_uav_offsets,
264
+		.scrub_func = vmw_binding_scrub_cs_uav},
265
+	[vmw_ctx_binding_so] = {
266
+		.size = sizeof(struct vmw_ctx_bindinfo_so),
267
+		.offsets = vmw_binding_so_offsets,
268
+		.scrub_func = vmw_binding_scrub_so},
229269 };
230270 
231271 /**
....@@ -309,6 +349,18 @@
309349 	loc->scrubbed = false;
310350 	list_add(&loc->ctx_list, &cbs->list);
311351 	INIT_LIST_HEAD(&loc->res_list);
352
+}
353
+
354
+/**
355
+ * vmw_binding_add_uav_index - Add UAV index for tracking.
356
+ * @cbs: Pointer to the context binding state tracker.
357
+ * @slot: UAV type to which bind this index.
358
+ * @index: The splice index to track.
359
+ */
360
+void vmw_binding_add_uav_index(struct vmw_ctx_binding_state *cbs, uint32 slot,
361
+			       uint32 index)
362
+{
363
+	cbs->ua_views[slot].index = index;
312364 }
313365 
314366 /**
....@@ -450,6 +502,10 @@
450502 		vmw_binding_transfer(to, from, entry);
451503 		vmw_binding_drop(entry);
452504 	}
505
+
506
+	/* Also transfer uav splice indices */
507
+	to->ua_views[0].index = from->ua_views[0].index;
508
+	to->ua_views[1].index = from->ua_views[1].index;
453509 }
454510 
455511 /**
....@@ -499,12 +555,9 @@
499555 		SVGA3dCmdSetShader body;
500556 	} *cmd;
501557 
502
-	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
503
-	if (unlikely(cmd == NULL)) {
504
-		DRM_ERROR("Failed reserving FIFO space for shader "
505
-			  "unbinding.\n");
558
+	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
559
+	if (unlikely(cmd == NULL))
506560 		return -ENOMEM;
507
-	}
508561 
509562 	cmd->header.id = SVGA_3D_CMD_SET_SHADER;
510563 	cmd->header.size = sizeof(cmd->body);
....@@ -534,12 +587,9 @@
534587 		SVGA3dCmdSetRenderTarget body;
535588 	} *cmd;
536589 
537
-	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
538
-	if (unlikely(cmd == NULL)) {
539
-		DRM_ERROR("Failed reserving FIFO space for render target "
540
-			  "unbinding.\n");
590
+	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
591
+	if (unlikely(cmd == NULL))
541592 		return -ENOMEM;
542
-	}
543593 
544594 	cmd->header.id = SVGA_3D_CMD_SETRENDERTARGET;
545595 	cmd->header.size = sizeof(cmd->body);
....@@ -576,12 +626,9 @@
576626 		} body;
577627 	} *cmd;
578628 
579
-	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
580
-	if (unlikely(cmd == NULL)) {
581
-		DRM_ERROR("Failed reserving FIFO space for texture "
582
-			  "unbinding.\n");
629
+	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
630
+	if (unlikely(cmd == NULL))
583631 		return -ENOMEM;
584
-	}
585632 
586633 	cmd->header.id = SVGA_3D_CMD_SETTEXTURESTATE;
587634 	cmd->header.size = sizeof(cmd->body);
....@@ -610,12 +657,10 @@
610657 		SVGA3dCmdDXSetShader body;
611658 	} *cmd;
612659 
613
-	cmd = vmw_fifo_reserve_dx(dev_priv, sizeof(*cmd), bi->ctx->id);
614
-	if (unlikely(cmd == NULL)) {
615
-		DRM_ERROR("Failed reserving FIFO space for DX shader "
616
-			  "unbinding.\n");
660
+	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
661
+	if (unlikely(cmd == NULL))
617662 		return -ENOMEM;
618
-	}
663
+
619664 	cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER;
620665 	cmd->header.size = sizeof(cmd->body);
621666 	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
....@@ -641,12 +686,9 @@
641686 		SVGA3dCmdDXSetSingleConstantBuffer body;
642687 	} *cmd;
643688 
644
-	cmd = vmw_fifo_reserve_dx(dev_priv, sizeof(*cmd), bi->ctx->id);
645
-	if (unlikely(cmd == NULL)) {
646
-		DRM_ERROR("Failed reserving FIFO space for DX shader "
647
-			  "unbinding.\n");
689
+	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
690
+	if (unlikely(cmd == NULL))
648691 		return -ENOMEM;
649
-	}
650692 
651693 	cmd->header.id = SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER;
652694 	cmd->header.size = sizeof(cmd->body);
....@@ -768,12 +810,9 @@
768810 
769811 	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
770812 	cmd_size = sizeof(*cmd) + view_id_size;
771
-	cmd = vmw_fifo_reserve_dx(ctx->dev_priv, cmd_size, ctx->id);
772
-	if (unlikely(cmd == NULL)) {
773
-		DRM_ERROR("Failed reserving FIFO space for DX shader"
774
-			  " resource binding.\n");
813
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
814
+	if (unlikely(cmd == NULL))
775815 		return -ENOMEM;
776
-	}
777816 
778817 	cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER_RESOURCES;
779818 	cmd->header.size = sizeof(cmd->body) + view_id_size;
....@@ -807,12 +846,9 @@
807846 	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
808847 	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
809848 	cmd_size = sizeof(*cmd) + view_id_size;
810
-	cmd = vmw_fifo_reserve_dx(ctx->dev_priv, cmd_size, ctx->id);
811
-	if (unlikely(cmd == NULL)) {
812
-		DRM_ERROR("Failed reserving FIFO space for DX render-target"
813
-			  " binding.\n");
849
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
850
+	if (unlikely(cmd == NULL))
814851 		return -ENOMEM;
815
-	}
816852 
817853 	cmd->header.id = SVGA_3D_CMD_DX_SET_RENDERTARGETS;
818854 	cmd->header.size = sizeof(cmd->body) + view_id_size;
....@@ -848,8 +884,8 @@
848884 				   const struct vmw_ctx_bindinfo *bi,
849885 				   u32 max_num)
850886 {
851
-	const struct vmw_ctx_bindinfo_so *biso =
852
-		container_of(bi, struct vmw_ctx_bindinfo_so, bi);
887
+	const struct vmw_ctx_bindinfo_so_target *biso =
888
+		container_of(bi, struct vmw_ctx_bindinfo_so_target, bi);
853889 	unsigned long i;
854890 	SVGA3dSoTarget *so_buffer = (SVGA3dSoTarget *) cbs->bind_cmd_buffer;
855891 
....@@ -874,11 +910,11 @@
874910 }
875911 
876912 /**
877
- * vmw_binding_emit_set_so - Issue delayed streamout binding commands
913
+ * vmw_emit_set_so_target - Issue delayed streamout binding commands
878914  *
879915  * @cbs: Pointer to the context's struct vmw_ctx_binding_state
880916  */
881
-static int vmw_emit_set_so(struct vmw_ctx_binding_state *cbs)
917
+static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs)
882918 {
883919 	const struct vmw_ctx_bindinfo *loc = &cbs->so_targets[0].bi;
884920 	struct {
....@@ -894,12 +930,9 @@
894930 
895931 	so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
896932 	cmd_size = sizeof(*cmd) + so_target_size;
897
-	cmd = vmw_fifo_reserve_dx(ctx->dev_priv, cmd_size, ctx->id);
898
-	if (unlikely(cmd == NULL)) {
899
-		DRM_ERROR("Failed reserving FIFO space for DX SO target"
900
-			  " binding.\n");
933
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
934
+	if (unlikely(cmd == NULL))
901935 		return -ENOMEM;
902
-	}
903936 
904937 	cmd->header.id = SVGA_3D_CMD_DX_SET_SOTARGETS;
905938 	cmd->header.size = sizeof(cmd->body) + so_target_size;
....@@ -1011,12 +1044,9 @@
10111044 
10121045 	set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
10131046 	cmd_size = sizeof(*cmd) + set_vb_size;
1014
-	cmd = vmw_fifo_reserve_dx(ctx->dev_priv, cmd_size, ctx->id);
1015
-	if (unlikely(cmd == NULL)) {
1016
-		DRM_ERROR("Failed reserving FIFO space for DX vertex buffer"
1017
-			  " binding.\n");
1047
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
1048
+	if (unlikely(cmd == NULL))
10181049 		return -ENOMEM;
1019
-	}
10201050 
10211051 	cmd->header.id = SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS;
10221052 	cmd->header.size = sizeof(cmd->body) + set_vb_size;
....@@ -1027,6 +1057,66 @@
10271057 	vmw_fifo_commit(ctx->dev_priv, cmd_size);
10281058 	bitmap_clear(cbs->dirty_vb,
10291059 		     cbs->bind_first_slot, cbs->bind_cmd_count);
1060
+
1061
+	return 0;
1062
+}
1063
+
1064
+static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs)
1065
+{
1066
+	const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[0].views[0].bi;
1067
+	struct {
1068
+		SVGA3dCmdHeader header;
1069
+		SVGA3dCmdDXSetUAViews body;
1070
+	} *cmd;
1071
+	size_t cmd_size, view_id_size;
1072
+	const struct vmw_resource *ctx = vmw_cbs_context(cbs);
1073
+
1074
+	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1075
+	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1076
+	cmd_size = sizeof(*cmd) + view_id_size;
1077
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
1078
+	if (!cmd)
1079
+		return -ENOMEM;
1080
+
1081
+	cmd->header.id = SVGA_3D_CMD_DX_SET_UA_VIEWS;
1082
+	cmd->header.size = sizeof(cmd->body) + view_id_size;
1083
+
1084
+	/* Splice index is specified user-space   */
1085
+	cmd->body.uavSpliceIndex = cbs->ua_views[0].index;
1086
+
1087
+	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1088
+
1089
+	vmw_fifo_commit(ctx->dev_priv, cmd_size);
1090
+
1091
+	return 0;
1092
+}
1093
+
1094
+static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs)
1095
+{
1096
+	const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[1].views[0].bi;
1097
+	struct {
1098
+		SVGA3dCmdHeader header;
1099
+		SVGA3dCmdDXSetCSUAViews body;
1100
+	} *cmd;
1101
+	size_t cmd_size, view_id_size;
1102
+	const struct vmw_resource *ctx = vmw_cbs_context(cbs);
1103
+
1104
+	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1105
+	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1106
+	cmd_size = sizeof(*cmd) + view_id_size;
1107
+	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);
1108
+	if (!cmd)
1109
+		return -ENOMEM;
1110
+
1111
+	cmd->header.id = SVGA_3D_CMD_DX_SET_CS_UA_VIEWS;
1112
+	cmd->header.size = sizeof(cmd->body) + view_id_size;
1113
+
1114
+	/* Start index is specified user-space */
1115
+	cmd->body.startIndex = cbs->ua_views[1].index;
1116
+
1117
+	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1118
+
1119
+	vmw_fifo_commit(ctx->dev_priv, cmd_size);
10301120 
10311121 	return 0;
10321122 }
....@@ -1056,11 +1146,17 @@
10561146 		case VMW_BINDING_PS_BIT:
10571147 			ret = vmw_binding_emit_dirty_ps(cbs);
10581148 			break;
1059
-		case VMW_BINDING_SO_BIT:
1060
-			ret = vmw_emit_set_so(cbs);
1149
+		case VMW_BINDING_SO_T_BIT:
1150
+			ret = vmw_emit_set_so_target(cbs);
10611151 			break;
10621152 		case VMW_BINDING_VB_BIT:
10631153 			ret = vmw_emit_set_vb(cbs);
1154
+			break;
1155
+		case VMW_BINDING_UAV_BIT:
1156
+			ret = vmw_emit_set_uav(cbs);
1157
+			break;
1158
+		case VMW_BINDING_CS_UAV_BIT:
1159
+			ret = vmw_emit_set_cs_uav(cbs);
10641160 			break;
10651161 		default:
10661162 			BUG();
....@@ -1115,18 +1211,18 @@
11151211 }
11161212 
11171213 /**
1118
- * vmw_binding_scrub_so - Schedule a dx streamoutput buffer binding
1214
+ * vmw_binding_scrub_so_target - Schedule a dx streamoutput buffer binding
11191215  * scrub from a context
11201216  *
11211217  * @bi: single binding information.
11221218  * @rebind: Whether to issue a bind instead of scrub command.
11231219  */
1124
-static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind)
1220
+static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind)
11251221 {
11261222 	struct vmw_ctx_binding_state *cbs =
11271223 		vmw_context_binding_state(bi->ctx);
11281224 
1129
-	__set_bit(VMW_BINDING_SO_BIT, &cbs->dirty);
1225
+	__set_bit(VMW_BINDING_SO_T_BIT, &cbs->dirty);
11301226 
11311227 	return 0;
11321228 }
....@@ -1167,12 +1263,10 @@
11671263 		SVGA3dCmdDXSetIndexBuffer body;
11681264 	} *cmd;
11691265 
1170
-	cmd = vmw_fifo_reserve_dx(dev_priv, sizeof(*cmd), bi->ctx->id);
1171
-	if (unlikely(cmd == NULL)) {
1172
-		DRM_ERROR("Failed reserving FIFO space for DX index buffer "
1173
-			  "binding.\n");
1266
+	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
1267
+	if (unlikely(cmd == NULL))
11741268 		return -ENOMEM;
1175
-	}
1269
+
11761270 	cmd->header.id = SVGA_3D_CMD_DX_SET_INDEX_BUFFER;
11771271 	cmd->header.size = sizeof(cmd->body);
11781272 	if (rebind) {
....@@ -1185,6 +1279,49 @@
11851279 		cmd->body.offset = 0;
11861280 	}
11871281 
1282
+	vmw_fifo_commit(dev_priv, sizeof(*cmd));
1283
+
1284
+	return 0;
1285
+}
1286
+
1287
+static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
1288
+{
1289
+	struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
1290
+
1291
+	__set_bit(VMW_BINDING_UAV_BIT, &cbs->dirty);
1292
+	return 0;
1293
+}
1294
+
1295
+static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
1296
+{
1297
+	struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
1298
+
1299
+	__set_bit(VMW_BINDING_CS_UAV_BIT, &cbs->dirty);
1300
+	return 0;
1301
+}
1302
+
1303
+/**
1304
+ * vmw_binding_scrub_so - Scrub a streamoutput binding from context.
1305
+ * @bi: Single binding information.
1306
+ * @rebind: Whether to issue a bind instead of scrub command.
1307
+ */
1308
+static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind)
1309
+{
1310
+	struct vmw_ctx_bindinfo_so *binding =
1311
+		container_of(bi, typeof(*binding), bi);
1312
+	struct vmw_private *dev_priv = bi->ctx->dev_priv;
1313
+	struct {
1314
+		SVGA3dCmdHeader header;
1315
+		SVGA3dCmdDXSetStreamOutput body;
1316
+	} *cmd;
1317
+
1318
+	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);
1319
+	if (!cmd)
1320
+		return -ENOMEM;
1321
+
1322
+	cmd->header.id = SVGA_3D_CMD_DX_SET_STREAMOUTPUT;
1323
+	cmd->header.size = sizeof(cmd->body);
1324
+	cmd->body.soid = rebind ? bi->res->id : SVGA3D_INVALID_ID;
11881325 	vmw_fifo_commit(dev_priv, sizeof(*cmd));
11891326 
11901327 	return 0;
....@@ -1269,6 +1406,34 @@
12691406 		vmw_binding_drop(entry);
12701407 }
12711408 
1409
+/**
1410
+ * vmw_binding_dirtying - Return whether a binding type is dirtying its resource
1411
+ * @binding_type: The binding type
1412
+ *
1413
+ * Each time a resource is put on the validation list as the result of a
1414
+ * context binding referencing it, we need to determine whether that resource
1415
+ * will be dirtied (written to by the GPU) as a result of the corresponding
1416
+ * GPU operation. Currently rendertarget-, depth-stencil-, stream-output-target
1417
+ * and unordered access view bindings are capable of dirtying its resource.
1418
+ *
1419
+ * Return: Whether the binding type dirties the resource its binding points to.
1420
+ */
1421
+u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
1422
+{
1423
+	static u32 is_binding_dirtying[vmw_ctx_binding_max] = {
1424
+		[vmw_ctx_binding_rt] = VMW_RES_DIRTY_SET,
1425
+		[vmw_ctx_binding_dx_rt] = VMW_RES_DIRTY_SET,
1426
+		[vmw_ctx_binding_ds] = VMW_RES_DIRTY_SET,
1427
+		[vmw_ctx_binding_so_target] = VMW_RES_DIRTY_SET,
1428
+		[vmw_ctx_binding_uav] = VMW_RES_DIRTY_SET,
1429
+		[vmw_ctx_binding_cs_uav] = VMW_RES_DIRTY_SET,
1430
+	};
1431
+
1432
+	/* Review this function as new bindings are added. */
1433
+	BUILD_BUG_ON(vmw_ctx_binding_max != 14);
1434
+	return is_binding_dirtying[binding_type];
1435
+}
1436
+
12721437 /*
12731438  * This function is unused at run-time, and only used to hold various build
12741439  * asserts important for code optimization assumptions.