modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/via/via_irq.c
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@@ -35,8 +35,10 @@
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  * The refresh rate is also calculated for video playback sync purposes.
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  */
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-#include <drm/drmP.h>
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+#include <drm/drm_device.h>
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+#include <drm/drm_vblank.h>
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 #include <drm/via_drm.h>
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+
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 #include "via_drv.h"
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 #define VIA_REG_INTERRUPT       0x200
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@@ -108,7 +110,7 @@
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 	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
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 	int i;
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-	status = VIA_READ(VIA_REG_INTERRUPT);
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+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
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 	if (status & VIA_IRQ_VBLANK_PENDING) {
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 		atomic_inc(&dev_priv->vbl_received);
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 		if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
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@@ -143,7 +145,7 @@
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 	}
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 	/* Acknowledge interrupts */
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-	VIA_WRITE(VIA_REG_INTERRUPT, status);
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+	via_write(dev_priv, VIA_REG_INTERRUPT, status);
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 	if (handled)
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@@ -158,8 +160,8 @@
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 	if (dev_priv) {
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 		/* Acknowledge interrupts */
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-		status = VIA_READ(VIA_REG_INTERRUPT);
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-		VIA_WRITE(VIA_REG_INTERRUPT, status |
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+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+		via_write(dev_priv, VIA_REG_INTERRUPT, status |
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 			  dev_priv->irq_pending_mask);
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 	}
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 }
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@@ -174,11 +176,11 @@
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 		return -EINVAL;
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 	}
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-	status = VIA_READ(VIA_REG_INTERRUPT);
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-	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
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+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
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-	VIA_WRITE8(0x83d4, 0x11);
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-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
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+	via_write8(dev_priv, 0x83d4, 0x11);
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+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
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 	return 0;
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 }
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@@ -188,11 +190,11 @@
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 	drm_via_private_t *dev_priv = dev->dev_private;
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 	u32 status;
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-	status = VIA_READ(VIA_REG_INTERRUPT);
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-	VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
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+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+	via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
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-	VIA_WRITE8(0x83d4, 0x11);
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-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
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+	via_write8(dev_priv, 0x83d4, 0x11);
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+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
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 	if (pipe != 0)
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 		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
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@@ -233,12 +235,12 @@
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 	cur_irq = dev_priv->via_irqs + real_irq;
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 	if (masks[real_irq][2] && !force_sequence) {
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-		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
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-			    ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
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+		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
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+			    ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
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 			     masks[irq][4]));
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 		cur_irq_sequence = atomic_read(&cur_irq->irq_received);
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 	} else {
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-		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
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+		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
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 			    (((cur_irq_sequence =
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 			       atomic_read(&cur_irq->irq_received)) -
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 			      *sequence) <= (1 << 23)));
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@@ -292,8 +294,8 @@
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 		dev_priv->last_vblank_valid = 0;
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 		/* Clear VSync interrupt regs */
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-		status = VIA_READ(VIA_REG_INTERRUPT);
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-		VIA_WRITE(VIA_REG_INTERRUPT, status &
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+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+		via_write(dev_priv, VIA_REG_INTERRUPT, status &
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 			  ~(dev_priv->irq_enable_mask));
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 		/* Clear bits if they're already high */
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@@ -310,13 +312,13 @@
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 	if (!dev_priv)
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 		return -EINVAL;
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-	status = VIA_READ(VIA_REG_INTERRUPT);
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-	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
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+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
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 		  | dev_priv->irq_enable_mask);
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 	/* Some magic, oh for some data sheets ! */
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-	VIA_WRITE8(0x83d4, 0x11);
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-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
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+	via_write8(dev_priv, 0x83d4, 0x11);
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+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
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 	return 0;
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 }
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@@ -331,11 +333,11 @@
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 		/* Some more magic, oh for some data sheets ! */
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-		VIA_WRITE8(0x83d4, 0x11);
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-		VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
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+		via_write8(dev_priv, 0x83d4, 0x11);
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+		via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
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-		status = VIA_READ(VIA_REG_INTERRUPT);
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-		VIA_WRITE(VIA_REG_INTERRUPT, status &
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+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
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+		via_write(dev_priv, VIA_REG_INTERRUPT, status &
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 			  ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
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 	}
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 }