modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/v3d/v3d_mmu.c
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@@ -40,7 +40,7 @@
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 	ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
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 			 V3D_MMU_CTL_TLB_CLEARING), 100);
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 	if (ret)
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-		dev_err(v3d->dev, "TLB clear wait idle pre-wait failed\n");
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+		dev_err(v3d->drm.dev, "TLB clear wait idle pre-wait failed\n");
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 	V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) |
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 		  V3D_MMU_CTL_TLB_CLEAR);
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@@ -52,14 +52,14 @@
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 	ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
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 			 V3D_MMU_CTL_TLB_CLEARING), 100);
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 	if (ret) {
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-		dev_err(v3d->dev, "TLB clear wait idle failed\n");
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+		dev_err(v3d->drm.dev, "TLB clear wait idle failed\n");
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 		return ret;
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 	}
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 	ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) &
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 			 V3D_MMUC_CONTROL_FLUSHING), 100);
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 	if (ret)
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-		dev_err(v3d->dev, "MMUC flush wait idle failed\n");
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+		dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n");
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 	return ret;
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 }
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@@ -69,10 +69,13 @@
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 	V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT);
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 	V3D_WRITE(V3D_MMU_CTL,
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 		  V3D_MMU_CTL_ENABLE |
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-		  V3D_MMU_CTL_PT_INVALID |
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+		  V3D_MMU_CTL_PT_INVALID_ENABLE |
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 		  V3D_MMU_CTL_PT_INVALID_ABORT |
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+		  V3D_MMU_CTL_PT_INVALID_INT |
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 		  V3D_MMU_CTL_WRITE_VIOLATION_ABORT |
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-		  V3D_MMU_CTL_CAP_EXCEEDED_ABORT);
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+		  V3D_MMU_CTL_WRITE_VIOLATION_INT |
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+		  V3D_MMU_CTL_CAP_EXCEEDED_ABORT |
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+		  V3D_MMU_CTL_CAP_EXCEEDED_INT);
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 	V3D_WRITE(V3D_MMU_ILLEGAL_ADDR,
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 		  (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) |
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 		  V3D_MMU_ILLEGAL_ADDR_ENABLE);
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@@ -83,40 +86,40 @@
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 void v3d_mmu_insert_ptes(struct v3d_bo *bo)
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 {
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-	struct v3d_dev *v3d = to_v3d_dev(bo->base.dev);
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+	struct drm_gem_shmem_object *shmem_obj = &bo->base;
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+	struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev);
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 	u32 page = bo->node.start;
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 	u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
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-	unsigned int count;
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-	struct scatterlist *sgl;
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+	struct sg_dma_page_iter dma_iter;
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-	for_each_sg(bo->sgt->sgl, sgl, bo->sgt->nents, count) {
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-		u32 page_address = sg_dma_address(sgl) >> V3D_MMU_PAGE_SHIFT;
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+	for_each_sgtable_dma_page(shmem_obj->sgt, &dma_iter, 0) {
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+		dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
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+		u32 page_address = dma_addr >> V3D_MMU_PAGE_SHIFT;
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 		u32 pte = page_prot | page_address;
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 		u32 i;
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-		BUG_ON(page_address + (sg_dma_len(sgl) >> V3D_MMU_PAGE_SHIFT) >=
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+		BUG_ON(page_address + (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) >=
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 		       BIT(24));
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-
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-		for (i = 0; i < sg_dma_len(sgl) >> V3D_MMU_PAGE_SHIFT; i++)
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+		for (i = 0; i < PAGE_SIZE >> V3D_MMU_PAGE_SHIFT; i++)
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 			v3d->pt[page++] = pte + i;
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 	}
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 	WARN_ON_ONCE(page - bo->node.start !=
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-		     bo->base.size >> V3D_MMU_PAGE_SHIFT);
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+		     shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT);
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 	if (v3d_mmu_flush_all(v3d))
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-		dev_err(v3d->dev, "MMU flush timeout\n");
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+		dev_err(v3d->drm.dev, "MMU flush timeout\n");
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 }
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 void v3d_mmu_remove_ptes(struct v3d_bo *bo)
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 {
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-	struct v3d_dev *v3d = to_v3d_dev(bo->base.dev);
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-	u32 npages = bo->base.size >> V3D_MMU_PAGE_SHIFT;
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+	struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev);
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+	u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT;
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 	u32 page;
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 	for (page = bo->node.start; page < bo->node.start + npages; page++)
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 		v3d->pt[page] = 0;
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 	if (v3d_mmu_flush_all(v3d))
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-		dev_err(v3d->dev, "MMU flush timeout\n");
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+		dev_err(v3d->drm.dev, "MMU flush timeout\n");
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 }