modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/v3d/v3d_debugfs.c
..
..
@@ -6,7 +6,8 @@
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 #include <linux/debugfs.h>
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 #include <linux/pm_runtime.h>
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 #include <linux/seq_file.h>
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-#include <drm/drmP.h>
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+
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+#include <drm/drm_debugfs.h>
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11
 
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 #include "v3d_drv.h"
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 #include "v3d_regs.h"
..
..
@@ -26,6 +27,11 @@
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 	REGDEF(V3D_HUB_IDENT3),
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 	REGDEF(V3D_HUB_INT_STS),
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 	REGDEF(V3D_HUB_INT_MSK_STS),
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+
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+	REGDEF(V3D_MMU_CTL),
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+	REGDEF(V3D_MMU_VIO_ADDR),
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+	REGDEF(V3D_MMU_VIO_ID),
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+	REGDEF(V3D_MMU_DEBUG_INFO),
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 };
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36
 
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 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
..
..
@@ -50,12 +56,25 @@
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 	REGDEF(V3D_PTB_BPCA),
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 	REGDEF(V3D_PTB_BPCS),
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-	REGDEF(V3D_MMU_CTL),
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-	REGDEF(V3D_MMU_VIO_ADDR),
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-
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 	REGDEF(V3D_GMP_STATUS),
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 	REGDEF(V3D_GMP_CFG),
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 	REGDEF(V3D_GMP_VIO_ADDR),
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+
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+	REGDEF(V3D_ERR_FDBGO),
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+	REGDEF(V3D_ERR_FDBGB),
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+	REGDEF(V3D_ERR_FDBGS),
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+	REGDEF(V3D_ERR_STAT),
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+};
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+
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+static const struct v3d_reg_def v3d_csd_reg_defs[] = {
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+	REGDEF(V3D_CSD_STATUS),
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+	REGDEF(V3D_CSD_CURRENT_CFG0),
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+	REGDEF(V3D_CSD_CURRENT_CFG1),
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+	REGDEF(V3D_CSD_CURRENT_CFG2),
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+	REGDEF(V3D_CSD_CURRENT_CFG3),
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+	REGDEF(V3D_CSD_CURRENT_CFG4),
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+	REGDEF(V3D_CSD_CURRENT_CFG5),
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+	REGDEF(V3D_CSD_CURRENT_CFG6),
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 };
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79
 
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 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
..
..
@@ -89,6 +108,17 @@
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 				   V3D_CORE_READ(core,
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 						 v3d_core_reg_defs[i].reg));
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 		}
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+
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+		if (v3d_has_csd(v3d)) {
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+			for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
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+				seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
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+					   core,
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+					   v3d_csd_reg_defs[i].name,
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+					   v3d_csd_reg_defs[i].reg,
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+					   V3D_CORE_READ(core,
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+							 v3d_csd_reg_defs[i].reg));
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+			}
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+		}
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 	}
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123
 
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 	return 0;
..
..
@@ -102,7 +132,7 @@
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 	u32 ident0, ident1, ident2, ident3, cores;
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 	int ret, core;
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-	ret = pm_runtime_get_sync(v3d->dev);
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+	ret = pm_runtime_get_sync(v3d->drm.dev);
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 	if (ret < 0)
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 		return ret;
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..
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@@ -157,8 +187,8 @@
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 			   (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
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 	}
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-	pm_runtime_mark_last_busy(v3d->dev);
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-	pm_runtime_put_autosuspend(v3d->dev);
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+	pm_runtime_mark_last_busy(v3d->drm.dev);
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+	pm_runtime_put_autosuspend(v3d->drm.dev);
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 	return 0;
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 }
..
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@@ -179,16 +209,59 @@
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 	return 0;
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 }
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211
 
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+static int v3d_measure_clock(struct seq_file *m, void *unused)
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+{
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+	struct drm_info_node *node = (struct drm_info_node *)m->private;
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+	struct drm_device *dev = node->minor->dev;
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+	struct v3d_dev *v3d = to_v3d_dev(dev);
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+	uint32_t cycles;
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+	int core = 0;
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+	int measure_ms = 1000;
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+	int ret;
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+
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+	ret = pm_runtime_get_sync(v3d->drm.dev);
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+	if (ret < 0)
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+		return ret;
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+
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+	if (v3d->ver >= 40) {
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+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
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+			       V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
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+					     V3D_PCTR_S0));
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+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
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+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
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+	} else {
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+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
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+			       V3D_PCTR_CYCLE_COUNT);
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+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
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+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
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+			       V3D_V3_PCTR_0_EN_ENABLE |
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+			       1);
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+	}
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+	msleep(measure_ms);
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+	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
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+
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+	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
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+		   cycles,
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+		   cycles / (measure_ms * 1000),
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+		   (cycles / (measure_ms * 100)) % 10);
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+
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+	pm_runtime_mark_last_busy(v3d->drm.dev);
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+	pm_runtime_put_autosuspend(v3d->drm.dev);
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+
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+	return 0;
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+}
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+
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 static const struct drm_info_list v3d_debugfs_list[] = {
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 	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
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 	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
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+	{"measure_clock", v3d_measure_clock, 0},
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 	{"bo_stats", v3d_debugfs_bo_stats, 0},
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 };
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-int
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+void
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 v3d_debugfs_init(struct drm_minor *minor)
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 {
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-	return drm_debugfs_create_files(v3d_debugfs_list,
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-					ARRAY_SIZE(v3d_debugfs_list),
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-					minor->debugfs_root, minor);
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+	drm_debugfs_create_files(v3d_debugfs_list,
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+				 ARRAY_SIZE(v3d_debugfs_list),
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+				 minor->debugfs_root, minor);
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 }