modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/tegra/sor.h
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@@ -1,9 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2013 NVIDIA Corporation
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef DRM_TEGRA_SOR_H
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@@ -42,6 +39,7 @@
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 #define  SOR_STATE_ASY_CRC_MODE_NON_ACTIVE	(0x2 << 6)
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 #define  SOR_STATE_ASY_CRC_MODE_COMPLETE	(0x1 << 6)
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 #define  SOR_STATE_ASY_CRC_MODE_ACTIVE		(0x0 << 6)
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+#define  SOR_STATE_ASY_SUBOWNER_MASK		(0x3 << 4)
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 #define  SOR_STATE_ASY_OWNER_MASK		0xf
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 #define  SOR_STATE_ASY_OWNER(x)			(((x) & 0xf) << 0)
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@@ -286,10 +284,12 @@
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 #define  SOR_DP_PADCTL_CM_TXD_2		(1 << 6)
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 #define  SOR_DP_PADCTL_CM_TXD_1		(1 << 5)
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 #define  SOR_DP_PADCTL_CM_TXD_0		(1 << 4)
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+#define  SOR_DP_PADCTL_CM_TXD(x)	(1 << (4 + (x)))
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 #define  SOR_DP_PADCTL_PD_TXD_3		(1 << 3)
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 #define  SOR_DP_PADCTL_PD_TXD_0		(1 << 2)
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 #define  SOR_DP_PADCTL_PD_TXD_1		(1 << 1)
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 #define  SOR_DP_PADCTL_PD_TXD_2		(1 << 0)
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+#define  SOR_DP_PADCTL_PD_TXD(x)	(1 << (0 + (x)))
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 #define SOR_DP_PADCTL1 0x5d
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@@ -364,11 +364,27 @@
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 #define  INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
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 #define  INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
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+#define SOR_HDMI_ACR_CTRL 0xb1
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+
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+#define SOR_HDMI_ACR_0320_SUBPACK_LOW 0xb2
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+#define  SOR_HDMI_ACR_SUBPACK_LOW_SB1(x) (((x) & 0xff) << 24)
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+
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+#define SOR_HDMI_ACR_0320_SUBPACK_HIGH 0xb3
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+#define  SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE (1 << 31)
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+
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+#define SOR_HDMI_ACR_0441_SUBPACK_LOW 0xb4
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+#define SOR_HDMI_ACR_0441_SUBPACK_HIGH 0xb5
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+
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 #define SOR_HDMI_CTRL 0xc0
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 #define  SOR_HDMI_CTRL_ENABLE (1 << 30)
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 #define  SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
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 #define  SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)
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 #define  SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
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+
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+#define SOR_HDMI_SPARE 0xcb
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+#define  SOR_HDMI_SPARE_ACR_PRIORITY_HIGH (1 << 31)
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+#define  SOR_HDMI_SPARE_CTS_RESET(x) (((x) & 0x7) << 16)
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+#define  SOR_HDMI_SPARE_HW_CTS_ENABLE (1 << 0)
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 #define SOR_REFCLK 0xe6
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 #define  SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8)
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@@ -378,10 +394,62 @@
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 #define  SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
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 #define  SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0)
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+#define SOR_AUDIO_CNTRL 0xfc
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+#define  SOR_AUDIO_CNTRL_INJECT_NULLSMPL (1 << 29)
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+#define  SOR_AUDIO_CNTRL_SOURCE_SELECT(x) (((x) & 0x3) << 20)
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+#define   SOURCE_SELECT_MASK 0x3
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+#define   SOURCE_SELECT_HDA 0x2
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+#define   SOURCE_SELECT_SPDIF 0x1
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+#define   SOURCE_SELECT_AUTO 0x0
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+#define  SOR_AUDIO_CNTRL_AFIFO_FLUSH (1 << 12)
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+
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+#define SOR_AUDIO_SPARE 0xfe
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+#define  SOR_AUDIO_SPARE_HBR_ENABLE (1 << 27)
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+
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+#define SOR_AUDIO_NVAL_0320 0xff
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+#define SOR_AUDIO_NVAL_0441 0x100
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+#define SOR_AUDIO_NVAL_0882 0x101
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+#define SOR_AUDIO_NVAL_1764 0x102
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+#define SOR_AUDIO_NVAL_0480 0x103
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+#define SOR_AUDIO_NVAL_0960 0x104
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+#define SOR_AUDIO_NVAL_1920 0x105
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+
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+#define SOR_AUDIO_HDA_CODEC_SCRATCH0 0x10a
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+#define  SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
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+#define  SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
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+
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+#define SOR_AUDIO_HDA_ELD_BUFWR 0x10c
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+#define  SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x) (((x) & 0xff) << 8)
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+#define  SOR_AUDIO_HDA_ELD_BUFWR_DATA(x) (((x) & 0xff) << 0)
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+
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+#define SOR_AUDIO_HDA_PRESENSE 0x10d
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+#define  SOR_AUDIO_HDA_PRESENSE_ELDV (1 << 1)
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+#define  SOR_AUDIO_HDA_PRESENSE_PD (1 << 0)
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+
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+#define SOR_AUDIO_AVAL_0320 0x10f
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+#define SOR_AUDIO_AVAL_0441 0x110
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+#define SOR_AUDIO_AVAL_0882 0x111
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+#define SOR_AUDIO_AVAL_1764 0x112
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+#define SOR_AUDIO_AVAL_0480 0x113
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+#define SOR_AUDIO_AVAL_0960 0x114
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+#define SOR_AUDIO_AVAL_1920 0x115
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+
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+#define SOR_INT_STATUS 0x11c
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+#define  SOR_INT_CODEC_CP_REQUEST (1 << 2)
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+#define  SOR_INT_CODEC_SCRATCH1 (1 << 1)
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+#define  SOR_INT_CODEC_SCRATCH0 (1 << 0)
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+
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+#define SOR_INT_MASK 0x11d
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+#define SOR_INT_ENABLE 0x11e
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+
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 #define SOR_HDMI_VSI_INFOFRAME_CTRL 0x123
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 #define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
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 #define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
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+#define SOR_HDMI_AUDIO_N 0x13c
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+#define SOR_HDMI_AUDIO_N_LOOKUP (1 << 28)
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+#define SOR_HDMI_AUDIO_N_RESET (1 << 20)
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+
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 #define SOR_HDMI2_CTRL 0x13e
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 #define  SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
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 #define  SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)