~hc/RK356X_SDK_RELEASE.git

..	..	@@ -11,10 +11,10 @@
11	11	#include <linux/pm_runtime.h>
12	12	#include <linux/regmap.h>
13	13
14		-#include <drm/drmP.h>
15	14	#include <drm/drm_atomic_helper.h>
16	15	#include <drm/drm_crtc_helper.h>
17	16	#include <drm/drm_of.h>
	17	+#include <drm/drm_probe_helper.h>
18	18
19	19	#include <uapi/linux/videodev2.h>
20	20
..	..	@@ -29,14 +29,84 @@
29	29	816, 864, 0, 576, 580, 586, 625, 0,
30	30	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
31	31	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
32		- .vrefresh = 50, 0, },
	32	+ 0, },
33	33
34	34	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
35	35	815, 858, 0, 480, 480, 486, 525, 0,
36	36	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC \|
37	37	DRM_MODE_FLAG_INTERLACE \| DRM_MODE_FLAG_DBLCLK),
38		- .vrefresh = 60, 0, },
	38	+ 0, },
39	39	};
	40	+
	41	+struct env_config {
	42	+ u32 offset;
	43	+ u32 value;
	44	+};
	45	+
	46	+static struct env_config ntsc_bt656_config[] = {
	47	+ { BT656_DECODER_CROP, 0x00000000 },
	48	+ { BT656_DECODER_SIZE, 0x01e002d0 },
	49	+ { BT656_DECODER_HTOTAL_HS_END, 0x035a003e },
	50	+ { BT656_DECODER_VACT_ST_HACT_ST, 0x00160069 },
	51	+ { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 },
	52	+ { BT656_DECODER_VS_ST_END_F1, 0x01060109 },
	53	+ { BT656_DECODER_DBG_REG, 0x024002d0 },
	54	+ { BT656_DECODER_CTRL, 0x00000009 },
	55	+};
	56	+
	57	+static struct env_config ntsc_tve_config[] = {
	58	+ { TVE_MODE_CTRL, 0x000af906 },
	59	+ { TVE_HOR_TIMING1, 0x00c07a81 },
	60	+ { TVE_HOR_TIMING2, 0x169810fc },
	61	+ { TVE_HOR_TIMING3, 0x96b40000 },
	62	+ { TVE_SUB_CAR_FRQ, 0x21f07bd7 },
	63	+ { TVE_IMAGE_POSITION, 0x001500d6 },
	64	+ { TVE_ROUTING, 0x10088880 },
	65	+ { TVE_SYNC_ADJUST, 0x00000000 },
	66	+ { TVE_STATUS, 0x00000000 },
	67	+ { TVE_CTRL, 0x00000000 },
	68	+ { TVE_INTR_STATUS, 0x00000000 },
	69	+ { TVE_INTR_EN, 0x00000000 },
	70	+ { TVE_INTR_CLR, 0x00000000 },
	71	+ { TVE_COLOR_BUSRT_SAT, 0x0052543c },
	72	+ { TVE_CHROMA_BANDWIDTH, 0x00000002 },
	73	+ { TVE_BRIGHTNESS_CONTRAST, 0x00008300 },
	74	+ { TVE_CLAMP, 0x00000000 },
	75	+};
	76	+
	77	+static struct env_config pal_bt656_config[] = {
	78	+ { BT656_DECODER_CROP, 0x00000000 },
	79	+ { BT656_DECODER_SIZE, 0x024002d0 },
	80	+ { BT656_DECODER_HTOTAL_HS_END, 0x0360003f },
	81	+ { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f },
	82	+ { BT656_DECODER_VTOTAL_VS_END, 0x02710003 },
	83	+ { BT656_DECODER_VS_ST_END_F1, 0x0138013b },
	84	+ { BT656_DECODER_DBG_REG, 0x024002d0 },
	85	+ { BT656_DECODER_CTRL, 0x00000009 },
	86	+};
	87	+
	88	+static struct env_config pal_tve_config[] = {
	89	+ { TVE_MODE_CTRL, 0x010ab906 },
	90	+ { TVE_HOR_TIMING1, 0x00c28381 },
	91	+ { TVE_HOR_TIMING2, 0x267d111d },
	92	+ { TVE_HOR_TIMING3, 0x66c00880 },
	93	+ { TVE_SUB_CAR_FRQ, 0x2a098acb },
	94	+ { TVE_IMAGE_POSITION, 0x001500f6 },
	95	+ { TVE_ROUTING, 0x10008882 },
	96	+ { TVE_SYNC_ADJUST, 0x00000000 },
	97	+ { TVE_STATUS, 0x000000b0 },
	98	+ { TVE_CTRL, 0x00000000 },
	99	+ { TVE_INTR_STATUS, 0x00000000 },
	100	+ { TVE_INTR_EN, 0x00000000 },
	101	+ { TVE_INTR_CLR, 0x00000000 },
	102	+ { TVE_COLOR_BUSRT_SAT, 0x00356245 },
	103	+ { TVE_CHROMA_BANDWIDTH, 0x00000022 },
	104	+ { TVE_BRIGHTNESS_CONTRAST, 0x0000aa00 },
	105	+ { TVE_CLAMP, 0x00000000 },
	106	+};
	107	+
	108	+#define BT656_ENV_CONFIG_SIZE (sizeof(ntsc_bt656_config) / sizeof(struct env_config))
	109	+#define TVE_ENV_CONFIG_SIZE (sizeof(ntsc_tve_config) / sizeof(struct env_config))
40	110
41	111	#define tve_writel(offset, v) writel_relaxed(v, tve->regbase + (offset))
42	112	#define tve_readl(offset) readl_relaxed(tve->regbase + (offset))
..	..	@@ -54,6 +124,14 @@
54	124	int input_format;
55	125	int soc_type;
56	126	};
	127	+
	128	+static void tve_write_block(struct rockchip_tve tve, struct env_config config, int len)
	129	+{
	130	+ int i;
	131	+
	132	+ for (i = 0; i < len; i++)
	133	+ tve_writel(config[i].offset, config[i].value);
	134	+}
57	135
58	136	static int
59	137	rockchip_tve_get_modes(struct drm_connector *connector)
..	..	@@ -107,61 +185,106 @@
107	185
108	186	static void tve_set_mode(struct rockchip_tve *tve)
109	187	{
	188	+ struct env_config bt656_cfg, tve_cfg;
110	189	int mode = tve->tv_format;
111	190
112		- dev_dbg(tve->dev, "tve set mode:%d\n", mode);
113		- if (tve->input_format == INPUT_FORMAT_RGB)
114		- tve_writel(TV_CTRL, v_CVBS_MODE(mode) \| v_CLK_UPSTREAM_EN(2) \|
115		- v_TIMING_EN(2) \| v_LUMA_FILTER_GAIN(0) \|
116		- v_LUMA_FILTER_UPSAMPLE(1) \| v_CSC_PATH(0));
117		- else
118		- tve_writel(TV_CTRL, v_CVBS_MODE(mode) \| v_CLK_UPSTREAM_EN(2) \|
119		- v_TIMING_EN(2) \| v_LUMA_FILTER_GAIN(0) \|
120		- v_LUMA_FILTER_UPSAMPLE(1) \| v_CSC_PATH(3));
	191	+ if (tve->soc_type == SOC_RK3528) {
	192	+ tve_writel(TVE_LUMA_FILTER1, tve->lumafilter0);
	193	+ tve_writel(TVE_LUMA_FILTER2, tve->lumafilter1);
	194	+ tve_writel(TVE_LUMA_FILTER3, tve->lumafilter2);
	195	+ tve_writel(TVE_LUMA_FILTER4, tve->lumafilter3);
	196	+ tve_writel(TVE_LUMA_FILTER5, tve->lumafilter4);
	197	+ tve_writel(TVE_LUMA_FILTER6, tve->lumafilter5);
	198	+ tve_writel(TVE_LUMA_FILTER7, tve->lumafilter6);
	199	+ tve_writel(TVE_LUMA_FILTER8, tve->lumafilter7);
	200	+ } else {
	201	+ dev_dbg(tve->dev, "tve set mode:%d\n", mode);
	202	+ if (tve->input_format == INPUT_FORMAT_RGB)
	203	+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) \| v_CLK_UPSTREAM_EN(2) \|
	204	+ v_TIMING_EN(2) \| v_LUMA_FILTER_GAIN(0) \|
	205	+ v_LUMA_FILTER_UPSAMPLE(1) \| v_CSC_PATH(0));
	206	+ else
	207	+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) \| v_CLK_UPSTREAM_EN(2) \|
	208	+ v_TIMING_EN(2) \| v_LUMA_FILTER_GAIN(0) \|
	209	+ v_LUMA_FILTER_UPSAMPLE(1) \| v_CSC_PATH(3));
121	210
122		- tve_writel(TV_LUMA_FILTER0, tve->lumafilter0);
123		- tve_writel(TV_LUMA_FILTER1, tve->lumafilter1);
124		- tve_writel(TV_LUMA_FILTER2, tve->lumafilter2);
	211	+ tve_writel(TV_LUMA_FILTER0, tve->lumafilter0);
	212	+ tve_writel(TV_LUMA_FILTER1, tve->lumafilter1);
	213	+ tve_writel(TV_LUMA_FILTER2, tve->lumafilter2);
	214	+ }
125	215
126	216	if (mode == TVOUT_CVBS_NTSC) {
127	217	dev_dbg(tve->dev, "NTSC MODE\n");
128		- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) \| v_Y_IRE_7_5(1) \|
129		- v_Y_AGC_PULSE_ON(0) \| v_Y_VIDEO_ON(1) \|
130		- v_YPP_MODE(1) \| v_Y_SYNC_ON(1) \| v_PIC_MODE(mode));
131		- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) \|
132		- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
133		- tve_writel(TV_SATURATION, 0x0042543C);
134		- if (tve->test_mode)
135		- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
136		- else
137		- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
138	218
139		- tve_writel(TV_FREQ_SC, 0x21F07BD7);
140		- tve_writel(TV_SYNC_TIMING, 0x00C07a81);
141		- tve_writel(TV_ADJ_TIMING, 0x96B40000 \| 0x70);
142		- tve_writel(TV_ACT_ST, 0x001500D6);
143		- tve_writel(TV_ACT_TIMING, 0x069800FC \| (1 << 12) \| (1 << 28));
	219	+ if (tve->soc_type == SOC_RK3528) {
	220	+ bt656_cfg = ntsc_bt656_config;
	221	+ tve_cfg = ntsc_tve_config;
144	222
	223	+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
	224	+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
	225	+ } else {
	226	+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) \| v_Y_IRE_7_5(1) \|
	227	+ v_Y_AGC_PULSE_ON(0) \| v_Y_VIDEO_ON(1) \|
	228	+ v_YPP_MODE(1) \| v_Y_SYNC_ON(1) \| v_PIC_MODE(mode));
	229	+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) \|
	230	+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
	231	+ tve_writel(TV_SATURATION, 0x0042543C);
	232	+ if (tve->test_mode)
	233	+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
	234	+ else
	235	+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
	236	+
	237	+ tve_writel(TV_FREQ_SC, 0x21F07BD7);
	238	+ tve_writel(TV_SYNC_TIMING, 0x00C07a81);
	239	+ tve_writel(TV_ADJ_TIMING, 0x96B40000 \| 0x70);
	240	+ tve_writel(TV_ACT_ST, 0x001500D6);
	241	+ tve_writel(TV_ACT_TIMING, 0x069800FC \| (1 << 12) \| (1 << 28));
	242	+ }
145	243	} else if (mode == TVOUT_CVBS_PAL) {
146	244	dev_dbg(tve->dev, "PAL MODE\n");
147		- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) \| v_Y_IRE_7_5(0) \|
148		- v_Y_AGC_PULSE_ON(0) \| v_Y_VIDEO_ON(1) \|
149		- v_YPP_MODE(1) \| v_Y_SYNC_ON(1) \| v_PIC_MODE(mode));
150		- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) \|
151		- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
152	245
153		- tve_writel(TV_SATURATION, tve->saturation);
154		- tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast);
	246	+ if (tve->soc_type == SOC_RK3528) {
	247	+ bt656_cfg = pal_bt656_config;
	248	+ tve_cfg = pal_tve_config;
155	249
156		- tve_writel(TV_FREQ_SC, 0x2A098ACB);
157		- tve_writel(TV_SYNC_TIMING, 0x00C28381);
158		- tve_writel(TV_ADJ_TIMING, (0xc << 28) \| 0x06c00800 \| 0x80);
159		- tve_writel(TV_ACT_ST, 0x001500F6);
160		- tve_writel(TV_ACT_TIMING, 0x0694011D \| (1 << 12) \| (2 << 28));
	250	+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
	251	+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
	252	+ } else {
	253	+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) \| v_Y_IRE_7_5(0) \|
	254	+ v_Y_AGC_PULSE_ON(0) \| v_Y_VIDEO_ON(1) \|
	255	+ v_YPP_MODE(1) \| v_Y_SYNC_ON(1) \| v_PIC_MODE(mode));
	256	+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) \|
	257	+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
161	258
162		- tve_writel(TV_ADJ_TIMING, tve->adjtiming);
163		- tve_writel(TV_ACT_TIMING, 0x0694011D \|
164		- (1 << 12) \| (2 << 28));
	259	+ tve_writel(TV_SATURATION, tve->saturation);
	260	+ tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast);
	261	+
	262	+ tve_writel(TV_FREQ_SC, 0x2A098ACB);
	263	+ tve_writel(TV_SYNC_TIMING, 0x00C28381);
	264	+ tve_writel(TV_ADJ_TIMING, (0xc << 28) \| 0x06c00800 \| 0x80);
	265	+ tve_writel(TV_ACT_ST, 0x001500F6);
	266	+ tve_writel(TV_ACT_TIMING, 0x0694011D \| (1 << 12) \| (2 << 28));
	267	+
	268	+ tve_writel(TV_ADJ_TIMING, tve->adjtiming);
	269	+ tve_writel(TV_ACT_TIMING, 0x0694011D \| (1 << 12) \| (2 << 28));
	270	+ }
	271	+ }
	272	+
	273	+ if (tve->soc_type == SOC_RK3528) {
	274	+ u32 upsample_mode = 0;
	275	+ u32 mask = 0;
	276	+ u32 val = 0;
	277	+ bool upsample_en;
	278	+
	279	+ upsample_en = tve->upsample_mode ? 1 : 0;
	280	+ if (upsample_en)
	281	+ upsample_mode = tve->upsample_mode - 1;
	282	+ mask = m_TVE_DCLK_POL \| m_TVE_DCLK_EN \| m_DCLK_UPSAMPLE_2X4X \|
	283	+ m_DCLK_UPSAMPLE_EN \| m_TVE_MODE \| m_TVE_EN;
	284	+ val = v_TVE_DCLK_POL(0) \| v_TVE_DCLK_EN(1) \| v_DCLK_UPSAMPLE_2X4X(upsample_mode) \|
	285	+ v_DCLK_UPSAMPLE_EN(upsample_en) \| v_TVE_MODE(tve->tv_format) \| v_TVE_EN(1);
	286	+
	287	+ tve_dac_grf_writel(RK3528_VO_GRF_CVBS_CON, (mask << 16) \| val);
165	288	}
166	289	}
167	290
..	..	@@ -178,36 +301,57 @@
178	301	u32 mask = 0;
179	302	u32 val = 0;
180	303	u32 grfreg = 0;
	304	+ u32 offset = 0;
181	305
182	306	if (enable) {
183	307	dev_dbg(tve->dev, "dac enable\n");
184	308
185		- mask = m_VBG_EN \| m_DAC_EN \| m_DAC_GAIN;
186	309	if (tve->soc_type == SOC_RK3036) {
	310	+ mask = m_VBG_EN \| m_DAC_EN \| m_DAC_GAIN;
187	311	val = m_VBG_EN \| m_DAC_EN \| v_DAC_GAIN(tve->daclevel);
188	312	grfreg = RK3036_GRF_SOC_CON3;
189	313	} else if (tve->soc_type == SOC_RK312X) {
	314	+ mask = m_VBG_EN \| m_DAC_EN \| m_DAC_GAIN;
190	315	val = m_VBG_EN \| m_DAC_EN \| v_DAC_GAIN(tve->daclevel);
191	316	grfreg = RK312X_GRF_TVE_CON;
192	317	} else if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328) {
193	318	val = v_CUR_REG(tve->dac1level) \| v_DR_PWR_DOWN(0) \| v_BG_PWR_DOWN(0);
	319	+ offset = VDAC_VDAC1;
	320	+ } else if (tve->soc_type == SOC_RK3528) {
	321	+ /*
	322	+ * Reset the vdac
	323	+ */
	324	+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(0) \| v_DIGITAL_RST(0));
	325	+ msleep(20);
	326	+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(1) \| v_DIGITAL_RST(1));
	327	+
	328	+ tve_dac_writel(VDAC_CURRENT_CTRL, v_OUT_CURRENT(tve->vdac_out_current));
	329	+
	330	+ val = v_REF_VOLTAGE(7) \| v_DAC_PWN(1) \| v_BIAS_PWN(1);
	331	+ offset = VDAC_PWM_REF_CTRL;
194	332	}
195	333	} else {
196	334	dev_dbg(tve->dev, "dac disable\n");
197	335
198		- mask = m_VBG_EN \| m_DAC_EN;
199		- if (tve->soc_type == SOC_RK312X)
	336	+ if (tve->soc_type == SOC_RK312X) {
	337	+ mask = m_VBG_EN \| m_DAC_EN;
200	338	grfreg = RK312X_GRF_TVE_CON;
201		- else if (tve->soc_type == SOC_RK3036)
	339	+ } else if (tve->soc_type == SOC_RK3036) {
	340	+ mask = m_VBG_EN \| m_DAC_EN;
202	341	grfreg = RK3036_GRF_SOC_CON3;
203		- else if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328)
	342	+ } else if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328) {
204	343	val = v_CUR_REG(tve->dac1level) \| m_DR_PWR_DOWN \| m_BG_PWR_DOWN;
	344	+ offset = VDAC_VDAC1;
	345	+ } else if (tve->soc_type == SOC_RK3528) {
	346	+ val = v_DAC_PWN(0) \| v_BIAS_PWN(0);
	347	+ offset = VDAC_PWM_REF_CTRL;
	348	+ }
205	349	}
206	350
207	351	if (grfreg)
208	352	tve_dac_grf_writel(grfreg, (mask << 16) \| val);
209	353	else if (tve->vdacbase)
210		- tve_dac_writel(VDAC_VDAC1, val);
	354	+ tve_dac_writel(offset, val);
211	355	}
212	356
213	357	static int cvbs_set_disable(struct rockchip_tve *tve)
..	..	@@ -229,6 +373,18 @@
229	373	return 0;
230	374	}
231	375
	376	+/*
	377	+ * RK3528 supports bt656 to cvbs, and the others support rgb to cvbs.
	378	+ *
	379	+ * ┌──────────┐
	380	+ * │ rgb data ├─────────────────────────────────────┐
	381	+ * └──────────┘ │
	382	+ * ▼
	383	+ * ┌────────────┐ ┌───────────────┐ ┌───────────────────┐ ┌──────┐ ┌────────┐
	384	+ * │ bt656 data ├───►│ bt656 decoder ├───►│ cvbs(tve) encoder ├───►│ vdac ├───►│ screen │
	385	+ * └────────────┘ └───────────────┘ └───────────────────┘ └──────┘ └────────┘
	386	+ *
	387	+ */
232	388	static int cvbs_set_enable(struct rockchip_tve *tve)
233	389	{
234	390	int ret = 0;
..	..	@@ -242,8 +398,9 @@
242	398	dev_err(tve->dev, "failed to get pm runtime: %d\n", ret);
243	399	return ret;
244	400	}
245		- dac_enable(tve, true);
246	401	tve_set_mode(tve);
	402	+ msleep(1000);
	403	+ dac_enable(tve, true);
247	404	tve->enable = 1;
248	405
249	406	return 0;
..	..	@@ -309,6 +466,7 @@
309	466	struct drm_connector_state *conn_state)
310	467	{
311	468	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
	469	+ struct rockchip_tve *tve = encoder_to_tve(encoder);
312	470	struct drm_connector *connector = conn_state->connector;
313	471	struct drm_display_info *info = &connector->display_info;
314	472
..	..	@@ -319,6 +477,12 @@
319	477	else
320	478	s->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
321	479
	480	+ /*
	481	+ * For RK3528:
	482	+ * VOP -> BT656 output -> BT656 decoder -> TVE encoder -> CVBS output
	483	+ */
	484	+ if (tve->soc_type == SOC_RK3528)
	485	+ s->output_if \|= VOP_OUTPUT_IF_BT656;
322	486	s->color_space = V4L2_COLORSPACE_SMPTE170M;
323	487	s->tv_state = &conn_state->tv;
324	488
..	..	@@ -354,8 +518,118 @@
354	518	.atomic_check = rockchip_tve_encoder_atomic_check,
355	519	};
356	520
357		-static int tve_parse_dt(struct device_node *np,
358		- struct rockchip_tve *tve)
	521	+static int tve_read_otp_by_name(struct rockchip_tve tve, char name, u8 *val, u8 default_val)
	522	+{
	523	+ struct nvmem_cell *cell;
	524	+ size_t len;
	525	+ unsigned char *efuse_buf;
	526	+ int ret = -EINVAL;
	527	+
	528	+ *val = default_val;
	529	+ cell = nvmem_cell_get(tve->dev, name);
	530	+ if (!IS_ERR(cell)) {
	531	+ efuse_buf = nvmem_cell_read(cell, &len);
	532	+ nvmem_cell_put(cell);
	533	+ if (!IS_ERR(efuse_buf)) {
	534	+ *val = efuse_buf[0];
	535	+ kfree(efuse_buf);
	536	+ return 0;
	537	+ }
	538	+ }
	539	+
	540	+ dev_err(tve->dev, "failed to read %s from otp, use default\n", name);
	541	+
	542	+ return ret;
	543	+}
	544	+
	545	+static int tve_parse_dt(struct device_node np, struct rockchip_tve tve)
	546	+{
	547	+ int ret, val;
	548	+ u8 out_current, version;
	549	+
	550	+ ret = of_property_read_u32(np, "rockchip,tvemode", &val);
	551	+ if (ret < 0) {
	552	+ tve->preferred_mode = 0;
	553	+ } else if (val > 1) {
	554	+ dev_err(tve->dev, "tve mode value invalid\n");
	555	+ return -EINVAL;
	556	+ }
	557	+ tve->preferred_mode = val;
	558	+
	559	+ ret = of_property_read_u32(np, "rockchip,lumafilter0", &val);
	560	+ if (val == 0 \|\| ret < 0)
	561	+ return -EINVAL;
	562	+ tve->lumafilter0 = val;
	563	+
	564	+ ret = of_property_read_u32(np, "rockchip,lumafilter1", &val);
	565	+ if (val == 0 \|\| ret < 0)
	566	+ return -EINVAL;
	567	+ tve->lumafilter1 = val;
	568	+
	569	+ ret = of_property_read_u32(np, "rockchip,lumafilter2", &val);
	570	+ if (val == 0 \|\| ret < 0)
	571	+ return -EINVAL;
	572	+ tve->lumafilter2 = val;
	573	+
	574	+ ret = of_property_read_u32(np, "rockchip,lumafilter3", &val);
	575	+ if (val == 0 \|\| ret < 0)
	576	+ return -EINVAL;
	577	+ tve->lumafilter3 = val;
	578	+
	579	+ ret = of_property_read_u32(np, "rockchip,lumafilter4", &val);
	580	+ if (val == 0 \|\| ret < 0)
	581	+ return -EINVAL;
	582	+ tve->lumafilter4 = val;
	583	+
	584	+ ret = of_property_read_u32(np, "rockchip,lumafilter5", &val);
	585	+ if (val == 0 \|\| ret < 0)
	586	+ return -EINVAL;
	587	+ tve->lumafilter5 = val;
	588	+
	589	+ ret = of_property_read_u32(np, "rockchip,lumafilter6", &val);
	590	+ if (val == 0 \|\| ret < 0)
	591	+ return -EINVAL;
	592	+ tve->lumafilter6 = val;
	593	+
	594	+ ret = of_property_read_u32(np, "rockchip,lumafilter7", &val);
	595	+ if (val == 0 \|\| ret < 0)
	596	+ return -EINVAL;
	597	+ tve->lumafilter7 = val;
	598	+
	599	+ ret = of_property_read_u32(np, "rockchip,tve-upsample", &val);
	600	+ if (val > DCLK_UPSAMPLEx4 \|\| ret < 0)
	601	+ return -EINVAL;
	602	+ tve->upsample_mode = val;
	603	+
	604	+ /*
	605	+ * Read vdac output current from OTP if exists, and the default
	606	+ * current val is 0xd2.
	607	+ */
	608	+ ret = tve_read_otp_by_name(tve, "out-current", &out_current, 0xd2);
	609	+ if (!ret) {
	610	+ if (out_current) {
	611	+ /*
	612	+ * If test version is 0x0, the value of vdac out current
	613	+ * needs to be reduced by one.
	614	+ */
	615	+ ret = tve_read_otp_by_name(tve, "version", &version, 0x0);
	616	+ if (!ret) {
	617	+ if (version == 0x0)
	618	+ out_current -= 1;
	619	+ }
	620	+ } else {
	621	+ /*
	622	+ * If the current value read from OTP is 0, set it to default.
	623	+ */
	624	+ out_current = 0xd2;
	625	+ }
	626	+ }
	627	+ tve->vdac_out_current = out_current;
	628	+
	629	+ return 0;
	630	+}
	631	+
	632	+static int tve_parse_dt_legacy(struct device_node np, struct rockchip_tve tve)
359	633	{
360	634	int ret, val;
361	635	u32 getdac = 0;
..	..	@@ -441,9 +715,52 @@
441	715	return 0;
442	716	}
443	717
	718	+static bool tve_check_lumafilter(struct rockchip_tve *tve)
	719	+{
	720	+ int lumafilter[8] = {INT_MAX};
	721	+
	722	+ /*
	723	+ * The default lumafilter value is 0. If lumafilter value
	724	+ * is equal to the dts value, uboot logo is enabled.
	725	+ */
	726	+ if (tve->soc_type == SOC_RK3528) {
	727	+ lumafilter[0] = tve_readl(TVE_LUMA_FILTER1);
	728	+ lumafilter[1] = tve_readl(TVE_LUMA_FILTER2);
	729	+ lumafilter[2] = tve_readl(TVE_LUMA_FILTER3);
	730	+ lumafilter[3] = tve_readl(TVE_LUMA_FILTER4);
	731	+ lumafilter[4] = tve_readl(TVE_LUMA_FILTER5);
	732	+ lumafilter[5] = tve_readl(TVE_LUMA_FILTER6);
	733	+ lumafilter[6] = tve_readl(TVE_LUMA_FILTER7);
	734	+ lumafilter[7] = tve_readl(TVE_LUMA_FILTER8);
	735	+
	736	+ if (lumafilter[0] == tve->lumafilter0 &&
	737	+ lumafilter[1] == tve->lumafilter1 &&
	738	+ lumafilter[2] == tve->lumafilter2 &&
	739	+ lumafilter[3] == tve->lumafilter3 &&
	740	+ lumafilter[4] == tve->lumafilter4 &&
	741	+ lumafilter[5] == tve->lumafilter5 &&
	742	+ lumafilter[6] == tve->lumafilter6 &&
	743	+ lumafilter[7] == tve->lumafilter7) {
	744	+ return true;
	745	+ }
	746	+ } else {
	747	+ lumafilter[0] = tve_readl(TV_LUMA_FILTER0);
	748	+ lumafilter[1] = tve_readl(TV_LUMA_FILTER1);
	749	+ lumafilter[2] = tve_readl(TV_LUMA_FILTER2);
	750	+
	751	+ if (lumafilter[0] == tve->lumafilter0 &&
	752	+ lumafilter[1] == tve->lumafilter1 &&
	753	+ lumafilter[2] == tve->lumafilter2) {
	754	+ return true;
	755	+ }
	756	+ }
	757	+
	758	+ return false;
	759	+}
	760	+
444	761	static void check_uboot_logo(struct rockchip_tve *tve)
445	762	{
446		- int lumafilter0, lumafilter1, lumafilter2, vdac;
	763	+ int vdac;
447	764
448	765	if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328) {
449	766	vdac = tve_dac_readl(VDAC_VDAC1);
..	..	@@ -454,17 +771,7 @@
454	771	}
455	772	}
456	773
457		- lumafilter0 = tve_readl(TV_LUMA_FILTER0);
458		- lumafilter1 = tve_readl(TV_LUMA_FILTER1);
459		- lumafilter2 = tve_readl(TV_LUMA_FILTER2);
460		-
461		- /*
462		- * The default lumafilter value is 0. If lumafilter value
463		- * is equal to the dts value, uboot logo is enabled.
464		- */
465		- if (lumafilter0 == tve->lumafilter0 &&
466		- lumafilter1 == tve->lumafilter1 &&
467		- lumafilter2 == tve->lumafilter2) {
	774	+ if (tve_check_lumafilter(tve)) {
468	775	tve->connector.dpms = DRM_MODE_DPMS_ON;
469	776	return;
470	777	}
..	..	@@ -495,11 +802,17 @@
495	802	.input_format = INPUT_FORMAT_YUV,
496	803	};
497	804
	805	+static const struct rockchip_tve_data rk3528_tve = {
	806	+ .soc_type = SOC_RK3528,
	807	+ .input_format = INPUT_FORMAT_YUV,
	808	+};
	809	+
498	810	static const struct of_device_id rockchip_tve_dt_ids[] = {
499	811	{ .compatible = "rockchip,rk3036-tve", .data = &rk3036_tve },
500	812	{ .compatible = "rockchip,rk312x-tve", .data = &rk312x_tve },
501	813	{ .compatible = "rockchip,rk322x-tve", .data = &rk322x_tve },
502	814	{ .compatible = "rockchip,rk3328-tve", .data = &rk3328_tve },
	815	+ { .compatible = "rockchip,rk3528-tve", .data = &rk3528_tve },
503	816	{}
504	817	};
505	818
..	..	@@ -530,20 +843,22 @@
530	843	}
531	844
532	845	tve->dev = &pdev->dev;
533		- tve_data = device_get_match_data(dev);
	846	+ tve_data = of_device_get_match_data(dev);
534	847	if (tve_data) {
535	848	tve->soc_type = tve_data->soc_type;
536	849	tve->input_format = tve_data->input_format;
537	850	}
538	851
539		- ret = tve_parse_dt(np, tve);
	852	+ if (tve->soc_type == SOC_RK3528)
	853	+ ret = tve_parse_dt(np, tve);
	854	+ else
	855	+ ret = tve_parse_dt_legacy(np, tve);
540	856	if (ret) {
541	857	dev_err(tve->dev, "TVE parse dts error!");
542	858	return -EINVAL;
543	859	}
544	860
545	861	tve->enable = 0;
546		- platform_set_drvdata(pdev, tve);
547	862	tve->drm_dev = drm_dev;
548	863	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
549	864	tve->reg_phy_base = res->start;
..	..	@@ -555,7 +870,8 @@
555	870	return PTR_ERR(tve->regbase);
556	871	}
557	872
558		- if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328) {
	873	+ if (tve->soc_type == SOC_RK322X \|\| tve->soc_type == SOC_RK3328 \|\|
	874	+ tve->soc_type == SOC_RK3528) {
559	875	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
560	876	tve->len = resource_size(res);
561	877	tve->vdacbase = devm_ioremap(tve->dev, res->start, tve->len);
..	..	@@ -577,6 +893,56 @@
577	893	dev_err(tve->dev, "Cannot enable tve aclk: %d\n", ret);
578	894	return ret;
579	895	}
	896	+ } else if (tve->soc_type == SOC_RK3528) {
	897	+ tve->hclk = devm_clk_get(tve->dev, "hclk");
	898	+ if (IS_ERR(tve->hclk)) {
	899	+ dev_err(tve->dev, "Unable to get tve hclk\n");
	900	+ return PTR_ERR(tve->hclk);
	901	+ }
	902	+
	903	+ ret = clk_prepare_enable(tve->hclk);
	904	+ if (ret) {
	905	+ dev_err(tve->dev, "Cannot enable tve hclk: %d\n", ret);
	906	+ return ret;
	907	+ }
	908	+
	909	+ tve->pclk_vdac = devm_clk_get(tve->dev, "pclk_vdac");
	910	+ if (IS_ERR(tve->pclk_vdac)) {
	911	+ dev_err(tve->dev, "Unable to get vdac pclk\n");
	912	+ return PTR_ERR(tve->pclk_vdac);
	913	+ }
	914	+
	915	+ ret = clk_prepare_enable(tve->pclk_vdac);
	916	+ if (ret) {
	917	+ dev_err(tve->dev, "Cannot enable vdac pclk: %d\n", ret);
	918	+ return ret;
	919	+ }
	920	+
	921	+ tve->dclk = devm_clk_get(tve->dev, "dclk");
	922	+ if (IS_ERR(tve->dclk)) {
	923	+ dev_err(tve->dev, "Unable to get tve dclk\n");
	924	+ return PTR_ERR(tve->dclk);
	925	+ }
	926	+
	927	+ ret = clk_prepare_enable(tve->dclk);
	928	+ if (ret) {
	929	+ dev_err(tve->dev, "Cannot enable tve dclk: %d\n", ret);
	930	+ return ret;
	931	+ }
	932	+
	933	+ if (tve->upsample_mode == DCLK_UPSAMPLEx4) {
	934	+ tve->dclk_4x = devm_clk_get(tve->dev, "dclk_4x");
	935	+ if (IS_ERR(tve->dclk_4x)) {
	936	+ dev_err(tve->dev, "Unable to get tve dclk_4x\n");
	937	+ return PTR_ERR(tve->dclk_4x);
	938	+ }
	939	+
	940	+ ret = clk_prepare_enable(tve->dclk_4x);
	941	+ if (ret) {
	942	+ dev_err(tve->dev, "Cannot enable tve dclk_4x: %d\n", ret);
	943	+ return ret;
	944	+ }
	945	+ }
580	946	}
581	947
582	948	tve->dac_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
..	..	@@ -585,8 +951,8 @@
585	951	check_uboot_logo(tve);
586	952	tve->tv_format = TVOUT_CVBS_PAL;
587	953	encoder = &tve->encoder;
588		- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
589		- dev->of_node);
	954	+ encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
	955	+ dev->of_node);
590	956	dev_dbg(tve->dev, "possible_crtc:%d\n", encoder->possible_crtcs);
591	957
592	958	ret = drm_encoder_init(drm_dev, encoder, &rockchip_tve_encoder_funcs,
..	..	@@ -621,6 +987,7 @@
621	987	rockchip_drm_register_sub_dev(&tve->sub_dev);
622	988
623	989	pm_runtime_enable(dev);
	990	+ dev_set_drvdata(dev, tve);
624	991	dev_dbg(tve->dev, "%s tv encoder probe ok\n", match->compatible);
625	992
626	993	return 0;
..	..	@@ -648,6 +1015,7 @@
648	1015	drm_encoder_cleanup(&tve->encoder);
649	1016
650	1017	pm_runtime_disable(dev);
	1018	+ dev_set_drvdata(dev, NULL);
651	1019	}
652	1020
653	1021	static const struct component_ops rockchip_tve_component_ops = {
..	..	@@ -666,6 +1034,9 @@
666	1034	{
667	1035	struct rockchip_tve *tve = dev_get_drvdata(&pdev->dev);
668	1036
	1037	+ if (!tve)
	1038	+ return;
	1039	+
669	1040	mutex_lock(&tve->suspend_lock);
670	1041
671	1042	dev_dbg(tve->dev, "tve shutdown\n");