forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/radeon/uvd_v1_0.c
....@@ -23,7 +23,7 @@
2323 */
2424
2525 #include <linux/firmware.h>
26
-#include <drm/drmP.h>
26
+
2727 #include "radeon.h"
2828 #include "radeon_asic.h"
2929 #include "r600d.h"
....@@ -117,7 +117,7 @@
117117 if (r)
118118 return r;
119119
120
- /* programm the VCPU memory controller bits 0-27 */
120
+ /* program the VCPU memory controller bits 0-27 */
121121 addr = (rdev->uvd.gpu_addr >> 3) + 16;
122122 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
123123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
....@@ -219,7 +219,7 @@
219219 WREG32(RS_DQ_RD_RET_CONF, 0x3f);
220220 WREG32(MC_CONFIG, 0x1f);
221221
222
- /* fall through */
222
+ fallthrough;
223223 case CHIP_RV670:
224224 case CHIP_RV635:
225225
....@@ -360,7 +360,7 @@
360360 /* Set the write pointer delay */
361361 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
362362
363
- /* programm the 4GB memory segment for rptr and ring buffer */
363
+ /* program the 4GB memory segment for rptr and ring buffer */
364364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
365365 (0x7 << 16) | (0x1 << 31));
366366
....@@ -438,7 +438,7 @@
438438 tmp = RREG32(UVD_CONTEXT_ID);
439439 if (tmp == 0xDEADBEEF)
440440 break;
441
- DRM_UDELAY(1);
441
+ udelay(1);
442442 }
443443
444444 if (i < rdev->usec_timeout) {