.. | .. |
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23 | 23 | */ |
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24 | 24 | |
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25 | 25 | #include <linux/firmware.h> |
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26 | | -#include <drm/drmP.h> |
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| 26 | + |
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27 | 27 | #include "radeon.h" |
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28 | 28 | #include "radeon_asic.h" |
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29 | 29 | #include "r600d.h" |
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.. | .. |
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117 | 117 | if (r) |
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118 | 118 | return r; |
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119 | 119 | |
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120 | | - /* programm the VCPU memory controller bits 0-27 */ |
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| 120 | + /* program the VCPU memory controller bits 0-27 */ |
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121 | 121 | addr = (rdev->uvd.gpu_addr >> 3) + 16; |
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122 | 122 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3; |
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123 | 123 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
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.. | .. |
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219 | 219 | WREG32(RS_DQ_RD_RET_CONF, 0x3f); |
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220 | 220 | WREG32(MC_CONFIG, 0x1f); |
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221 | 221 | |
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222 | | - /* fall through */ |
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| 222 | + fallthrough; |
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223 | 223 | case CHIP_RV670: |
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224 | 224 | case CHIP_RV635: |
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225 | 225 | |
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.. | .. |
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360 | 360 | /* Set the write pointer delay */ |
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361 | 361 | WREG32(UVD_RBC_RB_WPTR_CNTL, 0); |
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362 | 362 | |
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363 | | - /* programm the 4GB memory segment for rptr and ring buffer */ |
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| 363 | + /* program the 4GB memory segment for rptr and ring buffer */ |
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364 | 364 | WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | |
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365 | 365 | (0x7 << 16) | (0x1 << 31)); |
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366 | 366 | |
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.. | .. |
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438 | 438 | tmp = RREG32(UVD_CONTEXT_ID); |
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439 | 439 | if (tmp == 0xDEADBEEF) |
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440 | 440 | break; |
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441 | | - DRM_UDELAY(1); |
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| 441 | + udelay(1); |
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442 | 442 | } |
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443 | 443 | |
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444 | 444 | if (i < rdev->usec_timeout) { |
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