forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/radeon/si.c
....@@ -21,19 +21,23 @@
2121  *
2222  * Authors: Alex Deucher
2323  */
24
+
2425 #include <linux/firmware.h>
25
-#include <linux/slab.h>
2626 #include <linux/module.h>
27
-#include <drm/drmP.h>
27
+#include <linux/pci.h>
28
+#include <linux/slab.h>
29
+
30
+#include <drm/drm_vblank.h>
31
+#include <drm/radeon_drm.h>
32
+
33
+#include "atom.h"
34
+#include "clearstate_si.h"
2835 #include "radeon.h"
2936 #include "radeon_asic.h"
3037 #include "radeon_audio.h"
31
-#include <drm/radeon_drm.h>
32
-#include "sid.h"
33
-#include "atom.h"
34
-#include "si_blit_shaders.h"
35
-#include "clearstate_si.h"
3638 #include "radeon_ucode.h"
39
+#include "si_blit_shaders.h"
40
+#include "sid.h"
3741 
3842 
3943 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
....@@ -3253,7 +3257,7 @@
32533257 		/* XXX what about 12? */
32543258 		rdev->config.si.tile_config |= (3 << 0);
32553259 		break;
3256
-	}	
3260
+	}
32573261 	switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
32583262 	case 0: /* four banks */
32593263 		rdev->config.si.tile_config |= 0 << 4;
....@@ -6468,7 +6472,7 @@
64686472 		 * there. So it is pointless to try to go through that code
64696473 		 * hence why we disable uvd here.
64706474 		 */
6471
-		rdev->has_uvd = 0;
6475
+		rdev->has_uvd = false;
64726476 		return;
64736477 	}
64746478 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
....@@ -6535,7 +6539,7 @@
65356539 		 * there. So it is pointless to try to go through that code
65366540 		 * hence why we disable vce here.
65376541 		 */
6538
-		rdev->has_vce = 0;
6542
+		rdev->has_vce = false;
65396543 		return;
65406544 	}
65416545 	rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
....@@ -7083,7 +7087,6 @@
70837087 {
70847088 	struct pci_dev *root = rdev->pdev->bus->self;
70857089 	enum pci_bus_speed speed_cap;
7086
-	int bridge_pos, gpu_pos;
70877090 	u32 speed_cntl, current_data_rate;
70887091 	int i;
70897092 	u16 tmp16;
....@@ -7125,12 +7128,7 @@
71257128 		DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
71267129 	}
71277130 
7128
-	bridge_pos = pci_pcie_cap(root);
7129
-	if (!bridge_pos)
7130
-		return;
7131
-
7132
-	gpu_pos = pci_pcie_cap(rdev->pdev);
7133
-	if (!gpu_pos)
7131
+	if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
71347132 		return;
71357133 
71367134 	if (speed_cap == PCIE_SPEED_8_0GT) {
....@@ -7140,14 +7138,8 @@
71407138 			u16 bridge_cfg2, gpu_cfg2;
71417139 			u32 max_lw, current_lw, tmp;
71427140 
7143
-			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7144
-			pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7145
-
7146
-			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7147
-			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7148
-
7149
-			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7150
-			pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7141
+			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
7142
+			pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
71517143 
71527144 			tmp = RREG32_PCIE(PCIE_LC_STATUS1);
71537145 			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
....@@ -7165,15 +7157,23 @@
71657157 
71667158 			for (i = 0; i < 10; i++) {
71677159 				/* check status */
7168
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7160
+				pcie_capability_read_word(rdev->pdev,
7161
+							  PCI_EXP_DEVSTA,
7162
+							  &tmp16);
71697163 				if (tmp16 & PCI_EXP_DEVSTA_TRPND)
71707164 					break;
71717165 
7172
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7173
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7166
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL,
7167
+							  &bridge_cfg);
7168
+				pcie_capability_read_word(rdev->pdev,
7169
+							  PCI_EXP_LNKCTL,
7170
+							  &gpu_cfg);
71747171 
7175
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7176
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7172
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
7173
+							  &bridge_cfg2);
7174
+				pcie_capability_read_word(rdev->pdev,
7175
+							  PCI_EXP_LNKCTL2,
7176
+							  &gpu_cfg2);
71777177 
71787178 				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
71797179 				tmp |= LC_SET_QUIESCE;
....@@ -7183,29 +7183,41 @@
71837183 				tmp |= LC_REDO_EQ;
71847184 				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
71857185 
7186
-				mdelay(100);
7186
+				msleep(100);
71877187 
71887188 				/* linkctl */
7189
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7190
-				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7191
-				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7192
-				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7193
-
7194
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7195
-				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7196
-				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7197
-				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7189
+				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
7190
+								   PCI_EXP_LNKCTL_HAWD,
7191
+								   bridge_cfg &
7192
+								   PCI_EXP_LNKCTL_HAWD);
7193
+				pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL,
7194
+								   PCI_EXP_LNKCTL_HAWD,
7195
+								   gpu_cfg &
7196
+								   PCI_EXP_LNKCTL_HAWD);
71987197 
71997198 				/* linkctl2 */
7200
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7201
-				tmp16 &= ~((1 << 4) | (7 << 9));
7202
-				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7203
-				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7199
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
7200
+							  &tmp16);
7201
+				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
7202
+					   PCI_EXP_LNKCTL2_TX_MARGIN);
7203
+				tmp16 |= (bridge_cfg2 &
7204
+					  (PCI_EXP_LNKCTL2_ENTER_COMP |
7205
+					   PCI_EXP_LNKCTL2_TX_MARGIN));
7206
+				pcie_capability_write_word(root,
7207
+							   PCI_EXP_LNKCTL2,
7208
+							   tmp16);
72047209 
7205
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7206
-				tmp16 &= ~((1 << 4) | (7 << 9));
7207
-				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7208
-				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7210
+				pcie_capability_read_word(rdev->pdev,
7211
+							  PCI_EXP_LNKCTL2,
7212
+							  &tmp16);
7213
+				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
7214
+					   PCI_EXP_LNKCTL2_TX_MARGIN);
7215
+				tmp16 |= (gpu_cfg2 &
7216
+					  (PCI_EXP_LNKCTL2_ENTER_COMP |
7217
+					   PCI_EXP_LNKCTL2_TX_MARGIN));
7218
+				pcie_capability_write_word(rdev->pdev,
7219
+							   PCI_EXP_LNKCTL2,
7220
+							   tmp16);
72097221 
72107222 				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
72117223 				tmp &= ~LC_SET_QUIESCE;
....@@ -7219,15 +7231,15 @@
72197231 	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
72207232 	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
72217233 
7222
-	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7223
-	tmp16 &= ~0xf;
7234
+	pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
7235
+	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
72247236 	if (speed_cap == PCIE_SPEED_8_0GT)
7225
-		tmp16 |= 3; /* gen3 */
7237
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
72267238 	else if (speed_cap == PCIE_SPEED_5_0GT)
7227
-		tmp16 |= 2; /* gen2 */
7239
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
72287240 	else
7229
-		tmp16 |= 1; /* gen1 */
7230
-	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7241
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
7242
+	pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
72317243 
72327244 	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
72337245 	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;