forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/radeon/radeon_legacy_tv.c
....@@ -1,6 +1,8 @@
1
-// SPDX-License-Identifier: GPL-2.0
2
-#include <drm/drmP.h>
1
+// SPDX-License-Identifier: MIT
2
+
33 #include <drm/drm_crtc_helper.h>
4
+#include <drm/drm_device.h>
5
+
46 #include "radeon.h"
57
68 /*
....@@ -421,24 +423,14 @@
421423
422424 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
423425 {
424
- struct drm_device *dev = encoder->dev;
425
- struct radeon_device *rdev = dev->dev_private;
426426 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
427427 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
428
- struct radeon_crtc *radeon_crtc;
429428 int restart;
430429 unsigned int h_total, v_total, f_total;
431430 int v_offset, h_offset;
432431 u16 p1, p2, h_inc;
433432 bool h_changed;
434433 const struct radeon_tv_mode_constants *const_ptr;
435
- struct radeon_pll *pll;
436
-
437
- radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
438
- if (radeon_crtc->crtc_id == 1)
439
- pll = &rdev->clock.p2pll;
440
- else
441
- pll = &rdev->clock.p1pll;
442434
443435 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
444436 if (!const_ptr)
....@@ -545,7 +537,7 @@
545537 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
546538 uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
547539 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
548
- uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
540
+ uint32_t tv_pll_cntl, tv_ftotal;
549541 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
550542 uint32_t m, n, p;
551543 const uint16_t *hor_timing;
....@@ -716,12 +708,6 @@
716708 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
717709 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
718710 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
719
-
720
- tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
721
- ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
722
- ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
723
- RADEON_TVCLK_SRC_SEL_TVPLL |
724
- RADEON_TVPLL_TEST_DIS);
725711
726712 tv_dac->tv.tv_uv_adr = 0xc8;
727713