.. | .. |
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1 | | -// SPDX-License-Identifier: GPL-2.0 |
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2 | | -#include <drm/drmP.h> |
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| 1 | +// SPDX-License-Identifier: MIT |
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| 2 | + |
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3 | 3 | #include <drm/drm_crtc_helper.h> |
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| 4 | +#include <drm/drm_device.h> |
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| 5 | + |
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4 | 6 | #include "radeon.h" |
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5 | 7 | |
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6 | 8 | /* |
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.. | .. |
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421 | 423 | |
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422 | 424 | static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) |
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423 | 425 | { |
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424 | | - struct drm_device *dev = encoder->dev; |
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425 | | - struct radeon_device *rdev = dev->dev_private; |
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426 | 426 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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427 | 427 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
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428 | | - struct radeon_crtc *radeon_crtc; |
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429 | 428 | int restart; |
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430 | 429 | unsigned int h_total, v_total, f_total; |
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431 | 430 | int v_offset, h_offset; |
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432 | 431 | u16 p1, p2, h_inc; |
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433 | 432 | bool h_changed; |
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434 | 433 | const struct radeon_tv_mode_constants *const_ptr; |
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435 | | - struct radeon_pll *pll; |
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436 | | - |
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437 | | - radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); |
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438 | | - if (radeon_crtc->crtc_id == 1) |
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439 | | - pll = &rdev->clock.p2pll; |
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440 | | - else |
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441 | | - pll = &rdev->clock.p1pll; |
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442 | 434 | |
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443 | 435 | const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); |
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444 | 436 | if (!const_ptr) |
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.. | .. |
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545 | 537 | uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; |
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546 | 538 | uint32_t tv_modulator_cntl1, tv_modulator_cntl2; |
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547 | 539 | uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; |
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548 | | - uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; |
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| 540 | + uint32_t tv_pll_cntl, tv_ftotal; |
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549 | 541 | uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; |
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550 | 542 | uint32_t m, n, p; |
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551 | 543 | const uint16_t *hor_timing; |
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.. | .. |
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716 | 708 | ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | |
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717 | 709 | (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | |
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718 | 710 | ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); |
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719 | | - |
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720 | | - tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | |
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721 | | - ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | |
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722 | | - ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | |
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723 | | - RADEON_TVCLK_SRC_SEL_TVPLL | |
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724 | | - RADEON_TVPLL_TEST_DIS); |
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725 | 711 | |
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726 | 712 | tv_dac->tv.tv_uv_adr = 0xc8; |
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727 | 713 | |
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