.. | .. |
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33 | 33 | struct qxl_device *qdev; |
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34 | 34 | |
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35 | 35 | bo = to_qxl_bo(tbo); |
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36 | | - qdev = (struct qxl_device *)bo->gem_base.dev->dev_private; |
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| 36 | + qdev = to_qxl(bo->tbo.base.dev); |
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37 | 37 | |
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38 | 38 | qxl_surface_evict(qdev, bo, false); |
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| 39 | + WARN_ON_ONCE(bo->map_count > 0); |
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39 | 40 | mutex_lock(&qdev->gem.mutex); |
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40 | 41 | list_del_init(&bo->list); |
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41 | 42 | mutex_unlock(&qdev->gem.mutex); |
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42 | | - drm_gem_object_release(&bo->gem_base); |
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| 43 | + drm_gem_object_release(&bo->tbo.base); |
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43 | 44 | kfree(bo); |
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44 | 45 | } |
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45 | 46 | |
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.. | .. |
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53 | 54 | void qxl_ttm_placement_from_domain(struct qxl_bo *qbo, u32 domain, bool pinned) |
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54 | 55 | { |
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55 | 56 | u32 c = 0; |
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56 | | - u32 pflag = pinned ? TTM_PL_FLAG_NO_EVICT : 0; |
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57 | | - unsigned i; |
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| 57 | + u32 pflag = 0; |
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| 58 | + unsigned int i; |
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| 59 | + |
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| 60 | + if (pinned) |
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| 61 | + pflag |= TTM_PL_FLAG_NO_EVICT; |
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| 62 | + if (qbo->tbo.base.size <= PAGE_SIZE) |
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| 63 | + pflag |= TTM_PL_FLAG_TOPDOWN; |
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58 | 64 | |
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59 | 65 | qbo->placement.placement = qbo->placements; |
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60 | 66 | qbo->placement.busy_placement = qbo->placements; |
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61 | | - if (domain == QXL_GEM_DOMAIN_VRAM) |
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62 | | - qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag; |
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63 | | - if (domain == QXL_GEM_DOMAIN_SURFACE) |
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64 | | - qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_PRIV | pflag; |
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65 | | - if (domain == QXL_GEM_DOMAIN_CPU) |
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66 | | - qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | pflag; |
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67 | | - if (!c) |
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68 | | - qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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| 67 | + if (domain == QXL_GEM_DOMAIN_VRAM) { |
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| 68 | + qbo->placements[c].mem_type = TTM_PL_VRAM; |
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| 69 | + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; |
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| 70 | + } |
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| 71 | + if (domain == QXL_GEM_DOMAIN_SURFACE) { |
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| 72 | + qbo->placements[c].mem_type = TTM_PL_PRIV; |
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| 73 | + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; |
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| 74 | + qbo->placements[c].mem_type = TTM_PL_VRAM; |
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| 75 | + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; |
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| 76 | + } |
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| 77 | + if (domain == QXL_GEM_DOMAIN_CPU) { |
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| 78 | + qbo->placements[c].mem_type = TTM_PL_SYSTEM; |
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| 79 | + qbo->placements[c++].flags = TTM_PL_MASK_CACHING | pflag; |
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| 80 | + } |
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| 81 | + if (!c) { |
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| 82 | + qbo->placements[c].mem_type = TTM_PL_SYSTEM; |
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| 83 | + qbo->placements[c++].flags = TTM_PL_MASK_CACHING; |
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| 84 | + } |
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69 | 85 | qbo->placement.num_placement = c; |
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70 | 86 | qbo->placement.num_busy_placement = c; |
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71 | 87 | for (i = 0; i < c; ++i) { |
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.. | .. |
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74 | 90 | } |
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75 | 91 | } |
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76 | 92 | |
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| 93 | +static const struct drm_gem_object_funcs qxl_object_funcs = { |
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| 94 | + .free = qxl_gem_object_free, |
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| 95 | + .open = qxl_gem_object_open, |
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| 96 | + .close = qxl_gem_object_close, |
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| 97 | + .pin = qxl_gem_prime_pin, |
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| 98 | + .unpin = qxl_gem_prime_unpin, |
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| 99 | + .get_sg_table = qxl_gem_prime_get_sg_table, |
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| 100 | + .vmap = qxl_gem_prime_vmap, |
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| 101 | + .vunmap = qxl_gem_prime_vunmap, |
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| 102 | + .mmap = drm_gem_ttm_mmap, |
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| 103 | + .print_info = drm_gem_ttm_print_info, |
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| 104 | +}; |
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77 | 105 | |
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78 | | -int qxl_bo_create(struct qxl_device *qdev, |
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79 | | - unsigned long size, bool kernel, bool pinned, u32 domain, |
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| 106 | +int qxl_bo_create(struct qxl_device *qdev, unsigned long size, |
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| 107 | + bool kernel, bool pinned, u32 domain, u32 priority, |
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80 | 108 | struct qxl_surface *surf, |
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81 | 109 | struct qxl_bo **bo_ptr) |
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82 | 110 | { |
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.. | .. |
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93 | 121 | if (bo == NULL) |
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94 | 122 | return -ENOMEM; |
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95 | 123 | size = roundup(size, PAGE_SIZE); |
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96 | | - r = drm_gem_object_init(&qdev->ddev, &bo->gem_base, size); |
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| 124 | + r = drm_gem_object_init(&qdev->ddev, &bo->tbo.base, size); |
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97 | 125 | if (unlikely(r)) { |
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98 | 126 | kfree(bo); |
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99 | 127 | return r; |
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100 | 128 | } |
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| 129 | + bo->tbo.base.funcs = &qxl_object_funcs; |
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101 | 130 | bo->type = domain; |
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102 | 131 | bo->pin_count = pinned ? 1 : 0; |
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103 | 132 | bo->surface_id = 0; |
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.. | .. |
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108 | 137 | |
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109 | 138 | qxl_ttm_placement_from_domain(bo, domain, pinned); |
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110 | 139 | |
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| 140 | + bo->tbo.priority = priority; |
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111 | 141 | r = ttm_bo_init(&qdev->mman.bdev, &bo->tbo, size, type, |
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112 | 142 | &bo->placement, 0, !kernel, size, |
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113 | 143 | NULL, NULL, &qxl_ttm_bo_destroy); |
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.. | .. |
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130 | 160 | if (bo->kptr) { |
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131 | 161 | if (ptr) |
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132 | 162 | *ptr = bo->kptr; |
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| 163 | + bo->map_count++; |
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133 | 164 | return 0; |
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134 | 165 | } |
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135 | 166 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
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.. | .. |
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138 | 169 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
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139 | 170 | if (ptr) |
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140 | 171 | *ptr = bo->kptr; |
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| 172 | + bo->map_count = 1; |
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141 | 173 | return 0; |
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142 | 174 | } |
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143 | 175 | |
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144 | 176 | void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev, |
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145 | 177 | struct qxl_bo *bo, int page_offset) |
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146 | 178 | { |
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147 | | - struct ttm_mem_type_manager *man = &bo->tbo.bdev->man[bo->tbo.mem.mem_type]; |
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| 179 | + unsigned long offset; |
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148 | 180 | void *rptr; |
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149 | 181 | int ret; |
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150 | 182 | struct io_mapping *map; |
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.. | .. |
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156 | 188 | else |
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157 | 189 | goto fallback; |
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158 | 190 | |
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159 | | - (void) ttm_mem_io_lock(man, false); |
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160 | | - ret = ttm_mem_io_reserve(bo->tbo.bdev, &bo->tbo.mem); |
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161 | | - ttm_mem_io_unlock(man); |
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162 | | - |
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163 | | - return io_mapping_map_atomic_wc(map, bo->tbo.mem.bus.offset + page_offset); |
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| 191 | + offset = bo->tbo.mem.start << PAGE_SHIFT; |
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| 192 | + return io_mapping_map_atomic_wc(map, offset + page_offset); |
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164 | 193 | fallback: |
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165 | 194 | if (bo->kptr) { |
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166 | 195 | rptr = bo->kptr + (page_offset * PAGE_SIZE); |
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.. | .. |
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179 | 208 | { |
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180 | 209 | if (bo->kptr == NULL) |
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181 | 210 | return; |
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| 211 | + bo->map_count--; |
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| 212 | + if (bo->map_count > 0) |
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| 213 | + return; |
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182 | 214 | bo->kptr = NULL; |
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183 | 215 | ttm_bo_kunmap(&bo->kmap); |
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184 | 216 | } |
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.. | .. |
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186 | 218 | void qxl_bo_kunmap_atomic_page(struct qxl_device *qdev, |
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187 | 219 | struct qxl_bo *bo, void *pmap) |
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188 | 220 | { |
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189 | | - struct ttm_mem_type_manager *man = &bo->tbo.bdev->man[bo->tbo.mem.mem_type]; |
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190 | | - struct io_mapping *map; |
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191 | | - |
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192 | | - if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
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193 | | - map = qdev->vram_mapping; |
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194 | | - else if (bo->tbo.mem.mem_type == TTM_PL_PRIV) |
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195 | | - map = qdev->surface_mapping; |
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196 | | - else |
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| 221 | + if ((bo->tbo.mem.mem_type != TTM_PL_VRAM) && |
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| 222 | + (bo->tbo.mem.mem_type != TTM_PL_PRIV)) |
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197 | 223 | goto fallback; |
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198 | 224 | |
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199 | 225 | io_mapping_unmap_atomic(pmap); |
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200 | | - |
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201 | | - (void) ttm_mem_io_lock(man, false); |
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202 | | - ttm_mem_io_free(bo->tbo.bdev, &bo->tbo.mem); |
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203 | | - ttm_mem_io_unlock(man); |
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204 | | - return ; |
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| 226 | + return; |
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205 | 227 | fallback: |
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206 | 228 | qxl_bo_kunmap(bo); |
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207 | 229 | } |
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.. | .. |
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211 | 233 | if ((*bo) == NULL) |
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212 | 234 | return; |
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213 | 235 | |
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214 | | - drm_gem_object_put_unlocked(&(*bo)->gem_base); |
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| 236 | + drm_gem_object_put(&(*bo)->tbo.base); |
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215 | 237 | *bo = NULL; |
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216 | 238 | } |
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217 | 239 | |
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218 | 240 | struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo) |
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219 | 241 | { |
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220 | | - drm_gem_object_get(&bo->gem_base); |
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| 242 | + drm_gem_object_get(&bo->tbo.base); |
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221 | 243 | return bo; |
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222 | 244 | } |
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223 | 245 | |
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224 | | -static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) |
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| 246 | +static int __qxl_bo_pin(struct qxl_bo *bo) |
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225 | 247 | { |
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226 | 248 | struct ttm_operation_ctx ctx = { false, false }; |
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227 | | - struct drm_device *ddev = bo->gem_base.dev; |
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| 249 | + struct drm_device *ddev = bo->tbo.base.dev; |
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228 | 250 | int r; |
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229 | 251 | |
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230 | 252 | if (bo->pin_count) { |
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231 | 253 | bo->pin_count++; |
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232 | | - if (gpu_addr) |
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233 | | - *gpu_addr = qxl_bo_gpu_offset(bo); |
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234 | 254 | return 0; |
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235 | 255 | } |
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236 | | - qxl_ttm_placement_from_domain(bo, domain, true); |
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| 256 | + qxl_ttm_placement_from_domain(bo, bo->type, true); |
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237 | 257 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
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238 | 258 | if (likely(r == 0)) { |
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239 | 259 | bo->pin_count = 1; |
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240 | | - if (gpu_addr != NULL) |
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241 | | - *gpu_addr = qxl_bo_gpu_offset(bo); |
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242 | 260 | } |
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243 | 261 | if (unlikely(r != 0)) |
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244 | 262 | dev_err(ddev->dev, "%p pin failed\n", bo); |
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.. | .. |
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248 | 266 | static int __qxl_bo_unpin(struct qxl_bo *bo) |
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249 | 267 | { |
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250 | 268 | struct ttm_operation_ctx ctx = { false, false }; |
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251 | | - struct drm_device *ddev = bo->gem_base.dev; |
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| 269 | + struct drm_device *ddev = bo->tbo.base.dev; |
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252 | 270 | int r, i; |
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253 | 271 | |
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254 | 272 | if (!bo->pin_count) { |
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.. | .. |
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266 | 284 | return r; |
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267 | 285 | } |
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268 | 286 | |
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269 | | - |
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270 | 287 | /* |
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271 | 288 | * Reserve the BO before pinning the object. If the BO was reserved |
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272 | 289 | * beforehand, use the internal version directly __qxl_bo_pin. |
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273 | 290 | * |
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274 | 291 | */ |
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275 | | -int qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) |
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| 292 | +int qxl_bo_pin(struct qxl_bo *bo) |
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276 | 293 | { |
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277 | 294 | int r; |
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278 | 295 | |
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279 | | - r = qxl_bo_reserve(bo, false); |
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| 296 | + r = qxl_bo_reserve(bo); |
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280 | 297 | if (r) |
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281 | 298 | return r; |
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282 | 299 | |
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283 | | - r = __qxl_bo_pin(bo, bo->type, NULL); |
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| 300 | + r = __qxl_bo_pin(bo); |
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284 | 301 | qxl_bo_unreserve(bo); |
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285 | 302 | return r; |
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286 | 303 | } |
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.. | .. |
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294 | 311 | { |
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295 | 312 | int r; |
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296 | 313 | |
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297 | | - r = qxl_bo_reserve(bo, false); |
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| 314 | + r = qxl_bo_reserve(bo); |
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298 | 315 | if (r) |
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299 | 316 | return r; |
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300 | 317 | |
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.. | .. |
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312 | 329 | dev_err(qdev->ddev.dev, "Userspace still has active objects !\n"); |
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313 | 330 | list_for_each_entry_safe(bo, n, &qdev->gem.objects, list) { |
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314 | 331 | dev_err(qdev->ddev.dev, "%p %p %lu %lu force free\n", |
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315 | | - &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
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316 | | - *((unsigned long *)&bo->gem_base.refcount)); |
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| 332 | + &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size, |
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| 333 | + *((unsigned long *)&bo->tbo.base.refcount)); |
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317 | 334 | mutex_lock(&qdev->gem.mutex); |
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318 | 335 | list_del_init(&bo->list); |
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319 | 336 | mutex_unlock(&qdev->gem.mutex); |
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320 | 337 | /* this should unref the ttm bo */ |
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321 | | - drm_gem_object_put_unlocked(&bo->gem_base); |
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| 338 | + drm_gem_object_put(&bo->tbo.base); |
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322 | 339 | } |
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323 | 340 | } |
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324 | 341 | |
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.. | .. |
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335 | 352 | int qxl_bo_check_id(struct qxl_device *qdev, struct qxl_bo *bo) |
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336 | 353 | { |
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337 | 354 | int ret; |
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| 355 | + |
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338 | 356 | if (bo->type == QXL_GEM_DOMAIN_SURFACE && bo->surface_id == 0) { |
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339 | 357 | /* allocate a surface id for this surface now */ |
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340 | 358 | ret = qxl_surface_id_alloc(qdev, bo); |
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341 | 359 | if (ret) |
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342 | 360 | return ret; |
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343 | 361 | |
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344 | | - ret = qxl_hw_surface_alloc(qdev, bo, NULL); |
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| 362 | + ret = qxl_hw_surface_alloc(qdev, bo); |
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345 | 363 | if (ret) |
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346 | 364 | return ret; |
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347 | 365 | } |
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