forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/qxl/qxl_cmd.c
....@@ -25,6 +25,10 @@
2525
2626 /* QXL cmd/ring handling */
2727
28
+#include <linux/delay.h>
29
+
30
+#include <drm/drm_util.h>
31
+
2832 #include "qxl_drv.h"
2933 #include "qxl_object.h"
3034
....@@ -32,7 +36,7 @@
3236
3337 struct ring {
3438 struct qxl_ring_header header;
35
- uint8_t elements[0];
39
+ uint8_t elements[];
3640 };
3741
3842 struct qxl_ring {
....@@ -84,6 +88,7 @@
8488 int ret;
8589 struct qxl_ring_header *header = &(ring->ring->header);
8690 unsigned long flags;
91
+
8792 spin_lock_irqsave(&ring->lock, flags);
8893 ret = header->prod - header->cons < header->num_items;
8994 if (ret == 0)
....@@ -97,6 +102,7 @@
97102 int ret;
98103 struct qxl_ring_header *header = &(ring->ring->header);
99104 unsigned long flags;
105
+
100106 spin_lock_irqsave(&ring->lock, flags);
101107 ret = header->prod == header->cons;
102108 spin_unlock_irqrestore(&ring->lock, flags);
....@@ -110,6 +116,7 @@
110116 uint8_t *elt;
111117 int idx, ret;
112118 unsigned long flags;
119
+
113120 spin_lock_irqsave(&ring->lock, flags);
114121 if (header->prod - header->cons == header->num_items) {
115122 header->notify_on_cons = header->cons + 1;
....@@ -156,6 +163,7 @@
156163 volatile uint8_t *ring_elt;
157164 int idx;
158165 unsigned long flags;
166
+
159167 spin_lock_irqsave(&ring->lock, flags);
160168 if (header->cons == header->prod) {
161169 header->notify_on_prod = header->cons + 1;
....@@ -260,7 +268,7 @@
260268 int ret;
261269
262270 ret = qxl_bo_create(qdev, size, false /* not kernel - device */,
263
- false, QXL_GEM_DOMAIN_VRAM, NULL, &bo);
271
+ false, QXL_GEM_DOMAIN_VRAM, 0, NULL, &bo);
264272 if (ret) {
265273 DRM_ERROR("failed to allocate VRAM BO\n");
266274 return ret;
....@@ -365,17 +373,20 @@
365373 wait_for_io_cmd(qdev, 0, QXL_IO_FLUSH_SURFACES_ASYNC);
366374 }
367375
368
-
369376 void qxl_io_destroy_primary(struct qxl_device *qdev)
370377 {
371378 wait_for_io_cmd(qdev, 0, QXL_IO_DESTROY_PRIMARY_ASYNC);
372
- qdev->primary_created = false;
379
+ qdev->primary_bo->is_primary = false;
380
+ drm_gem_object_put(&qdev->primary_bo->tbo.base);
381
+ qdev->primary_bo = NULL;
373382 }
374383
375
-void qxl_io_create_primary(struct qxl_device *qdev,
376
- unsigned offset, struct qxl_bo *bo)
384
+void qxl_io_create_primary(struct qxl_device *qdev, struct qxl_bo *bo)
377385 {
378386 struct qxl_surface_create *create;
387
+
388
+ if (WARN_ON(qdev->primary_bo))
389
+ return;
379390
380391 DRM_DEBUG_DRIVER("qdev %p, ram_header %p\n", qdev, qdev->ram_header);
381392 create = &qdev->ram_header->create_surface;
....@@ -383,11 +394,7 @@
383394 create->width = bo->surf.width;
384395 create->height = bo->surf.height;
385396 create->stride = bo->surf.stride;
386
- if (bo->shadow) {
387
- create->mem = qxl_bo_physical_address(qdev, bo->shadow, offset);
388
- } else {
389
- create->mem = qxl_bo_physical_address(qdev, bo, offset);
390
- }
397
+ create->mem = qxl_bo_physical_address(qdev, bo, 0);
391398
392399 DRM_DEBUG_DRIVER("mem = %llx, from %p\n", create->mem, bo->kptr);
393400
....@@ -395,7 +402,9 @@
395402 create->type = QXL_SURF_TYPE_PRIMARY;
396403
397404 wait_for_io_cmd(qdev, 0, QXL_IO_CREATE_PRIMARY_ASYNC);
398
- qdev->primary_created = true;
405
+ qdev->primary_bo = bo;
406
+ qdev->primary_bo->is_primary = true;
407
+ drm_gem_object_get(&qdev->primary_bo->tbo.base);
399408 }
400409
401410 void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id)
....@@ -455,8 +464,7 @@
455464 }
456465
457466 int qxl_hw_surface_alloc(struct qxl_device *qdev,
458
- struct qxl_bo *surf,
459
- struct ttm_mem_reg *new_mem)
467
+ struct qxl_bo *surf)
460468 {
461469 struct qxl_surface_cmd *cmd;
462470 struct qxl_release *release;
....@@ -483,16 +491,7 @@
483491 cmd->u.surface_create.width = surf->surf.width;
484492 cmd->u.surface_create.height = surf->surf.height;
485493 cmd->u.surface_create.stride = surf->surf.stride;
486
- if (new_mem) {
487
- int slot_id = surf->type == QXL_GEM_DOMAIN_VRAM ? qdev->main_mem_slot : qdev->surfaces_mem_slot;
488
- struct qxl_memslot *slot = &(qdev->mem_slots[slot_id]);
489
-
490
- /* TODO - need to hold one of the locks to read tbo.offset */
491
- cmd->u.surface_create.data = slot->high_bits;
492
-
493
- cmd->u.surface_create.data |= (new_mem->start << PAGE_SHIFT) + surf->tbo.bdev->man[new_mem->mem_type].gpu_offset;
494
- } else
495
- cmd->u.surface_create.data = qxl_bo_physical_address(qdev, surf, 0);
494
+ cmd->u.surface_create.data = qxl_bo_physical_address(qdev, surf, 0);
496495 cmd->surface_id = surf->surface_id;
497496 qxl_release_unmap(qdev, release, &cmd->release_info);
498497
....@@ -589,7 +588,7 @@
589588 {
590589 int ret;
591590
592
- ret = qxl_bo_reserve(surf, false);
591
+ ret = qxl_bo_reserve(surf);
593592 if (ret)
594593 return ret;
595594