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hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/nouveau/nv84_fence.c
....@@ -21,7 +21,6 @@
2121  *
2222  * Authors: Ben Skeggs
2323  */
24
-
2524 #include "nouveau_drv.h"
2625 #include "nouveau_dma.h"
2726 #include "nouveau_fence.h"
....@@ -29,20 +28,29 @@
2928 
3029 #include "nv50_display.h"
3130 
31
+#include <nvif/push206e.h>
32
+
33
+#include <nvhw/class/cl826f.h>
34
+
3235 static int
3336 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
3437 {
35
-	int ret = RING_SPACE(chan, 8);
38
+	struct nvif_push *push = chan->chan.push;
39
+	int ret = PUSH_WAIT(push, 8);
3640 	if (ret == 0) {
37
-		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
38
-		OUT_RING  (chan, chan->vram.handle);
39
-		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
40
-		OUT_RING  (chan, upper_32_bits(virtual));
41
-		OUT_RING  (chan, lower_32_bits(virtual));
42
-		OUT_RING  (chan, sequence);
43
-		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
44
-		OUT_RING  (chan, 0x00000000);
45
-		FIRE_RING (chan);
41
+		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
42
+
43
+		PUSH_MTHD(push, NV826F, SEMAPHOREA,
44
+			  NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
45
+
46
+					SEMAPHOREB, lower_32_bits(virtual),
47
+					SEMAPHOREC, sequence,
48
+
49
+					SEMAPHORED,
50
+			  NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),
51
+
52
+					NON_STALLED_INTERRUPT, 0);
53
+		PUSH_KICK(push);
4654 	}
4755 	return ret;
4856 }
....@@ -50,16 +58,20 @@
5058 static int
5159 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5260 {
53
-	int ret = RING_SPACE(chan, 7);
61
+	struct nvif_push *push = chan->chan.push;
62
+	int ret = PUSH_WAIT(push, 7);
5463 	if (ret == 0) {
55
-		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
56
-		OUT_RING  (chan, chan->vram.handle);
57
-		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
58
-		OUT_RING  (chan, upper_32_bits(virtual));
59
-		OUT_RING  (chan, lower_32_bits(virtual));
60
-		OUT_RING  (chan, sequence);
61
-		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
62
-		FIRE_RING (chan);
64
+		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
65
+
66
+		PUSH_MTHD(push, NV826F, SEMAPHOREA,
67
+			  NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
68
+
69
+					SEMAPHOREB, lower_32_bits(virtual),
70
+					SEMAPHOREC, sequence,
71
+
72
+					SEMAPHORED,
73
+			  NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
74
+		PUSH_KICK(push);
6375 	}
6476 	return ret;
6577 }
....@@ -109,7 +121,6 @@
109121 int
110122 nv84_fence_context_new(struct nouveau_channel *chan)
111123 {
112
-	struct nouveau_cli *cli = (void *)chan->user.client;
113124 	struct nv84_fence_priv *priv = chan->drm->fence;
114125 	struct nv84_fence_chan *fctx;
115126 	int ret;
....@@ -127,7 +138,7 @@
127138 	fctx->base.sequence = nv84_fence_read(chan);
128139 
129140 	mutex_lock(&priv->mutex);
130
-	ret = nouveau_vma_new(priv->bo, &cli->vmm, &fctx->vma);
141
+	ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
131142 	mutex_unlock(&priv->mutex);
132143 
133144 	if (ret)
....@@ -198,12 +209,13 @@
198209 	mutex_init(&priv->mutex);
199210 
200211 	/* Use VRAM if there is any ; otherwise fallback to system memory */
201
-	domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
202
-			 /*
203
-			  * fences created in sysmem must be non-cached or we
204
-			  * will lose CPU/GPU coherency!
205
-			  */
206
-			 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
212
+	domain = drm->client.device.info.ram_size != 0 ?
213
+		NOUVEAU_GEM_DOMAIN_VRAM :
214
+		 /*
215
+		  * fences created in sysmem must be non-cached or we
216
+		  * will lose CPU/GPU coherency!
217
+		  */
218
+		NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
207219 	ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0,
208220 			     domain, 0, 0, NULL, NULL, &priv->bo);
209221 	if (ret == 0) {