modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/nouveau/nv50_fbcon.c
..
..
@@ -21,11 +21,15 @@
21
21
  *
22
22
  * Authors: Ben Skeggs
23
23
  */
24
-
24
+#define NVIF_DEBUG_PRINT_DISABLE
25
25
 #include "nouveau_drv.h"
26
26
 #include "nouveau_dma.h"
27
27
 #include "nouveau_fbcon.h"
28
28
 #include "nouveau_vmm.h"
29
+
30
+#include <nvif/push206e.h>
31
+
32
+#include <nvhw/class/cl502d.h>
29
33
 
30
34
 int
31
35
 nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
..
..
@@ -33,32 +37,38 @@
33
37
 	struct nouveau_fbdev *nfbdev = info->par;
34
38
 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
35
39
 	struct nouveau_channel *chan = drm->channel;
40
+	struct nvif_push *push = chan->chan.push;
41
+	u32 colour;
36
42
 	int ret;
37
43
 
38
-	ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11);
44
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
45
+	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
46
+		colour = ((uint32_t *)info->pseudo_palette)[rect->color];
47
+	else
48
+		colour = rect->color;
49
+
50
+	ret = PUSH_WAIT(push, rect->rop == ROP_COPY ? 7 : 11);
39
51
 	if (ret)
40
52
 		return ret;
41
53
 
42
54
 	if (rect->rop != ROP_COPY) {
43
-		BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
44
-		OUT_RING(chan, 1);
55
+		PUSH_MTHD(push, NV502D, SET_OPERATION,
56
+			  NVDEF(NV502D, SET_OPERATION, V, ROP_AND));
45
57
 	}
46
-	BEGIN_NV04(chan, NvSub2D, 0x0588, 1);
47
-	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
48
-	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
49
-		OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
50
-	else
51
-		OUT_RING(chan, rect->color);
52
-	BEGIN_NV04(chan, NvSub2D, 0x0600, 4);
53
-	OUT_RING(chan, rect->dx);
54
-	OUT_RING(chan, rect->dy);
55
-	OUT_RING(chan, rect->dx + rect->width);
56
-	OUT_RING(chan, rect->dy + rect->height);
58
+
59
+	PUSH_MTHD(push, NV502D, SET_RENDER_SOLID_PRIM_COLOR, colour);
60
+
61
+	PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_POINT_SET_X(0), rect->dx,
62
+				RENDER_SOLID_PRIM_POINT_Y(0), rect->dy,
63
+				RENDER_SOLID_PRIM_POINT_SET_X(1), rect->dx + rect->width,
64
+				RENDER_SOLID_PRIM_POINT_Y(1), rect->dy + rect->height);
65
+
57
66
 	if (rect->rop != ROP_COPY) {
58
-		BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
59
-		OUT_RING(chan, 3);
67
+		PUSH_MTHD(push, NV502D, SET_OPERATION,
68
+			  NVDEF(NV502D, SET_OPERATION, V, SRCCOPY));
60
69
 	}
61
-	FIRE_RING(chan);
70
+
71
+	PUSH_KICK(push);
62
72
 	return 0;
63
73
 }
64
74
 
..
..
@@ -68,25 +78,25 @@
68
78
 	struct nouveau_fbdev *nfbdev = info->par;
69
79
 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
70
80
 	struct nouveau_channel *chan = drm->channel;
81
+	struct nvif_push *push = chan->chan.push;
71
82
 	int ret;
72
83
 
73
-	ret = RING_SPACE(chan, 12);
84
+	ret = PUSH_WAIT(push, 12);
74
85
 	if (ret)
75
86
 		return ret;
76
87
 
77
-	BEGIN_NV04(chan, NvSub2D, 0x0110, 1);
78
-	OUT_RING(chan, 0);
79
-	BEGIN_NV04(chan, NvSub2D, 0x08b0, 4);
80
-	OUT_RING(chan, region->dx);
81
-	OUT_RING(chan, region->dy);
82
-	OUT_RING(chan, region->width);
83
-	OUT_RING(chan, region->height);
84
-	BEGIN_NV04(chan, NvSub2D, 0x08d0, 4);
85
-	OUT_RING(chan, 0);
86
-	OUT_RING(chan, region->sx);
87
-	OUT_RING(chan, 0);
88
-	OUT_RING(chan, region->sy);
89
-	FIRE_RING(chan);
88
+	PUSH_MTHD(push, NV502D, WAIT_FOR_IDLE, 0);
89
+
90
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DST_X0, region->dx,
91
+				SET_PIXELS_FROM_MEMORY_DST_Y0, region->dy,
92
+				SET_PIXELS_FROM_MEMORY_DST_WIDTH, region->width,
93
+				SET_PIXELS_FROM_MEMORY_DST_HEIGHT, region->height);
94
+
95
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC, 0,
96
+				SET_PIXELS_FROM_MEMORY_SRC_X0_INT, region->sx,
97
+				SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC, 0,
98
+				PIXELS_FROM_MEMORY_SRC_Y0_INT, region->sy);
99
+	PUSH_KICK(push);
90
100
 	return 0;
91
101
 }
92
102
 
..
..
@@ -96,52 +106,54 @@
96
106
 	struct nouveau_fbdev *nfbdev = info->par;
97
107
 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
98
108
 	struct nouveau_channel *chan = drm->channel;
109
+	struct nvif_push *push = chan->chan.push;
99
110
 	uint32_t dwords, *data = (uint32_t *)image->data;
100
111
 	uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
101
-	uint32_t *palette = info->pseudo_palette;
112
+	uint32_t *palette = info->pseudo_palette, bg, fg;
102
113
 	int ret;
103
114
 
104
115
 	if (image->depth != 1)
105
116
 		return -ENODEV;
106
117
 
107
-	ret = RING_SPACE(chan, 11);
118
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
119
+	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
120
+		bg = palette[image->bg_color] | mask;
121
+		fg = palette[image->fg_color] | mask;
122
+	} else {
123
+		bg = image->bg_color;
124
+		fg = image->fg_color;
125
+	}
126
+
127
+	ret = PUSH_WAIT(push, 11);
108
128
 	if (ret)
109
129
 		return ret;
110
130
 
111
-	BEGIN_NV04(chan, NvSub2D, 0x0814, 2);
112
-	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
113
-	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
114
-		OUT_RING(chan, palette[image->bg_color] | mask);
115
-		OUT_RING(chan, palette[image->fg_color] | mask);
116
-	} else {
117
-		OUT_RING(chan, image->bg_color);
118
-		OUT_RING(chan, image->fg_color);
119
-	}
120
-	BEGIN_NV04(chan, NvSub2D, 0x0838, 2);
121
-	OUT_RING(chan, image->width);
122
-	OUT_RING(chan, image->height);
123
-	BEGIN_NV04(chan, NvSub2D, 0x0850, 4);
124
-	OUT_RING(chan, 0);
125
-	OUT_RING(chan, image->dx);
126
-	OUT_RING(chan, 0);
127
-	OUT_RING(chan, image->dy);
131
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_COLOR0, bg,
132
+				SET_PIXELS_FROM_CPU_COLOR1, fg);
133
+
134
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_SRC_WIDTH, image->width,
135
+				SET_PIXELS_FROM_CPU_SRC_HEIGHT, image->height);
136
+
137
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DST_X0_FRAC, 0,
138
+				SET_PIXELS_FROM_CPU_DST_X0_INT, image->dx,
139
+				SET_PIXELS_FROM_CPU_DST_Y0_FRAC, 0,
140
+				SET_PIXELS_FROM_CPU_DST_Y0_INT, image->dy);
128
141
 
129
142
 	dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
130
143
 	while (dwords) {
131
-		int push = dwords > 2047 ? 2047 : dwords;
144
+		int count = dwords > 2047 ? 2047 : dwords;
132
145
 
133
-		ret = RING_SPACE(chan, push + 1);
146
+		ret = PUSH_WAIT(push, count + 1);
134
147
 		if (ret)
135
148
 			return ret;
136
149
 
137
-		dwords -= push;
150
+		dwords -= count;
138
151
 
139
-		BEGIN_NI04(chan, NvSub2D, 0x0860, push);
140
-		OUT_RINGp(chan, data, push);
141
-		data += push;
152
+		PUSH_NINC(push, NV502D, PIXELS_FROM_CPU_DATA, data, count);
153
+		data += count;
142
154
 	}
143
155
 
144
-	FIRE_RING(chan);
156
+	PUSH_KICK(push);
145
157
 	return 0;
146
158
 }
147
159
 
..
..
@@ -149,30 +161,30 @@
149
161
 nv50_fbcon_accel_init(struct fb_info *info)
150
162
 {
151
163
 	struct nouveau_fbdev *nfbdev = info->par;
152
-	struct nouveau_framebuffer *fb = nouveau_framebuffer(nfbdev->helper.fb);
153
164
 	struct drm_device *dev = nfbdev->helper.dev;
154
165
 	struct nouveau_drm *drm = nouveau_drm(dev);
155
166
 	struct nouveau_channel *chan = drm->channel;
167
+	struct nvif_push *push = chan->chan.push;
156
168
 	int ret, format;
157
169
 
158
170
 	switch (info->var.bits_per_pixel) {
159
171
 	case 8:
160
-		format = 0xf3;
172
+		format = NV502D_SET_DST_FORMAT_V_Y8;
161
173
 		break;
162
174
 	case 15:
163
-		format = 0xf8;
175
+		format = NV502D_SET_DST_FORMAT_V_X1R5G5B5;
164
176
 		break;
165
177
 	case 16:
166
-		format = 0xe8;
178
+		format = NV502D_SET_DST_FORMAT_V_R5G6B5;
167
179
 		break;
168
180
 	case 32:
169
181
 		switch (info->var.transp.length) {
170
182
 		case 0: /* depth 24 */
171
183
 		case 8: /* depth 32, just use 24.. */
172
-			format = 0xe6;
184
+			format = NV502D_SET_DST_FORMAT_V_X8R8G8B8;
173
185
 			break;
174
186
 		case 2: /* depth 30 */
175
-			format = 0xd1;
187
+			format = NV502D_SET_DST_FORMAT_V_A2B10G10R10;
176
188
 			break;
177
189
 		default:
178
190
 			return -EINVAL;
..
..
@@ -182,77 +194,106 @@
182
194
 		return -EINVAL;
183
195
 	}
184
196
 
185
-	ret = nvif_object_init(&chan->user, 0x502d, 0x502d, NULL, 0,
186
-			       &nfbdev->twod);
197
+	ret = nvif_object_ctor(&chan->user, "fbconTwoD", 0x502d, 0x502d,
198
+			       NULL, 0, &nfbdev->twod);
187
199
 	if (ret)
188
200
 		return ret;
189
201
 
190
-	ret = RING_SPACE(chan, 58);
202
+	ret = PUSH_WAIT(push, 56);
191
203
 	if (ret) {
192
204
 		nouveau_fbcon_gpu_lockup(info);
193
205
 		return ret;
194
206
 	}
195
207
 
196
-	BEGIN_NV04(chan, NvSub2D, 0x0000, 1);
197
-	OUT_RING(chan, nfbdev->twod.handle);
198
-	BEGIN_NV04(chan, NvSub2D, 0x0184, 3);
199
-	OUT_RING(chan, chan->vram.handle);
200
-	OUT_RING(chan, chan->vram.handle);
201
-	OUT_RING(chan, chan->vram.handle);
202
-	BEGIN_NV04(chan, NvSub2D, 0x0290, 1);
203
-	OUT_RING(chan, 0);
204
-	BEGIN_NV04(chan, NvSub2D, 0x0888, 1);
205
-	OUT_RING(chan, 1);
206
-	BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
207
-	OUT_RING(chan, 3);
208
-	BEGIN_NV04(chan, NvSub2D, 0x02a0, 1);
209
-	OUT_RING(chan, 0x55);
210
-	BEGIN_NV04(chan, NvSub2D, 0x08c0, 4);
211
-	OUT_RING(chan, 0);
212
-	OUT_RING(chan, 1);
213
-	OUT_RING(chan, 0);
214
-	OUT_RING(chan, 1);
215
-	BEGIN_NV04(chan, NvSub2D, 0x0580, 2);
216
-	OUT_RING(chan, 4);
217
-	OUT_RING(chan, format);
218
-	BEGIN_NV04(chan, NvSub2D, 0x02e8, 2);
219
-	OUT_RING(chan, 2);
220
-	OUT_RING(chan, 1);
221
-	BEGIN_NV04(chan, NvSub2D, 0x0804, 1);
222
-	OUT_RING(chan, format);
223
-	BEGIN_NV04(chan, NvSub2D, 0x0800, 1);
224
-	OUT_RING(chan, 1);
225
-	BEGIN_NV04(chan, NvSub2D, 0x0808, 3);
226
-	OUT_RING(chan, 0);
227
-	OUT_RING(chan, 0);
228
-	OUT_RING(chan, 1);
229
-	BEGIN_NV04(chan, NvSub2D, 0x081c, 1);
230
-	OUT_RING(chan, 1);
231
-	BEGIN_NV04(chan, NvSub2D, 0x0840, 4);
232
-	OUT_RING(chan, 0);
233
-	OUT_RING(chan, 1);
234
-	OUT_RING(chan, 0);
235
-	OUT_RING(chan, 1);
236
-	BEGIN_NV04(chan, NvSub2D, 0x0200, 2);
237
-	OUT_RING(chan, format);
238
-	OUT_RING(chan, 1);
239
-	BEGIN_NV04(chan, NvSub2D, 0x0214, 5);
240
-	OUT_RING(chan, info->fix.line_length);
241
-	OUT_RING(chan, info->var.xres_virtual);
242
-	OUT_RING(chan, info->var.yres_virtual);
243
-	OUT_RING(chan, upper_32_bits(fb->vma->addr));
244
-	OUT_RING(chan, lower_32_bits(fb->vma->addr));
245
-	BEGIN_NV04(chan, NvSub2D, 0x0230, 2);
246
-	OUT_RING(chan, format);
247
-	OUT_RING(chan, 1);
248
-	BEGIN_NV04(chan, NvSub2D, 0x0244, 5);
249
-	OUT_RING(chan, info->fix.line_length);
250
-	OUT_RING(chan, info->var.xres_virtual);
251
-	OUT_RING(chan, info->var.yres_virtual);
252
-	OUT_RING(chan, upper_32_bits(fb->vma->addr));
253
-	OUT_RING(chan, lower_32_bits(fb->vma->addr));
254
-	FIRE_RING(chan);
208
+	PUSH_MTHD(push, NV502D, SET_OBJECT, nfbdev->twod.handle);
209
+	PUSH_MTHD(push, NV502D, SET_DST_CONTEXT_DMA, chan->vram.handle,
210
+				SET_SRC_CONTEXT_DMA, chan->vram.handle,
211
+				SET_SEMAPHORE_CONTEXT_DMA, chan->vram.handle);
255
212
 
213
+	PUSH_MTHD(push, NV502D, SET_DST_FORMAT,
214
+		  NVVAL(NV502D, SET_DST_FORMAT, V, format),
215
+
216
+				SET_DST_MEMORY_LAYOUT,
217
+		  NVDEF(NV502D, SET_DST_MEMORY_LAYOUT, V, PITCH));
218
+
219
+	PUSH_MTHD(push, NV502D, SET_DST_PITCH, info->fix.line_length,
220
+				SET_DST_WIDTH, info->var.xres_virtual,
221
+				SET_DST_HEIGHT, info->var.yres_virtual,
222
+
223
+				SET_DST_OFFSET_UPPER,
224
+		  NVVAL(NV502D, SET_DST_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)),
225
+
226
+				SET_DST_OFFSET_LOWER,
227
+		  NVVAL(NV502D, SET_DST_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr)));
228
+
229
+	PUSH_MTHD(push, NV502D, SET_SRC_FORMAT,
230
+		  NVVAL(NV502D, SET_SRC_FORMAT, V, format),
231
+
232
+				SET_SRC_MEMORY_LAYOUT,
233
+		  NVDEF(NV502D, SET_SRC_MEMORY_LAYOUT, V, PITCH));
234
+
235
+	PUSH_MTHD(push, NV502D, SET_SRC_PITCH, info->fix.line_length,
236
+				SET_SRC_WIDTH, info->var.xres_virtual,
237
+				SET_SRC_HEIGHT, info->var.yres_virtual,
238
+
239
+				SET_SRC_OFFSET_UPPER,
240
+		  NVVAL(NV502D, SET_SRC_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)),
241
+
242
+				SET_SRC_OFFSET_LOWER,
243
+		  NVVAL(NV502D, SET_SRC_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr)));
244
+
245
+	PUSH_MTHD(push, NV502D, SET_CLIP_ENABLE,
246
+		  NVDEF(NV502D, SET_CLIP_ENABLE, V, FALSE));
247
+
248
+	PUSH_MTHD(push, NV502D, SET_ROP,
249
+		  NVVAL(NV502D, SET_ROP, V, 0x55));
250
+
251
+	PUSH_MTHD(push, NV502D, SET_OPERATION,
252
+		  NVDEF(NV502D, SET_OPERATION, V, SRCCOPY));
253
+
254
+	PUSH_MTHD(push, NV502D, SET_MONOCHROME_PATTERN_COLOR_FORMAT,
255
+		  NVDEF(NV502D, SET_MONOCHROME_PATTERN_COLOR_FORMAT, V, A8R8G8B8),
256
+
257
+				SET_MONOCHROME_PATTERN_FORMAT,
258
+		  NVDEF(NV502D, SET_MONOCHROME_PATTERN_FORMAT, V, LE_M1));
259
+
260
+	PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_MODE,
261
+		  NVDEF(NV502D, RENDER_SOLID_PRIM_MODE, V, RECTS),
262
+
263
+				SET_RENDER_SOLID_PRIM_COLOR_FORMAT,
264
+		  NVVAL(NV502D, SET_RENDER_SOLID_PRIM_COLOR_FORMAT, V, format));
265
+
266
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DATA_TYPE,
267
+		  NVDEF(NV502D, SET_PIXELS_FROM_CPU_DATA_TYPE, V, INDEX),
268
+
269
+				SET_PIXELS_FROM_CPU_COLOR_FORMAT,
270
+		  NVVAL(NV502D, SET_PIXELS_FROM_CPU_COLOR_FORMAT, V, format),
271
+
272
+				SET_PIXELS_FROM_CPU_INDEX_FORMAT,
273
+		  NVDEF(NV502D, SET_PIXELS_FROM_CPU_INDEX_FORMAT, V, I1),
274
+
275
+				SET_PIXELS_FROM_CPU_MONO_FORMAT,
276
+		  NVDEF(NV502D, SET_PIXELS_FROM_CPU_MONO_FORMAT, V, CGA6_M1),
277
+
278
+				SET_PIXELS_FROM_CPU_WRAP,
279
+		  NVDEF(NV502D, SET_PIXELS_FROM_CPU_WRAP, V, WRAP_BYTE));
280
+
281
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_MONO_OPACITY,
282
+		  NVDEF(NV502D, SET_PIXELS_FROM_CPU_MONO_OPACITY, V, OPAQUE));
283
+
284
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DX_DU_FRAC, 0,
285
+				SET_PIXELS_FROM_CPU_DX_DU_INT, 1,
286
+				SET_PIXELS_FROM_CPU_DY_DV_FRAC, 0,
287
+				SET_PIXELS_FROM_CPU_DY_DV_INT, 1);
288
+
289
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP,
290
+		  NVDEF(NV502D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP, V, TRUE));
291
+
292
+	PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DU_DX_FRAC, 0,
293
+				SET_PIXELS_FROM_MEMORY_DU_DX_INT, 1,
294
+				SET_PIXELS_FROM_MEMORY_DV_DY_FRAC, 0,
295
+				SET_PIXELS_FROM_MEMORY_DV_DY_INT, 1);
296
+	PUSH_KICK(push);
256
297
 	return 0;
257
298
 }
258
299