~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,6 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 and
6		- * only version 2 as published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14	6	#include "mdp5_kms.h"
..	..	@@ -22,7 +14,7 @@
22	14	/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
23	15	const struct mdp5_cfg_hw *mdp5_cfg = NULL;
24	16
25		-const struct mdp5_cfg_hw msm8x74v1_config = {
	17	+static const struct mdp5_cfg_hw msm8x74v1_config = {
26	18	.name = "msm8x74v1",
27	19	.mdp = {
28	20	.count = 1,
..	..	@@ -106,7 +98,7 @@
106	98	.max_clk = 200000000,
107	99	};
108	100
109		-const struct mdp5_cfg_hw msm8x74v2_config = {
	101	+static const struct mdp5_cfg_hw msm8x74v2_config = {
110	102	.name = "msm8x74",
111	103	.mdp = {
112	104	.count = 1,
..	..	@@ -188,7 +180,7 @@
188	180	.max_clk = 200000000,
189	181	};
190	182
191		-const struct mdp5_cfg_hw apq8084_config = {
	183	+static const struct mdp5_cfg_hw apq8084_config = {
192	184	.name = "apq8084",
193	185	.mdp = {
194	186	.count = 1,
..	..	@@ -283,7 +275,7 @@
283	275	.max_clk = 320000000,
284	276	};
285	277
286		-const struct mdp5_cfg_hw msm8x16_config = {
	278	+static const struct mdp5_cfg_hw msm8x16_config = {
287	279	.name = "msm8x16",
288	280	.mdp = {
289	281	.count = 1,
..	..	@@ -350,7 +342,82 @@
350	342	.max_clk = 320000000,
351	343	};
352	344
353		-const struct mdp5_cfg_hw msm8x94_config = {
	345	+static const struct mdp5_cfg_hw msm8x36_config = {
	346	+ .name = "msm8x36",
	347	+ .mdp = {
	348	+ .count = 1,
	349	+ .base = { 0x0 },
	350	+ .caps = MDP_CAP_SMP \|
	351	+ 0,
	352	+ },
	353	+ .smp = {
	354	+ .mmb_count = 8,
	355	+ .mmb_size = 10240,
	356	+ .clients = {
	357	+ [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
	358	+ [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
	359	+ },
	360	+ },
	361	+ .ctl = {
	362	+ .count = 3,
	363	+ .base = { 0x01000, 0x01200, 0x01400 },
	364	+ .flush_hw_mask = 0x4003ffff,
	365	+ },
	366	+ .pipe_vig = {
	367	+ .count = 1,
	368	+ .base = { 0x04000 },
	369	+ .caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	370	+ MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC \|
	371	+ MDP_PIPE_CAP_DECIMATION,
	372	+ },
	373	+ .pipe_rgb = {
	374	+ .count = 2,
	375	+ .base = { 0x14000, 0x16000 },
	376	+ .caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	377	+ MDP_PIPE_CAP_DECIMATION,
	378	+ },
	379	+ .pipe_dma = {
	380	+ .count = 1,
	381	+ .base = { 0x24000 },
	382	+ .caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP,
	383	+ },
	384	+ .lm = {
	385	+ .count = 2,
	386	+ .base = { 0x44000, 0x47000 },
	387	+ .instances = {
	388	+ { .id = 0, .pp = 0, .dspp = 0,
	389	+ .caps = MDP_LM_CAP_DISPLAY, },
	390	+ { .id = 1, .pp = -1, .dspp = -1,
	391	+ .caps = MDP_LM_CAP_WB, },
	392	+ },
	393	+ .nb_stages = 8,
	394	+ .max_width = 2560,
	395	+ .max_height = 0xFFFF,
	396	+ },
	397	+ .pp = {
	398	+ .count = 1,
	399	+ .base = { 0x70000 },
	400	+ },
	401	+ .ad = {
	402	+ .count = 1,
	403	+ .base = { 0x78000 },
	404	+ },
	405	+ .dspp = {
	406	+ .count = 1,
	407	+ .base = { 0x54000 },
	408	+ },
	409	+ .intf = {
	410	+ .base = { 0x00000, 0x6a800, 0x6b000 },
	411	+ .connect = {
	412	+ [0] = INTF_DISABLED,
	413	+ [1] = INTF_DSI,
	414	+ [2] = INTF_DSI,
	415	+ },
	416	+ },
	417	+ .max_clk = 366670000,
	418	+};
	419	+
	420	+static const struct mdp5_cfg_hw msm8x94_config = {
354	421	.name = "msm8x94",
355	422	.mdp = {
356	423	.count = 1,
..	..	@@ -445,7 +512,7 @@
445	512	.max_clk = 400000000,
446	513	};
447	514
448		-const struct mdp5_cfg_hw msm8x96_config = {
	515	+static const struct mdp5_cfg_hw msm8x96_config = {
449	516	.name = "msm8x96",
450	517	.mdp = {
451	518	.count = 1,
..	..	@@ -553,13 +620,508 @@
553	620	.max_clk = 412500000,
554	621	};
555	622
556		-static const struct mdp5_cfg_handler cfg_handlers[] = {
	623	+const struct mdp5_cfg_hw msm8x76_config = {
	624	+ .name = "msm8x76",
	625	+ .mdp = {
	626	+ .count = 1,
	627	+ .caps = MDP_CAP_SMP \|
	628	+ MDP_CAP_DSC \|
	629	+ MDP_CAP_SRC_SPLIT \|
	630	+ 0,
	631	+ },
	632	+ .ctl = {
	633	+ .count = 3,
	634	+ .base = { 0x01000, 0x01200, 0x01400 },
	635	+ .flush_hw_mask = 0xffffffff,
	636	+ },
	637	+ .smp = {
	638	+ .mmb_count = 10,
	639	+ .mmb_size = 10240,
	640	+ .clients = {
	641	+ [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
	642	+ [SSPP_DMA0] = 4,
	643	+ [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
	644	+ },
	645	+ },
	646	+ .pipe_vig = {
	647	+ .count = 2,
	648	+ .base = { 0x04000, 0x06000 },
	649	+ .caps = MDP_PIPE_CAP_HFLIP \|
	650	+ MDP_PIPE_CAP_VFLIP \|
	651	+ MDP_PIPE_CAP_SCALE \|
	652	+ MDP_PIPE_CAP_CSC \|
	653	+ MDP_PIPE_CAP_DECIMATION \|
	654	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	655	+ 0,
	656	+ },
	657	+ .pipe_rgb = {
	658	+ .count = 2,
	659	+ .base = { 0x14000, 0x16000 },
	660	+ .caps = MDP_PIPE_CAP_HFLIP \|
	661	+ MDP_PIPE_CAP_VFLIP \|
	662	+ MDP_PIPE_CAP_DECIMATION \|
	663	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	664	+ 0,
	665	+ },
	666	+ .pipe_dma = {
	667	+ .count = 1,
	668	+ .base = { 0x24000 },
	669	+ .caps = MDP_PIPE_CAP_HFLIP \|
	670	+ MDP_PIPE_CAP_VFLIP \|
	671	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	672	+ 0,
	673	+ },
	674	+ .pipe_cursor = {
	675	+ .count = 1,
	676	+ .base = { 0x440DC },
	677	+ .caps = MDP_PIPE_CAP_HFLIP \|
	678	+ MDP_PIPE_CAP_VFLIP \|
	679	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	680	+ MDP_PIPE_CAP_CURSOR \|
	681	+ 0,
	682	+ },
	683	+ .lm = {
	684	+ .count = 2,
	685	+ .base = { 0x44000, 0x45000 },
	686	+ .instances = {
	687	+ { .id = 0, .pp = 0, .dspp = 0,
	688	+ .caps = MDP_LM_CAP_DISPLAY, },
	689	+ { .id = 1, .pp = -1, .dspp = -1,
	690	+ .caps = MDP_LM_CAP_WB },
	691	+ },
	692	+ .nb_stages = 8,
	693	+ .max_width = 2560,
	694	+ .max_height = 0xFFFF,
	695	+ },
	696	+ .dspp = {
	697	+ .count = 1,
	698	+ .base = { 0x54000 },
	699	+
	700	+ },
	701	+ .pp = {
	702	+ .count = 3,
	703	+ .base = { 0x70000, 0x70800, 0x72000 },
	704	+ },
	705	+ .dsc = {
	706	+ .count = 2,
	707	+ .base = { 0x80000, 0x80400 },
	708	+ },
	709	+ .intf = {
	710	+ .base = { 0x6a000, 0x6a800, 0x6b000 },
	711	+ .connect = {
	712	+ [0] = INTF_DISABLED,
	713	+ [1] = INTF_DSI,
	714	+ [2] = INTF_DSI,
	715	+ },
	716	+ },
	717	+ .max_clk = 360000000,
	718	+};
	719	+
	720	+static const struct mdp5_cfg_hw msm8917_config = {
	721	+ .name = "msm8917",
	722	+ .mdp = {
	723	+ .count = 1,
	724	+ .caps = MDP_CAP_CDM,
	725	+ },
	726	+ .ctl = {
	727	+ .count = 3,
	728	+ .base = { 0x01000, 0x01200, 0x01400 },
	729	+ .flush_hw_mask = 0xffffffff,
	730	+ },
	731	+ .pipe_vig = {
	732	+ .count = 1,
	733	+ .base = { 0x04000 },
	734	+ .caps = MDP_PIPE_CAP_HFLIP \|
	735	+ MDP_PIPE_CAP_VFLIP \|
	736	+ MDP_PIPE_CAP_SCALE \|
	737	+ MDP_PIPE_CAP_CSC \|
	738	+ MDP_PIPE_CAP_DECIMATION \|
	739	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	740	+ 0,
	741	+ },
	742	+ .pipe_rgb = {
	743	+ .count = 2,
	744	+ .base = { 0x14000, 0x16000 },
	745	+ .caps = MDP_PIPE_CAP_HFLIP \|
	746	+ MDP_PIPE_CAP_VFLIP \|
	747	+ MDP_PIPE_CAP_DECIMATION \|
	748	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	749	+ 0,
	750	+ },
	751	+ .pipe_dma = {
	752	+ .count = 1,
	753	+ .base = { 0x24000 },
	754	+ .caps = MDP_PIPE_CAP_HFLIP \|
	755	+ MDP_PIPE_CAP_VFLIP \|
	756	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	757	+ 0,
	758	+ },
	759	+ .pipe_cursor = {
	760	+ .count = 1,
	761	+ .base = { 0x34000 },
	762	+ .caps = MDP_PIPE_CAP_HFLIP \|
	763	+ MDP_PIPE_CAP_VFLIP \|
	764	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	765	+ MDP_PIPE_CAP_CURSOR \|
	766	+ 0,
	767	+ },
	768	+
	769	+ .lm = {
	770	+ .count = 2,
	771	+ .base = { 0x44000, 0x45000 },
	772	+ .instances = {
	773	+ { .id = 0, .pp = 0, .dspp = 0,
	774	+ .caps = MDP_LM_CAP_DISPLAY, },
	775	+ { .id = 1, .pp = -1, .dspp = -1,
	776	+ .caps = MDP_LM_CAP_WB },
	777	+ },
	778	+ .nb_stages = 8,
	779	+ .max_width = 2048,
	780	+ .max_height = 0xFFFF,
	781	+ },
	782	+ .dspp = {
	783	+ .count = 1,
	784	+ .base = { 0x54000 },
	785	+
	786	+ },
	787	+ .pp = {
	788	+ .count = 1,
	789	+ .base = { 0x70000 },
	790	+ },
	791	+ .cdm = {
	792	+ .count = 1,
	793	+ .base = { 0x79200 },
	794	+ },
	795	+ .intf = {
	796	+ .base = { 0x6a000, 0x6a800 },
	797	+ .connect = {
	798	+ [0] = INTF_DISABLED,
	799	+ [1] = INTF_DSI,
	800	+ },
	801	+ },
	802	+ .max_clk = 320000000,
	803	+};
	804	+
	805	+static const struct mdp5_cfg_hw msm8998_config = {
	806	+ .name = "msm8998",
	807	+ .mdp = {
	808	+ .count = 1,
	809	+ .caps = MDP_CAP_DSC \|
	810	+ MDP_CAP_CDM \|
	811	+ MDP_CAP_SRC_SPLIT \|
	812	+ 0,
	813	+ },
	814	+ .ctl = {
	815	+ .count = 5,
	816	+ .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
	817	+ .flush_hw_mask = 0xf7ffffff,
	818	+ },
	819	+ .pipe_vig = {
	820	+ .count = 4,
	821	+ .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
	822	+ .caps = MDP_PIPE_CAP_HFLIP \|
	823	+ MDP_PIPE_CAP_VFLIP \|
	824	+ MDP_PIPE_CAP_SCALE \|
	825	+ MDP_PIPE_CAP_CSC \|
	826	+ MDP_PIPE_CAP_DECIMATION \|
	827	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	828	+ 0,
	829	+ },
	830	+ .pipe_rgb = {
	831	+ .count = 4,
	832	+ .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
	833	+ .caps = MDP_PIPE_CAP_HFLIP \|
	834	+ MDP_PIPE_CAP_VFLIP \|
	835	+ MDP_PIPE_CAP_SCALE \|
	836	+ MDP_PIPE_CAP_DECIMATION \|
	837	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	838	+ 0,
	839	+ },
	840	+ .pipe_dma = {
	841	+ .count = 2, /* driver supports max of 2 currently */
	842	+ .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
	843	+ .caps = MDP_PIPE_CAP_HFLIP \|
	844	+ MDP_PIPE_CAP_VFLIP \|
	845	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	846	+ 0,
	847	+ },
	848	+ .pipe_cursor = {
	849	+ .count = 2,
	850	+ .base = { 0x34000, 0x36000 },
	851	+ .caps = MDP_PIPE_CAP_HFLIP \|
	852	+ MDP_PIPE_CAP_VFLIP \|
	853	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	854	+ MDP_PIPE_CAP_CURSOR \|
	855	+ 0,
	856	+ },
	857	+
	858	+ .lm = {
	859	+ .count = 6,
	860	+ .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
	861	+ .instances = {
	862	+ { .id = 0, .pp = 0, .dspp = 0,
	863	+ .caps = MDP_LM_CAP_DISPLAY \|
	864	+ MDP_LM_CAP_PAIR, },
	865	+ { .id = 1, .pp = 1, .dspp = 1,
	866	+ .caps = MDP_LM_CAP_DISPLAY, },
	867	+ { .id = 2, .pp = 2, .dspp = -1,
	868	+ .caps = MDP_LM_CAP_DISPLAY \|
	869	+ MDP_LM_CAP_PAIR, },
	870	+ { .id = 3, .pp = -1, .dspp = -1,
	871	+ .caps = MDP_LM_CAP_WB, },
	872	+ { .id = 4, .pp = -1, .dspp = -1,
	873	+ .caps = MDP_LM_CAP_WB, },
	874	+ { .id = 5, .pp = 3, .dspp = -1,
	875	+ .caps = MDP_LM_CAP_DISPLAY, },
	876	+ },
	877	+ .nb_stages = 8,
	878	+ .max_width = 2560,
	879	+ .max_height = 0xFFFF,
	880	+ },
	881	+ .dspp = {
	882	+ .count = 2,
	883	+ .base = { 0x54000, 0x56000 },
	884	+ },
	885	+ .ad = {
	886	+ .count = 3,
	887	+ .base = { 0x78000, 0x78800, 0x79000 },
	888	+ },
	889	+ .pp = {
	890	+ .count = 4,
	891	+ .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
	892	+ },
	893	+ .cdm = {
	894	+ .count = 1,
	895	+ .base = { 0x79200 },
	896	+ },
	897	+ .dsc = {
	898	+ .count = 2,
	899	+ .base = { 0x80000, 0x80400 },
	900	+ },
	901	+ .intf = {
	902	+ .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
	903	+ .connect = {
	904	+ [0] = INTF_eDP,
	905	+ [1] = INTF_DSI,
	906	+ [2] = INTF_DSI,
	907	+ [3] = INTF_HDMI,
	908	+ },
	909	+ },
	910	+ .max_clk = 412500000,
	911	+};
	912	+
	913	+static const struct mdp5_cfg_hw sdm630_config = {
	914	+ .name = "sdm630",
	915	+ .mdp = {
	916	+ .count = 1,
	917	+ .caps = MDP_CAP_CDM \|
	918	+ MDP_CAP_SRC_SPLIT \|
	919	+ 0,
	920	+ },
	921	+ .ctl = {
	922	+ .count = 5,
	923	+ .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
	924	+ .flush_hw_mask = 0xf4ffffff,
	925	+ },
	926	+ .pipe_vig = {
	927	+ .count = 1,
	928	+ .base = { 0x04000 },
	929	+ .caps = MDP_PIPE_CAP_HFLIP \|
	930	+ MDP_PIPE_CAP_VFLIP \|
	931	+ MDP_PIPE_CAP_SCALE \|
	932	+ MDP_PIPE_CAP_CSC \|
	933	+ MDP_PIPE_CAP_DECIMATION \|
	934	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	935	+ 0,
	936	+ },
	937	+ .pipe_rgb = {
	938	+ .count = 4,
	939	+ .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
	940	+ .caps = MDP_PIPE_CAP_HFLIP \|
	941	+ MDP_PIPE_CAP_VFLIP \|
	942	+ MDP_PIPE_CAP_SCALE \|
	943	+ MDP_PIPE_CAP_DECIMATION \|
	944	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	945	+ 0,
	946	+ },
	947	+ .pipe_dma = {
	948	+ .count = 2, /* driver supports max of 2 currently */
	949	+ .base = { 0x24000, 0x26000, 0x28000 },
	950	+ .caps = MDP_PIPE_CAP_HFLIP \|
	951	+ MDP_PIPE_CAP_VFLIP \|
	952	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	953	+ 0,
	954	+ },
	955	+ .pipe_cursor = {
	956	+ .count = 1,
	957	+ .base = { 0x34000 },
	958	+ .caps = MDP_PIPE_CAP_HFLIP \|
	959	+ MDP_PIPE_CAP_VFLIP \|
	960	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	961	+ MDP_PIPE_CAP_CURSOR \|
	962	+ 0,
	963	+ },
	964	+
	965	+ .lm = {
	966	+ .count = 2,
	967	+ .base = { 0x44000, 0x46000 },
	968	+ .instances = {
	969	+ { .id = 0, .pp = 0, .dspp = 0,
	970	+ .caps = MDP_LM_CAP_DISPLAY \|
	971	+ MDP_LM_CAP_PAIR, },
	972	+ { .id = 1, .pp = 1, .dspp = -1,
	973	+ .caps = MDP_LM_CAP_WB, },
	974	+ },
	975	+ .nb_stages = 8,
	976	+ .max_width = 2048,
	977	+ .max_height = 0xFFFF,
	978	+ },
	979	+ .dspp = {
	980	+ .count = 1,
	981	+ .base = { 0x54000 },
	982	+ },
	983	+ .ad = {
	984	+ .count = 2,
	985	+ .base = { 0x78000, 0x78800 },
	986	+ },
	987	+ .pp = {
	988	+ .count = 3,
	989	+ .base = { 0x70000, 0x71000, 0x72000 },
	990	+ },
	991	+ .cdm = {
	992	+ .count = 1,
	993	+ .base = { 0x79200 },
	994	+ },
	995	+ .intf = {
	996	+ .base = { 0x6a000, 0x6a800 },
	997	+ .connect = {
	998	+ [0] = INTF_DISABLED,
	999	+ [1] = INTF_DSI,
	1000	+ },
	1001	+ },
	1002	+ .max_clk = 412500000,
	1003	+};
	1004	+
	1005	+static const struct mdp5_cfg_hw sdm660_config = {
	1006	+ .name = "sdm660",
	1007	+ .mdp = {
	1008	+ .count = 1,
	1009	+ .caps = MDP_CAP_DSC \|
	1010	+ MDP_CAP_CDM \|
	1011	+ MDP_CAP_SRC_SPLIT \|
	1012	+ 0,
	1013	+ },
	1014	+ .ctl = {
	1015	+ .count = 5,
	1016	+ .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
	1017	+ .flush_hw_mask = 0xf4ffffff,
	1018	+ },
	1019	+ .pipe_vig = {
	1020	+ .count = 2,
	1021	+ .base = { 0x04000, 0x6000 },
	1022	+ .caps = MDP_PIPE_CAP_HFLIP \|
	1023	+ MDP_PIPE_CAP_VFLIP \|
	1024	+ MDP_PIPE_CAP_SCALE \|
	1025	+ MDP_PIPE_CAP_CSC \|
	1026	+ MDP_PIPE_CAP_DECIMATION \|
	1027	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	1028	+ 0,
	1029	+ },
	1030	+ .pipe_rgb = {
	1031	+ .count = 4,
	1032	+ .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
	1033	+ .caps = MDP_PIPE_CAP_HFLIP \|
	1034	+ MDP_PIPE_CAP_VFLIP \|
	1035	+ MDP_PIPE_CAP_SCALE \|
	1036	+ MDP_PIPE_CAP_DECIMATION \|
	1037	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	1038	+ 0,
	1039	+ },
	1040	+ .pipe_dma = {
	1041	+ .count = 2, /* driver supports max of 2 currently */
	1042	+ .base = { 0x24000, 0x26000, 0x28000 },
	1043	+ .caps = MDP_PIPE_CAP_HFLIP \|
	1044	+ MDP_PIPE_CAP_VFLIP \|
	1045	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	1046	+ 0,
	1047	+ },
	1048	+ .pipe_cursor = {
	1049	+ .count = 1,
	1050	+ .base = { 0x34000 },
	1051	+ .caps = MDP_PIPE_CAP_HFLIP \|
	1052	+ MDP_PIPE_CAP_VFLIP \|
	1053	+ MDP_PIPE_CAP_SW_PIX_EXT \|
	1054	+ MDP_PIPE_CAP_CURSOR \|
	1055	+ 0,
	1056	+ },
	1057	+
	1058	+ .lm = {
	1059	+ .count = 4,
	1060	+ .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
	1061	+ .instances = {
	1062	+ { .id = 0, .pp = 0, .dspp = 0,
	1063	+ .caps = MDP_LM_CAP_DISPLAY \|
	1064	+ MDP_LM_CAP_PAIR, },
	1065	+ { .id = 1, .pp = 1, .dspp = 1,
	1066	+ .caps = MDP_LM_CAP_DISPLAY, },
	1067	+ { .id = 2, .pp = 2, .dspp = -1,
	1068	+ .caps = MDP_LM_CAP_DISPLAY \|
	1069	+ MDP_LM_CAP_PAIR, },
	1070	+ { .id = 3, .pp = 3, .dspp = -1,
	1071	+ .caps = MDP_LM_CAP_WB, },
	1072	+ },
	1073	+ .nb_stages = 8,
	1074	+ .max_width = 2560,
	1075	+ .max_height = 0xFFFF,
	1076	+ },
	1077	+ .dspp = {
	1078	+ .count = 2,
	1079	+ .base = { 0x54000, 0x56000 },
	1080	+ },
	1081	+ .ad = {
	1082	+ .count = 2,
	1083	+ .base = { 0x78000, 0x78800 },
	1084	+ },
	1085	+ .pp = {
	1086	+ .count = 5,
	1087	+ .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
	1088	+ },
	1089	+ .cdm = {
	1090	+ .count = 1,
	1091	+ .base = { 0x79200 },
	1092	+ },
	1093	+ .dsc = {
	1094	+ .count = 2,
	1095	+ .base = { 0x80000, 0x80400 },
	1096	+ },
	1097	+ .intf = {
	1098	+ .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
	1099	+ .connect = {
	1100	+ [0] = INTF_DISABLED,
	1101	+ [1] = INTF_DSI,
	1102	+ [2] = INTF_DSI,
	1103	+ [3] = INTF_HDMI,
	1104	+ },
	1105	+ },
	1106	+ .max_clk = 412500000,
	1107	+};
	1108	+
	1109	+static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
557	1110	{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
558	1111	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
559	1112	{ .revision = 3, .config = { .hw = &apq8084_config } },
560	1113	{ .revision = 6, .config = { .hw = &msm8x16_config } },
	1114	+ { .revision = 8, .config = { .hw = &msm8x36_config } },
561	1115	{ .revision = 9, .config = { .hw = &msm8x94_config } },
562	1116	{ .revision = 7, .config = { .hw = &msm8x96_config } },
	1117	+ { .revision = 11, .config = { .hw = &msm8x76_config } },
	1118	+ { .revision = 15, .config = { .hw = &msm8917_config } },
	1119	+};
	1120	+
	1121	+static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
	1122	+ { .revision = 0, .config = { .hw = &msm8998_config } },
	1123	+ { .revision = 2, .config = { .hw = &sdm660_config } },
	1124	+ { .revision = 3, .config = { .hw = &sdm630_config } },
563	1125	};
564	1126
565	1127	static struct mdp5_cfg_platform mdp5_get_config(struct platform_device dev);
..	..	@@ -590,8 +1152,9 @@
590	1152	struct drm_device *dev = mdp5_kms->dev;
591	1153	struct platform_device *pdev = to_platform_device(dev->dev);
592	1154	struct mdp5_cfg_handler *cfg_handler;
	1155	+ const struct mdp5_cfg_handler *cfg_handlers;
593	1156	struct mdp5_cfg_platform *pconfig;
594		- int i, ret = 0;
	1157	+ int i, ret = 0, num_handlers;
595	1158
596	1159	cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
597	1160	if (unlikely(!cfg_handler)) {
..	..	@@ -599,15 +1162,24 @@
599	1162	goto fail;
600	1163	}
601	1164
602		- if (major != 1) {
603		- dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
	1165	+ switch (major) {
	1166	+ case 1:
	1167	+ cfg_handlers = cfg_handlers_v1;
	1168	+ num_handlers = ARRAY_SIZE(cfg_handlers_v1);
	1169	+ break;
	1170	+ case 3:
	1171	+ cfg_handlers = cfg_handlers_v3;
	1172	+ num_handlers = ARRAY_SIZE(cfg_handlers_v3);
	1173	+ break;
	1174	+ default:
	1175	+ DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
604	1176	major, minor);
605	1177	ret = -ENXIO;
606	1178	goto fail;
607	1179	}
608	1180
609	1181	/* only after mdp5_cfg global pointer's init can we access the hw */
610		- for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
	1182	+ for (i = 0; i < num_handlers; i++) {
611	1183	if (cfg_handlers[i].revision != minor)
612	1184	continue;
613	1185	mdp5_cfg = cfg_handlers[i].config.hw;
..	..	@@ -615,7 +1187,7 @@
615	1187	break;
616	1188	}
617	1189	if (unlikely(!mdp5_cfg)) {
618		- dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
	1190	+ DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
619	1191	major, minor);
620	1192	ret = -ENXIO;
621	1193	goto fail;
..	..	@@ -643,10 +1215,6 @@
643	1215	static struct mdp5_cfg_platform config = {};
644	1216
645	1217	config.iommu = iommu_domain_alloc(&platform_bus_type);
646		- if (config.iommu) {
647		- config.iommu->geometry.aperture_start = 0x1000;
648		- config.iommu->geometry.aperture_end = 0xffffffff;
649		- }
650	1218
651	1219	return &config;
652	1220	}