forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
....@@ -1,20 +1,15 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2012-2015, 2017-2018, The Linux Foundation.
23 * All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
- * GNU General Public License for more details.
124 */
135
146 #include <linux/clk.h>
157 #include <linux/clk/clk-conf.h>
168 #include <linux/err.h>
179 #include <linux/delay.h>
10
+#include <linux/of.h>
11
+
12
+#include <drm/drm_print.h>
1813
1914 #include "dpu_io_util.h"
2015
....@@ -98,23 +93,16 @@
9893 DEV_DBG("%pS->%s: enable '%s'\n",
9994 __builtin_return_address(0), __func__,
10095 clk_arry[i].clk_name);
101
- if (clk_arry[i].clk) {
102
- rc = clk_prepare_enable(clk_arry[i].clk);
103
- if (rc)
104
- DEV_ERR("%pS->%s: %s en fail. rc=%d\n",
105
- __builtin_return_address(0),
106
- __func__,
107
- clk_arry[i].clk_name, rc);
108
- } else {
109
- DEV_ERR("%pS->%s: '%s' is not available\n",
110
- __builtin_return_address(0), __func__,
111
- clk_arry[i].clk_name);
112
- rc = -EPERM;
113
- }
96
+ rc = clk_prepare_enable(clk_arry[i].clk);
97
+ if (rc)
98
+ DEV_ERR("%pS->%s: %s en fail. rc=%d\n",
99
+ __builtin_return_address(0),
100
+ __func__,
101
+ clk_arry[i].clk_name, rc);
114102
115
- if (rc) {
116
- msm_dss_enable_clk(&clk_arry[i],
117
- i, false);
103
+ if (rc && i) {
104
+ msm_dss_enable_clk(&clk_arry[i - 1],
105
+ i - 1, false);
118106 break;
119107 }
120108 }
....@@ -124,12 +112,7 @@
124112 __builtin_return_address(0), __func__,
125113 clk_arry[i].clk_name);
126114
127
- if (clk_arry[i].clk)
128
- clk_disable_unprepare(clk_arry[i].clk);
129
- else
130
- DEV_ERR("%pS->%s: '%s' is not available\n",
131
- __builtin_return_address(0), __func__,
132
- clk_arry[i].clk_name);
115
+ clk_disable_unprepare(clk_arry[i].clk);
133116 }
134117 }
135118
....@@ -164,7 +147,7 @@
164147 "clock-names", i,
165148 &clock_name);
166149 if (rc) {
167
- dev_err(&pdev->dev, "Failed to get clock name for %d\n",
150
+ DRM_DEV_ERROR(&pdev->dev, "Failed to get clock name for %d\n",
168151 i);
169152 break;
170153 }
....@@ -176,13 +159,13 @@
176159
177160 rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, num_clk);
178161 if (rc) {
179
- dev_err(&pdev->dev, "Failed to get clock refs %d\n", rc);
162
+ DRM_DEV_ERROR(&pdev->dev, "Failed to get clock refs %d\n", rc);
180163 goto err;
181164 }
182165
183166 rc = of_clk_set_defaults(pdev->dev.of_node, false);
184167 if (rc) {
185
- dev_err(&pdev->dev, "Failed to set clock defaults %d\n", rc);
168
+ DRM_DEV_ERROR(&pdev->dev, "Failed to set clock defaults %d\n", rc);
186169 goto err;
187170 }
188171
....@@ -192,6 +175,7 @@
192175 continue;
193176 mp->clk_config[i].rate = rate;
194177 mp->clk_config[i].type = DSS_CLK_PCLK;
178
+ mp->clk_config[i].max_rate = rate;
195179 }
196180
197181 mp->num_clk = num_clk;