modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
..
..
@@ -1,20 +1,11 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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3
  */
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4
 
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 #include "dpu_hwio.h"
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 #include "dpu_hw_catalog.h"
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 #include "dpu_hw_lm.h"
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 #include "dpu_hw_sspp.h"
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-#include "dpu_dbg.h"
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 #include "dpu_kms.h"
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10
 
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 #define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087
..
..
@@ -141,7 +132,8 @@
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 /* traffic shaper clock in Hz */
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 #define TS_CLK			19200000
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134
 
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-static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
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+
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+static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
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 		int s_id,
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 		u32 *idx)
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 {
..
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@@ -313,11 +305,25 @@
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 		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
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 			DPU_FETCH_CONFIG_RESET_VALUE |
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 			ctx->mdp->highest_bank_bit << 18);
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-		if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) {
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+		switch (ctx->catalog->caps->ubwc_version) {
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+		case DPU_HW_UBWC_VER_10:
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+			/* TODO: UBWC v1 case */
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+			break;
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+		case DPU_HW_UBWC_VER_20:
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 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
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 			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
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 					fast_clear | (ctx->mdp->ubwc_swizzle) |
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 					(ctx->mdp->highest_bank_bit << 4));
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+			break;
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+		case DPU_HW_UBWC_VER_30:
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+			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
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+					BIT(30) | (ctx->mdp->ubwc_swizzle) |
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+					(ctx->mdp->highest_bank_bit << 4));
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+			break;
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+		case DPU_HW_UBWC_VER_40:
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+			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
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+					DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
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+			break;
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 		}
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 	}
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@@ -664,10 +670,12 @@
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 		test_bit(DPU_SSPP_CSC_10BIT, &features))
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 		c->ops.setup_csc = dpu_hw_sspp_setup_csc;
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672
 
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-	if (dpu_hw_sspp_multirect_enabled(c->cap))
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+	if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
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+		test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
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 		c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
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-	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) {
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+	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
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+			test_bit(DPU_SSPP_SCALER_QSEED4, &features)) {
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 		c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
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 		c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
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 	}
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@@ -676,7 +684,7 @@
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 		c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
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 }
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-static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
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+static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
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 		void __iomem *addr,
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 		struct dpu_mdss_cfg *catalog,
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 		struct dpu_hw_blk_reg_map *b)
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@@ -699,18 +707,14 @@
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 	return ERR_PTR(-ENOMEM);
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 }
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709
 
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-static struct dpu_hw_blk_ops dpu_hw_ops = {
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-	.start = NULL,
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-	.stop = NULL,
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-};
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+static struct dpu_hw_blk_ops dpu_hw_ops;
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 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
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 		void __iomem *addr, struct dpu_mdss_cfg *catalog,
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 		bool is_virtual_pipe)
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 {
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 	struct dpu_hw_pipe *hw_pipe;
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-	struct dpu_sspp_cfg *cfg;
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-	int rc;
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+	const struct dpu_sspp_cfg *cfg;
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 	if (!addr || !catalog)
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 		return ERR_PTR(-EINVAL);
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@@ -732,18 +736,9 @@
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 	hw_pipe->cap = cfg;
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 	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
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-	rc = dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
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-	if (rc) {
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-		DPU_ERROR("failed to init hw blk %d\n", rc);
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-		goto blk_init_error;
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-	}
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+	dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
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 	return hw_pipe;
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-
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-blk_init_error:
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-	kzfree(hw_pipe);
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-
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-	return ERR_PTR(rc);
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 }
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 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)