forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
....@@ -1,34 +1,26 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
34  * Copyright (C) 2013 Red Hat
45  * Author: Rob Clark <robdclark@gmail.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms of the GNU General Public License version 2 as published by
8
- * the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program.  If not, see <http://www.gnu.org/licenses/>.
176  */
187 
198 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
20
-#include <linux/kthread.h>
219 #include <linux/debugfs.h>
10
+#include <linux/kthread.h>
2211 #include <linux/seq_file.h>
12
+
13
+#include <drm/drm_crtc.h>
14
+#include <drm/drm_file.h>
15
+#include <drm/drm_probe_helper.h>
2316 
2417 #include "msm_drv.h"
2518 #include "dpu_kms.h"
26
-#include <drm/drm_crtc.h>
27
-#include <drm/drm_crtc_helper.h>
2819 #include "dpu_hwio.h"
2920 #include "dpu_hw_catalog.h"
3021 #include "dpu_hw_intf.h"
3122 #include "dpu_hw_ctl.h"
23
+#include "dpu_hw_dspp.h"
3224 #include "dpu_formats.h"
3325 #include "dpu_encoder_phys.h"
3426 #include "dpu_crtc.h"
....@@ -65,11 +57,12 @@
6557 
6658 #define MAX_CHANNELS_PER_ENC 2
6759 
68
-#define MISR_BUFF_SIZE			256
69
-
7060 #define IDLE_SHORT_TIMEOUT	1
7161 
72
-#define MAX_VDISPLAY_SPLIT 1080
62
+#define MAX_HDISPLAY_SPLIT 1080
63
+
64
+/* timeout in frames waiting for frame done */
65
+#define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
7366 
7467 /**
7568  * enum dpu_enc_rc_events - events for resource control state machine
....@@ -132,8 +125,9 @@
132125  *	Virtual encoder defers as much as possible to the physical encoders.
133126  *	Virtual encoder registers itself with the DRM Framework as the encoder.
134127  * @base:		drm_encoder base class for registration with DRM
135
- * @enc_spin_lock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
128
+ * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
136129  * @bus_scaling_client:	Client handle to the bus scaling interface
130
+ * @enabled:		True if the encoder is active, protected by enc_lock
137131  * @num_phys_encs:	Actual number of physical encoders contained.
138132  * @phys_encs:		Container of physical encoders managed.
139133  * @cur_master:		Pointer to the current master in this mode. Optimization
....@@ -143,26 +137,26 @@
143137  * @intfs_swapped	Whether or not the phys_enc interfaces have been swapped
144138  *			for partial update right-only cases, such as pingpong
145139  *			split where virtual pingpong does not generate IRQs
146
- * @crtc_vblank_cb:	Callback into the upper layer / CRTC for
147
- *			notification of the VBLANK
148
- * @crtc_vblank_cb_data:	Data from upper layer for VBLANK notification
140
+ * @crtc:		Pointer to the currently assigned crtc. Normally you
141
+ *			would use crtc->state->encoder_mask to determine the
142
+ *			link between encoder/crtc. However in this case we need
143
+ *			to track crtc in the disable() hook which is called
144
+ *			_after_ encoder_mask is cleared.
149145  * @crtc_kickoff_cb:		Callback into CRTC that will flush & start
150146  *				all CTL paths
151147  * @crtc_kickoff_cb_data:	Opaque user data given to crtc_kickoff_cb
152148  * @debugfs_root:		Debug file system root file node
153
- * @enc_lock:			Lock around physical encoder create/destroy and
154
-				access.
149
+ * @enc_lock:			Lock around physical encoder
150
+ *				create/destroy/enable/disable
155151  * @frame_busy_mask:		Bitmask tracking which phys_enc we are still
156152  *				busy processing current command.
157153  *				Bit0 = phys_encs[0] etc.
158154  * @crtc_frame_event_cb:	callback handler for frame event
159155  * @crtc_frame_event_cb_data:	callback handler private data
160
- * @frame_done_timeout:		frame done timeout in Hz
156
+ * @frame_done_timeout_ms:	frame done timeout in ms
161157  * @frame_done_timer:		watchdog timer for frame done event
162158  * @vsync_event_timer:		vsync timer
163159  * @disp_info:			local copy of msm_display_info struct
164
- * @misr_enable:		misr enable/disable status
165
- * @misr_frame_count:		misr frame count before start capturing the data
166160  * @idle_pc_supported:		indicate if idle power collaps is supported
167161  * @rc_lock:			resource control mutex lock to protect
168162  *				virt encoder over various state changes
....@@ -171,7 +165,6 @@
171165  *				clks and resources after IDLE_TIMEOUT time.
172166  * @vsync_event_work:		worker to handle vsync event for autorefresh
173167  * @topology:                   topology of the display
174
- * @mode_set_complete:          flag to indicate modeset completion
175168  * @idle_timeout:		idle timeout duration in milliseconds
176169  */
177170 struct dpu_encoder_virt {
....@@ -179,17 +172,17 @@
179172 	spinlock_t enc_spinlock;
180173 	uint32_t bus_scaling_client;
181174 
182
-	uint32_t display_num_of_h_tiles;
175
+	bool enabled;
183176 
184177 	unsigned int num_phys_encs;
185178 	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
186179 	struct dpu_encoder_phys *cur_master;
180
+	struct dpu_encoder_phys *cur_slave;
187181 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
188182 
189183 	bool intfs_swapped;
190184 
191
-	void (*crtc_vblank_cb)(void *);
192
-	void *crtc_vblank_cb_data;
185
+	struct drm_crtc *crtc;
193186 
194187 	struct dentry *debugfs_root;
195188 	struct mutex enc_lock;
....@@ -197,58 +190,52 @@
197190 	void (*crtc_frame_event_cb)(void *, u32 event);
198191 	void *crtc_frame_event_cb_data;
199192 
200
-	atomic_t frame_done_timeout;
193
+	atomic_t frame_done_timeout_ms;
201194 	struct timer_list frame_done_timer;
202195 	struct timer_list vsync_event_timer;
203196 
204197 	struct msm_display_info disp_info;
205
-	bool misr_enable;
206
-	u32 misr_frame_count;
207198 
208199 	bool idle_pc_supported;
209200 	struct mutex rc_lock;
210201 	enum dpu_enc_rc_states rc_state;
211
-	struct kthread_delayed_work delayed_off_work;
202
+	struct delayed_work delayed_off_work;
212203 	struct kthread_work vsync_event_work;
213204 	struct msm_display_topology topology;
214
-	bool mode_set_complete;
215205 
216206 	u32 idle_timeout;
217207 };
218208 
219209 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
220
-static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
221
-								bool enable)
210
+
211
+static u32 dither_matrix[DITHER_MATRIX_SZ] = {
212
+	15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
213
+};
214
+
215
+static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
222216 {
223
-	struct drm_encoder *drm_enc;
224
-	struct msm_drm_private *priv;
225
-	struct dpu_kms *dpu_kms;
217
+	struct dpu_hw_dither_cfg dither_cfg = { 0 };
226218 
227
-	if (!dpu_enc) {
228
-		DPU_ERROR("invalid dpu enc\n");
229
-		return -EINVAL;
219
+	if (!hw_pp->ops.setup_dither)
220
+		return;
221
+
222
+	switch (bpc) {
223
+	case 6:
224
+		dither_cfg.c0_bitdepth = 6;
225
+		dither_cfg.c1_bitdepth = 6;
226
+		dither_cfg.c2_bitdepth = 6;
227
+		dither_cfg.c3_bitdepth = 6;
228
+		dither_cfg.temporal_en = 0;
229
+		break;
230
+	default:
231
+		hw_pp->ops.setup_dither(hw_pp, NULL);
232
+		return;
230233 	}
231234 
232
-	drm_enc = &dpu_enc->base;
233
-	if (!drm_enc->dev || !drm_enc->dev->dev_private) {
234
-		DPU_ERROR("drm device invalid\n");
235
-		return -EINVAL;
236
-	}
235
+	memcpy(&dither_cfg.matrix, dither_matrix,
236
+			sizeof(u32) * DITHER_MATRIX_SZ);
237237 
238
-	priv = drm_enc->dev->dev_private;
239
-	if (!priv->kms) {
240
-		DPU_ERROR("invalid kms\n");
241
-		return -EINVAL;
242
-	}
243
-
244
-	dpu_kms = to_dpu_kms(priv->kms);
245
-
246
-	if (enable)
247
-		pm_runtime_get_sync(&dpu_kms->pdev->dev);
248
-	else
249
-		pm_runtime_put_sync(&dpu_kms->pdev->dev);
250
-
251
-	return 0;
238
+	hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
252239 }
253240 
254241 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
....@@ -275,7 +262,7 @@
275262 	u32 irq_status;
276263 	int ret;
277264 
278
-	if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
265
+	if (!wait_info || intr_idx >= INTR_IDX_MAX) {
279266 		DPU_ERROR("invalid params\n");
280267 		return -EINVAL;
281268 	}
....@@ -350,7 +337,7 @@
350337 	struct dpu_encoder_irq *irq;
351338 	int ret = 0;
352339 
353
-	if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
340
+	if (intr_idx >= INTR_IDX_MAX) {
354341 		DPU_ERROR("invalid params\n");
355342 		return -EINVAL;
356343 	}
....@@ -405,10 +392,6 @@
405392 	struct dpu_encoder_irq *irq;
406393 	int ret;
407394 
408
-	if (!phys_enc) {
409
-		DPU_ERROR("invalid encoder\n");
410
-		return -EINVAL;
411
-	}
412395 	irq = &phys_enc->irq[intr_idx];
413396 
414397 	/* silently skip irqs that weren't registered */
....@@ -443,30 +426,22 @@
443426 }
444427 
445428 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
446
-		struct dpu_encoder_hw_resources *hw_res,
447
-		struct drm_connector_state *conn_state)
429
+				  struct dpu_encoder_hw_resources *hw_res)
448430 {
449431 	struct dpu_encoder_virt *dpu_enc = NULL;
450432 	int i = 0;
451
-
452
-	if (!hw_res || !drm_enc || !conn_state) {
453
-		DPU_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
454
-				drm_enc != 0, hw_res != 0, conn_state != 0);
455
-		return;
456
-	}
457433 
458434 	dpu_enc = to_dpu_encoder_virt(drm_enc);
459435 	DPU_DEBUG_ENC(dpu_enc, "\n");
460436 
461437 	/* Query resources used by phys encs, expected to be without overlap */
462438 	memset(hw_res, 0, sizeof(*hw_res));
463
-	hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
464439 
465440 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
466441 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
467442 
468
-		if (phys && phys->ops.get_hw_resources)
469
-			phys->ops.get_hw_resources(phys, hw_res, conn_state);
443
+		if (phys->ops.get_hw_resources)
444
+			phys->ops.get_hw_resources(phys, hw_res);
470445 	}
471446 }
472447 
....@@ -488,7 +463,7 @@
488463 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
489464 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
490465 
491
-		if (phys && phys->ops.destroy) {
466
+		if (phys->ops.destroy) {
492467 			phys->ops.destroy(phys);
493468 			--dpu_enc->num_phys_encs;
494469 			dpu_enc->phys_encs[i] = NULL;
....@@ -514,8 +489,8 @@
514489 	struct dpu_hw_mdp *hw_mdptop;
515490 	struct msm_display_info *disp_info;
516491 
517
-	if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
518
-		DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
492
+	if (!phys_enc->hw_mdptop || !phys_enc->parent) {
493
+		DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
519494 		return;
520495 	}
521496 
....@@ -523,7 +498,7 @@
523498 	hw_mdptop = phys_enc->hw_mdptop;
524499 	disp_info = &dpu_enc->disp_info;
525500 
526
-	if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
501
+	if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
527502 		return;
528503 
529504 	/**
....@@ -554,38 +529,43 @@
554529 	}
555530 }
556531 
557
-static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
558
-		struct drm_display_mode *adj_mode)
559
-{
560
-	struct drm_display_mode *cur_mode;
561
-
562
-	if (!connector || !adj_mode)
563
-		return;
564
-
565
-	list_for_each_entry(cur_mode, &connector->modes, head) {
566
-		if (cur_mode->vdisplay == adj_mode->vdisplay &&
567
-			cur_mode->hdisplay == adj_mode->hdisplay &&
568
-			cur_mode->vrefresh == adj_mode->vrefresh) {
569
-			adj_mode->private = cur_mode->private;
570
-			adj_mode->private_flags |= cur_mode->private_flags;
571
-		}
572
-	}
573
-}
574
-
575532 static struct msm_display_topology dpu_encoder_get_topology(
576533 			struct dpu_encoder_virt *dpu_enc,
577534 			struct dpu_kms *dpu_kms,
578535 			struct drm_display_mode *mode)
579536 {
580
-	struct msm_display_topology topology;
537
+	struct msm_display_topology topology = {0};
581538 	int i, intf_count = 0;
582539 
583540 	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
584541 		if (dpu_enc->phys_encs[i])
585542 			intf_count++;
586543 
587
-	/* User split topology for width > 1080 */
588
-	topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
544
+	/* Datapath topology selection
545
+	 *
546
+	 * Dual display
547
+	 * 2 LM, 2 INTF ( Split display using 2 interfaces)
548
+	 *
549
+	 * Single display
550
+	 * 1 LM, 1 INTF
551
+	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
552
+	 *
553
+	 * Adding color blocks only to primary interface if available in
554
+	 * sufficient number
555
+	 */
556
+	if (intf_count == 2)
557
+		topology.num_lm = 2;
558
+	else if (!dpu_kms->catalog->caps->has_3d_merge)
559
+		topology.num_lm = 1;
560
+	else
561
+		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
562
+
563
+	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
564
+		if (dpu_kms->catalog->dspp &&
565
+			(dpu_kms->catalog->dspp_count >= topology.num_lm))
566
+			topology.num_dspp = topology.num_lm;
567
+	}
568
+
589569 	topology.num_enc = 0;
590570 	topology.num_intf = intf_count;
591571 
....@@ -602,12 +582,13 @@
602582 	const struct drm_display_mode *mode;
603583 	struct drm_display_mode *adj_mode;
604584 	struct msm_display_topology topology;
585
+	struct dpu_global_state *global_state;
605586 	int i = 0;
606587 	int ret = 0;
607588 
608589 	if (!drm_enc || !crtc_state || !conn_state) {
609590 		DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
610
-				drm_enc != 0, crtc_state != 0, conn_state != 0);
591
+				drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
611592 		return -EINVAL;
612593 	}
613594 
....@@ -618,25 +599,20 @@
618599 	dpu_kms = to_dpu_kms(priv->kms);
619600 	mode = &crtc_state->mode;
620601 	adj_mode = &crtc_state->adjusted_mode;
621
-	trace_dpu_enc_atomic_check(DRMID(drm_enc));
602
+	global_state = dpu_kms_get_global_state(crtc_state->state);
603
+	if (IS_ERR(global_state))
604
+		return PTR_ERR(global_state);
622605 
623
-	/*
624
-	 * display drivers may populate private fields of the drm display mode
625
-	 * structure while registering possible modes of a connector with DRM.
626
-	 * These private fields are not populated back while DRM invokes
627
-	 * the mode_set callbacks. This module retrieves and populates the
628
-	 * private fields of the given mode.
629
-	 */
630
-	_dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
606
+	trace_dpu_enc_atomic_check(DRMID(drm_enc));
631607 
632608 	/* perform atomic check on the first physical encoder (master) */
633609 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
634610 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
635611 
636
-		if (phys && phys->ops.atomic_check)
612
+		if (phys->ops.atomic_check)
637613 			ret = phys->ops.atomic_check(phys, crtc_state,
638614 					conn_state);
639
-		else if (phys && phys->ops.mode_fixup)
615
+		else if (phys->ops.mode_fixup)
640616 			if (!phys->ops.mode_fixup(phys, mode, adj_mode))
641617 				ret = -EINVAL;
642618 
....@@ -649,25 +625,22 @@
649625 
650626 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
651627 
652
-	/* Reserve dynamic resources now. Indicating AtomicTest phase */
628
+	/* Reserve dynamic resources now. */
653629 	if (!ret) {
654630 		/*
655
-		 * Avoid reserving resources when mode set is pending. Topology
656
-		 * info may not be available to complete reservation.
631
+		 * Release and Allocate resources on every modeset
632
+		 * Dont allocate when active is false.
657633 		 */
658
-		if (drm_atomic_crtc_needs_modeset(crtc_state)
659
-				&& dpu_enc->mode_set_complete) {
660
-			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
661
-				conn_state, topology, true);
662
-			dpu_enc->mode_set_complete = false;
634
+		if (drm_atomic_crtc_needs_modeset(crtc_state)) {
635
+			dpu_rm_release(global_state, drm_enc);
636
+
637
+			if (!crtc_state->active_changed || crtc_state->enable)
638
+				ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
639
+						drm_enc, crtc_state, topology);
663640 		}
664641 	}
665642 
666
-	if (!ret)
667
-		drm_mode_set_crtcinfo(adj_mode, 0);
668
-
669
-	trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
670
-			adj_mode->private_flags);
643
+	trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
671644 
672645 	return ret;
673646 }
....@@ -698,11 +671,6 @@
698671 	priv = drm_enc->dev->dev_private;
699672 
700673 	dpu_kms = to_dpu_kms(priv->kms);
701
-	if (!dpu_kms) {
702
-		DPU_ERROR("invalid dpu_kms\n");
703
-		return;
704
-	}
705
-
706674 	hw_mdptop = dpu_kms->hw_mdp;
707675 	if (!hw_mdptop) {
708676 		DPU_ERROR("invalid mdptop\n");
....@@ -740,7 +708,7 @@
740708 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
741709 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
742710 
743
-		if (phys && phys->ops.irq_control)
711
+		if (phys->ops.irq_control)
744712 			phys->ops.irq_control(phys, enable);
745713 	}
746714 
....@@ -786,11 +754,9 @@
786754 {
787755 	struct dpu_encoder_virt *dpu_enc;
788756 	struct msm_drm_private *priv;
789
-	struct msm_drm_thread *disp_thread;
790757 	bool is_vid_mode = false;
791758 
792
-	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private ||
793
-			!drm_enc->crtc) {
759
+	if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
794760 		DPU_ERROR("invalid parameters\n");
795761 		return -EINVAL;
796762 	}
....@@ -798,12 +764,6 @@
798764 	priv = drm_enc->dev->dev_private;
799765 	is_vid_mode = dpu_enc->disp_info.capabilities &
800766 						MSM_DISPLAY_CAP_VID_MODE;
801
-
802
-	if (drm_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
803
-		DPU_ERROR("invalid crtc index\n");
804
-		return -EINVAL;
805
-	}
806
-	disp_thread = &priv->disp_thread[drm_enc->crtc->index];
807767 
808768 	/*
809769 	 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
....@@ -821,8 +781,7 @@
821781 	switch (sw_event) {
822782 	case DPU_ENC_RC_EVENT_KICKOFF:
823783 		/* cancel delayed off work, if any */
824
-		if (kthread_cancel_delayed_work_sync(
825
-				&dpu_enc->delayed_off_work))
784
+		if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
826785 			DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
827786 					sw_event);
828787 
....@@ -881,10 +840,8 @@
881840 			return 0;
882841 		}
883842 
884
-		kthread_queue_delayed_work(
885
-			&disp_thread->worker,
886
-			&dpu_enc->delayed_off_work,
887
-			msecs_to_jiffies(dpu_enc->idle_timeout));
843
+		queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
844
+				   msecs_to_jiffies(dpu_enc->idle_timeout));
888845 
889846 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
890847 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
....@@ -893,8 +850,7 @@
893850 
894851 	case DPU_ENC_RC_EVENT_PRE_STOP:
895852 		/* cancel delayed off work, if any */
896
-		if (kthread_cancel_delayed_work_sync(
897
-				&dpu_enc->delayed_off_work))
853
+		if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
898854 			DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
899855 					sw_event);
900856 
....@@ -1014,10 +970,16 @@
1014970 	struct dpu_kms *dpu_kms;
1015971 	struct list_head *connector_list;
1016972 	struct drm_connector *conn = NULL, *conn_iter;
1017
-	struct dpu_rm_hw_iter pp_iter;
973
+	struct drm_crtc *drm_crtc;
974
+	struct dpu_crtc_state *cstate;
975
+	struct dpu_global_state *global_state;
1018976 	struct msm_display_topology topology;
1019
-	enum dpu_rm_topology_name topology_name;
1020
-	int i = 0, ret;
977
+	struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
978
+	struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
979
+	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
980
+	struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
981
+	int num_lm, num_ctl, num_pp, num_dspp;
982
+	int i, j;
1021983 
1022984 	if (!drm_enc) {
1023985 		DPU_ERROR("invalid encoder\n");
....@@ -1031,7 +993,16 @@
1031993 	dpu_kms = to_dpu_kms(priv->kms);
1032994 	connector_list = &dpu_kms->dev->mode_config.connector_list;
1033995 
996
+	global_state = dpu_kms_get_existing_global_state(dpu_kms);
997
+	if (IS_ERR_OR_NULL(global_state)) {
998
+		DPU_ERROR("Failed to get global state");
999
+		return;
1000
+	}
1001
+
10341002 	trace_dpu_enc_mode_set(DRMID(drm_enc));
1003
+
1004
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp)
1005
+		msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode);
10351006 
10361007 	list_for_each_entry(conn_iter, connector_list, head)
10371008 		if (conn_iter->encoder == drm_enc)
....@@ -1045,63 +1016,95 @@
10451016 		return;
10461017 	}
10471018 
1019
+	drm_for_each_crtc(drm_crtc, drm_enc->dev)
1020
+		if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
1021
+			break;
1022
+
10481023 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
10491024 
1050
-	/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
1051
-	ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state,
1052
-			conn->state, topology, false);
1053
-	if (ret) {
1054
-		DPU_ERROR_ENC(dpu_enc,
1055
-				"failed to reserve hw resources, %d\n", ret);
1056
-		return;
1025
+	/* Query resource that have been reserved in atomic check step. */
1026
+	num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1027
+		drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1028
+		ARRAY_SIZE(hw_pp));
1029
+	num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1030
+		drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1031
+	num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1032
+		drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1033
+	num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1034
+		drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1035
+		ARRAY_SIZE(hw_dspp));
1036
+
1037
+	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1038
+		dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1039
+						: NULL;
1040
+
1041
+	cstate = to_dpu_crtc_state(drm_crtc->state);
1042
+
1043
+	for (i = 0; i < num_lm; i++) {
1044
+		int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1045
+
1046
+		cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1047
+		cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1048
+		cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
10571049 	}
10581050 
1059
-	dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
1060
-	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1061
-		dpu_enc->hw_pp[i] = NULL;
1062
-		if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
1063
-			break;
1064
-		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
1065
-	}
1051
+	cstate->num_mixers = num_lm;
10661052 
1067
-	topology_name = dpu_rm_get_topology_name(topology);
10681053 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1054
+		int num_blk;
1055
+		struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
10691056 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
10701057 
1071
-		if (phys) {
1072
-			if (!dpu_enc->hw_pp[i]) {
1073
-				DPU_ERROR_ENC(dpu_enc,
1074
-				    "invalid pingpong block for the encoder\n");
1075
-				return;
1076
-			}
1077
-			phys->hw_pp = dpu_enc->hw_pp[i];
1078
-			phys->connector = conn->state->connector;
1079
-			phys->topology_name = topology_name;
1080
-			if (phys->ops.mode_set)
1081
-				phys->ops.mode_set(phys, mode, adj_mode);
1058
+		if (!dpu_enc->hw_pp[i]) {
1059
+			DPU_ERROR_ENC(dpu_enc,
1060
+				"no pp block assigned at idx: %d\n", i);
1061
+			return;
10821062 		}
1083
-	}
10841063 
1085
-	dpu_enc->mode_set_complete = true;
1064
+		if (!hw_ctl[i]) {
1065
+			DPU_ERROR_ENC(dpu_enc,
1066
+				"no ctl block assigned at idx: %d\n", i);
1067
+			return;
1068
+		}
1069
+
1070
+		phys->hw_pp = dpu_enc->hw_pp[i];
1071
+		phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1072
+
1073
+		num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,
1074
+			global_state, drm_enc->base.id, DPU_HW_BLK_INTF,
1075
+			hw_blk, ARRAY_SIZE(hw_blk));
1076
+		for (j = 0; j < num_blk; j++) {
1077
+			struct dpu_hw_intf *hw_intf;
1078
+
1079
+			hw_intf = to_dpu_hw_intf(hw_blk[i]);
1080
+			if (hw_intf->idx == phys->intf_idx)
1081
+				phys->hw_intf = hw_intf;
1082
+		}
1083
+
1084
+		if (!phys->hw_intf) {
1085
+			DPU_ERROR_ENC(dpu_enc,
1086
+				      "no intf block assigned at idx: %d\n", i);
1087
+			return;
1088
+		}
1089
+
1090
+		phys->connector = conn->state->connector;
1091
+		if (phys->ops.mode_set)
1092
+			phys->ops.mode_set(phys, mode, adj_mode);
1093
+	}
10861094 }
10871095 
10881096 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
10891097 {
10901098 	struct dpu_encoder_virt *dpu_enc = NULL;
10911099 	struct msm_drm_private *priv;
1092
-	struct dpu_kms *dpu_kms;
1100
+	int i;
10931101 
1094
-	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
1102
+	if (!drm_enc || !drm_enc->dev) {
10951103 		DPU_ERROR("invalid parameters\n");
10961104 		return;
10971105 	}
10981106 
10991107 	priv = drm_enc->dev->dev_private;
1100
-	dpu_kms = to_dpu_kms(priv->kms);
1101
-	if (!dpu_kms) {
1102
-		DPU_ERROR("invalid dpu_kms\n");
1103
-		return;
1104
-	}
11051108 
11061109 	dpu_enc = to_dpu_encoder_virt(drm_enc);
11071110 	if (!dpu_enc || !dpu_enc->cur_master) {
....@@ -1109,49 +1112,51 @@
11091112 		return;
11101113 	}
11111114 
1112
-	if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
1113
-	    dpu_enc->cur_master->hw_mdptop &&
1114
-	    dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1115
-		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1116
-					dpu_enc->cur_master->hw_mdptop);
11171115 
1118
-	if (dpu_enc->cur_master->hw_mdptop &&
1119
-			dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1120
-		dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1121
-				dpu_enc->cur_master->hw_mdptop,
1122
-				dpu_kms->catalog);
1116
+	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
1117
+		dpu_enc->cur_master->hw_mdptop &&
1118
+		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1119
+		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1120
+			dpu_enc->cur_master->hw_mdptop);
11231121 
11241122 	_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1123
+
1124
+	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1125
+			!WARN_ON(dpu_enc->num_phys_encs == 0)) {
1126
+		unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc;
1127
+		for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1128
+			if (!dpu_enc->hw_pp[i])
1129
+				continue;
1130
+			_dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1131
+		}
1132
+	}
11251133 }
11261134 
1127
-void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
1135
+void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
11281136 {
1129
-	struct dpu_encoder_virt *dpu_enc = NULL;
1130
-	int i;
1137
+	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
11311138 
1132
-	if (!drm_enc) {
1133
-		DPU_ERROR("invalid encoder\n");
1134
-		return;
1135
-	}
1136
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
1139
+	mutex_lock(&dpu_enc->enc_lock);
11371140 
1138
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1139
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1141
+	if (!dpu_enc->enabled)
1142
+		goto out;
11401143 
1141
-		if (phys && (phys != dpu_enc->cur_master) && phys->ops.restore)
1142
-			phys->ops.restore(phys);
1143
-	}
1144
-
1144
+	if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1145
+		dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
11451146 	if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
11461147 		dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
11471148 
11481149 	_dpu_encoder_virt_enable_helper(drm_enc);
1150
+
1151
+out:
1152
+	mutex_unlock(&dpu_enc->enc_lock);
11491153 }
11501154 
11511155 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
11521156 {
11531157 	struct dpu_encoder_virt *dpu_enc = NULL;
1154
-	int i, ret = 0;
1158
+	int ret = 0;
1159
+	struct msm_drm_private *priv;
11551160 	struct drm_display_mode *cur_mode = NULL;
11561161 
11571162 	if (!drm_enc) {
....@@ -1159,55 +1164,43 @@
11591164 		return;
11601165 	}
11611166 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1167
+
1168
+	mutex_lock(&dpu_enc->enc_lock);
11621169 	cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1170
+	priv = drm_enc->dev->dev_private;
11631171 
11641172 	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
11651173 			     cur_mode->vdisplay);
11661174 
1167
-	dpu_enc->cur_master = NULL;
1168
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1169
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1175
+	/* always enable slave encoder before master */
1176
+	if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1177
+		dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
11701178 
1171
-		if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
1172
-			DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
1173
-			dpu_enc->cur_master = phys;
1174
-			break;
1175
-		}
1176
-	}
1177
-
1178
-	if (!dpu_enc->cur_master) {
1179
-		DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
1180
-		return;
1181
-	}
1179
+	if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1180
+		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
11821181 
11831182 	ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
11841183 	if (ret) {
11851184 		DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
11861185 				ret);
1187
-		return;
1186
+		goto out;
11881187 	}
1189
-
1190
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1191
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1192
-
1193
-		if (!phys)
1194
-			continue;
1195
-
1196
-		if (phys != dpu_enc->cur_master) {
1197
-			if (phys->ops.enable)
1198
-				phys->ops.enable(phys);
1199
-		}
1200
-
1201
-		if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities &
1202
-		     MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr)
1203
-			phys->ops.setup_misr(phys, true,
1204
-						dpu_enc->misr_frame_count);
1205
-	}
1206
-
1207
-	if (dpu_enc->cur_master->ops.enable)
1208
-		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
12091188 
12101189 	_dpu_encoder_virt_enable_helper(drm_enc);
1190
+
1191
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1192
+		ret = msm_dp_display_enable(priv->dp,
1193
+						drm_enc);
1194
+		if (ret) {
1195
+			DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
1196
+				ret);
1197
+			goto out;
1198
+		}
1199
+	}
1200
+	dpu_enc->enabled = true;
1201
+
1202
+out:
1203
+	mutex_unlock(&dpu_enc->enc_lock);
12111204 }
12121205 
12131206 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
....@@ -1215,7 +1208,6 @@
12151208 	struct dpu_encoder_virt *dpu_enc = NULL;
12161209 	struct msm_drm_private *priv;
12171210 	struct dpu_kms *dpu_kms;
1218
-	struct drm_display_mode *mode;
12191211 	int i = 0;
12201212 
12211213 	if (!drm_enc) {
....@@ -1224,15 +1216,13 @@
12241216 	} else if (!drm_enc->dev) {
12251217 		DPU_ERROR("invalid dev\n");
12261218 		return;
1227
-	} else if (!drm_enc->dev->dev_private) {
1228
-		DPU_ERROR("invalid dev_private\n");
1229
-		return;
12301219 	}
1231
-
1232
-	mode = &drm_enc->crtc->state->adjusted_mode;
12331220 
12341221 	dpu_enc = to_dpu_encoder_virt(drm_enc);
12351222 	DPU_DEBUG_ENC(dpu_enc, "\n");
1223
+
1224
+	mutex_lock(&dpu_enc->enc_lock);
1225
+	dpu_enc->enabled = false;
12361226 
12371227 	priv = drm_enc->dev->dev_private;
12381228 	dpu_kms = to_dpu_kms(priv->kms);
....@@ -1242,17 +1232,23 @@
12421232 	/* wait for idle */
12431233 	dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
12441234 
1235
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1236
+		if (msm_dp_display_pre_disable(priv->dp, drm_enc))
1237
+			DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
1238
+	}
1239
+
12451240 	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
12461241 
12471242 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
12481243 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
12491244 
1250
-		if (phys && phys->ops.disable)
1245
+		if (phys->ops.disable)
12511246 			phys->ops.disable(phys);
12521247 	}
12531248 
1249
+
12541250 	/* after phys waits for frame-done, should be no more frames pending */
1255
-	if (atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
1251
+	if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
12561252 		DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
12571253 		del_timer_sync(&dpu_enc->frame_done_timer);
12581254 	}
....@@ -1260,15 +1256,17 @@
12601256 	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
12611257 
12621258 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1263
-		if (dpu_enc->phys_encs[i])
1264
-			dpu_enc->phys_encs[i]->connector = NULL;
1259
+		dpu_enc->phys_encs[i]->connector = NULL;
12651260 	}
1266
-
1267
-	dpu_enc->cur_master = NULL;
12681261 
12691262 	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
12701263 
1271
-	dpu_rm_release(&dpu_kms->rm, drm_enc);
1264
+	if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1265
+		if (msm_dp_display_disable(priv->dp, drm_enc))
1266
+			DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
1267
+	}
1268
+
1269
+	mutex_unlock(&dpu_enc->enc_lock);
12721270 }
12731271 
12741272 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
....@@ -1299,8 +1297,8 @@
12991297 	dpu_enc = to_dpu_encoder_virt(drm_enc);
13001298 
13011299 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1302
-	if (dpu_enc->crtc_vblank_cb)
1303
-		dpu_enc->crtc_vblank_cb(dpu_enc->crtc_vblank_cb_data);
1300
+	if (dpu_enc->crtc)
1301
+		dpu_crtc_vblank_callback(dpu_enc->crtc);
13041302 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
13051303 
13061304 	atomic_inc(&phy_enc->vsync_cnt);
....@@ -1320,31 +1318,38 @@
13201318 	DPU_ATRACE_END("encoder_underrun_callback");
13211319 }
13221320 
1323
-void dpu_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
1324
-		void (*vbl_cb)(void *), void *vbl_data)
1321
+void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
13251322 {
13261323 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
13271324 	unsigned long lock_flags;
1328
-	bool enable;
1325
+
1326
+	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1327
+	/* crtc should always be cleared before re-assigning */
1328
+	WARN_ON(crtc && dpu_enc->crtc);
1329
+	dpu_enc->crtc = crtc;
1330
+	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1331
+}
1332
+
1333
+void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1334
+					struct drm_crtc *crtc, bool enable)
1335
+{
1336
+	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1337
+	unsigned long lock_flags;
13291338 	int i;
13301339 
1331
-	enable = vbl_cb ? true : false;
1332
-
1333
-	if (!drm_enc) {
1334
-		DPU_ERROR("invalid encoder\n");
1335
-		return;
1336
-	}
13371340 	trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
13381341 
13391342 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1340
-	dpu_enc->crtc_vblank_cb = vbl_cb;
1341
-	dpu_enc->crtc_vblank_cb_data = vbl_data;
1343
+	if (dpu_enc->crtc != crtc) {
1344
+		spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1345
+		return;
1346
+	}
13421347 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
13431348 
13441349 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
13451350 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
13461351 
1347
-		if (phys && phys->ops.control_vblank_irq)
1352
+		if (phys->ops.control_vblank_irq)
13481353 			phys->ops.control_vblank_irq(phys, enable);
13491354 	}
13501355 }
....@@ -1395,14 +1400,14 @@
13951400 		/* One of the physical encoders has become idle */
13961401 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
13971402 			if (dpu_enc->phys_encs[i] == ready_phys) {
1398
-				clear_bit(i, dpu_enc->frame_busy_mask);
13991403 				trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
14001404 						dpu_enc->frame_busy_mask[0]);
1405
+				clear_bit(i, dpu_enc->frame_busy_mask);
14011406 			}
14021407 		}
14031408 
14041409 		if (!dpu_enc->frame_busy_mask[0]) {
1405
-			atomic_set(&dpu_enc->frame_done_timeout, 0);
1410
+			atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
14061411 			del_timer(&dpu_enc->frame_done_timer);
14071412 
14081413 			dpu_encoder_resource_control(drm_enc,
....@@ -1420,7 +1425,7 @@
14201425 	}
14211426 }
14221427 
1423
-static void dpu_encoder_off_work(struct kthread_work *work)
1428
+static void dpu_encoder_off_work(struct work_struct *work)
14241429 {
14251430 	struct dpu_encoder_virt *dpu_enc = container_of(work,
14261431 			struct dpu_encoder_virt, delayed_off_work.work);
....@@ -1443,18 +1448,12 @@
14431448  * phys: Pointer to physical encoder structure
14441449  * extra_flush_bits: Additional bit mask to include in flush trigger
14451450  */
1446
-static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1451
+static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
14471452 		struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
14481453 {
14491454 	struct dpu_hw_ctl *ctl;
14501455 	int pending_kickoff_cnt;
14511456 	u32 ret = UINT_MAX;
1452
-
1453
-	if (!drm_enc || !phys) {
1454
-		DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
1455
-				drm_enc != 0, phys != 0);
1456
-		return;
1457
-	}
14581457 
14591458 	if (!phys->hw_pp) {
14601459 		DPU_ERROR("invalid pingpong hw\n");
....@@ -1462,7 +1461,7 @@
14621461 	}
14631462 
14641463 	ctl = phys->hw_ctl;
1465
-	if (!ctl || !ctl->ops.trigger_flush) {
1464
+	if (!ctl->ops.trigger_flush) {
14661465 		DPU_ERROR("missing trigger cb\n");
14671466 		return;
14681467 	}
....@@ -1478,14 +1477,15 @@
14781477 		ret = ctl->ops.get_pending_flush(ctl);
14791478 
14801479 	trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1481
-				    pending_kickoff_cnt, ctl->idx, ret);
1480
+				    pending_kickoff_cnt, ctl->idx,
1481
+				    extra_flush_bits, ret);
14821482 }
14831483 
14841484 /**
14851485  * _dpu_encoder_trigger_start - trigger start for a physical encoder
14861486  * phys: Pointer to physical encoder structure
14871487  */
1488
-static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1488
+static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
14891489 {
14901490 	if (!phys) {
14911491 		DPU_ERROR("invalid argument(s)\n");
....@@ -1505,13 +1505,8 @@
15051505 {
15061506 	struct dpu_hw_ctl *ctl;
15071507 
1508
-	if (!phys_enc) {
1509
-		DPU_ERROR("invalid encoder\n");
1510
-		return;
1511
-	}
1512
-
15131508 	ctl = phys_enc->hw_ctl;
1514
-	if (ctl && ctl->ops.trigger_start) {
1509
+	if (ctl->ops.trigger_start) {
15151510 		ctl->ops.trigger_start(ctl);
15161511 		trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
15171512 	}
....@@ -1542,30 +1537,24 @@
15421537 	return rc;
15431538 }
15441539 
1545
-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1540
+static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
15461541 {
15471542 	struct dpu_encoder_virt *dpu_enc;
15481543 	struct dpu_hw_ctl *ctl;
15491544 	int rc;
15501545 
1551
-	if (!phys_enc) {
1552
-		DPU_ERROR("invalid encoder\n");
1553
-		return;
1554
-	}
15551546 	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
15561547 	ctl = phys_enc->hw_ctl;
15571548 
1558
-	if (!ctl || !ctl->ops.reset)
1549
+	if (!ctl->ops.reset)
15591550 		return;
15601551 
15611552 	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
15621553 		      ctl->idx);
15631554 
15641555 	rc = ctl->ops.reset(ctl);
1565
-	if (rc) {
1556
+	if (rc)
15661557 		DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1567
-		dpu_dbg_dump(false, __func__, true, true);
1568
-	}
15691558 
15701559 	phys_enc->enable_state = DPU_ENC_ENABLED;
15711560 }
....@@ -1585,11 +1574,6 @@
15851574 	uint32_t i, pending_flush;
15861575 	unsigned long lock_flags;
15871576 
1588
-	if (!dpu_enc) {
1589
-		DPU_ERROR("invalid encoder\n");
1590
-		return;
1591
-	}
1592
-
15931577 	pending_flush = 0x0;
15941578 
15951579 	/* update pending counts and trigger kickoff ctl flush atomically */
....@@ -1599,15 +1583,19 @@
15991583 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
16001584 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
16011585 
1602
-		if (!phys || phys->enable_state == DPU_ENC_DISABLED)
1586
+		if (phys->enable_state == DPU_ENC_DISABLED)
16031587 			continue;
16041588 
16051589 		ctl = phys->hw_ctl;
1606
-		if (!ctl)
1607
-			continue;
16081590 
1591
+		/*
1592
+		 * This is cleared in frame_done worker, which isn't invoked
1593
+		 * for async commits. So don't set this for async, since it'll
1594
+		 * roll over to the next commit.
1595
+		 */
16091596 		if (phys->split_role != ENC_ROLE_SLAVE)
16101597 			set_bit(i, dpu_enc->frame_busy_mask);
1598
+
16111599 		if (!phys->ops.needs_single_flush ||
16121600 				!phys->ops.needs_single_flush(phys))
16131601 			_dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
....@@ -1646,17 +1634,15 @@
16461634 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
16471635 		phys = dpu_enc->phys_encs[i];
16481636 
1649
-		if (phys && phys->hw_ctl) {
1650
-			ctl = phys->hw_ctl;
1651
-			if (ctl->ops.clear_pending_flush)
1652
-				ctl->ops.clear_pending_flush(ctl);
1637
+		ctl = phys->hw_ctl;
1638
+		if (ctl->ops.clear_pending_flush)
1639
+			ctl->ops.clear_pending_flush(ctl);
16531640 
1654
-			/* update only for command mode primary ctl */
1655
-			if ((phys == dpu_enc->cur_master) &&
1656
-			   (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1657
-			    && ctl->ops.trigger_pending)
1658
-				ctl->ops.trigger_pending(ctl);
1659
-		}
1641
+		/* update only for command mode primary ctl */
1642
+		if ((phys == dpu_enc->cur_master) &&
1643
+		   (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1644
+		    && ctl->ops.trigger_pending)
1645
+			ctl->ops.trigger_pending(ctl);
16601646 	}
16611647 }
16621648 
....@@ -1707,8 +1693,7 @@
17071693 	return line_time;
17081694 }
17091695 
1710
-static int _dpu_encoder_wakeup_time(struct drm_encoder *drm_enc,
1711
-		ktime_t *wakeup_time)
1696
+int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
17121697 {
17131698 	struct drm_display_mode *mode;
17141699 	struct dpu_encoder_virt *dpu_enc;
....@@ -1762,8 +1747,7 @@
17621747 	struct msm_drm_private *priv;
17631748 	struct msm_drm_thread *event_thread;
17641749 
1765
-	if (!drm_enc->dev || !drm_enc->dev->dev_private ||
1766
-			!drm_enc->crtc) {
1750
+	if (!drm_enc->dev || !drm_enc->crtc) {
17671751 		DPU_ERROR("invalid parameters\n");
17681752 		return;
17691753 	}
....@@ -1795,7 +1779,7 @@
17951779 		return;
17961780 	}
17971781 
1798
-	if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time))
1782
+	if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
17991783 		return;
18001784 
18011785 	trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
....@@ -1803,18 +1787,13 @@
18031787 			nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
18041788 }
18051789 
1806
-void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
1807
-		struct dpu_encoder_kickoff_params *params)
1790
+void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
18081791 {
18091792 	struct dpu_encoder_virt *dpu_enc;
18101793 	struct dpu_encoder_phys *phys;
18111794 	bool needs_hw_reset = false;
18121795 	unsigned int i;
18131796 
1814
-	if (!drm_enc || !params) {
1815
-		DPU_ERROR("invalid args\n");
1816
-		return;
1817
-	}
18181797 	dpu_enc = to_dpu_encoder_virt(drm_enc);
18191798 
18201799 	trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
....@@ -1823,12 +1802,10 @@
18231802 	DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
18241803 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
18251804 		phys = dpu_enc->phys_encs[i];
1826
-		if (phys) {
1827
-			if (phys->ops.prepare_for_kickoff)
1828
-				phys->ops.prepare_for_kickoff(phys, params);
1829
-			if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1830
-				needs_hw_reset = true;
1831
-		}
1805
+		if (phys->ops.prepare_for_kickoff)
1806
+			phys->ops.prepare_for_kickoff(phys);
1807
+		if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1808
+			needs_hw_reset = true;
18321809 	}
18331810 	DPU_ATRACE_END("enc_prepare_for_kickoff");
18341811 
....@@ -1838,9 +1815,7 @@
18381815 	if (needs_hw_reset) {
18391816 		trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
18401817 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1841
-			phys = dpu_enc->phys_encs[i];
1842
-			if (phys && phys->ops.hw_reset)
1843
-				phys->ops.hw_reset(phys);
1818
+			dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
18441819 		}
18451820 	}
18461821 }
....@@ -1850,22 +1825,20 @@
18501825 	struct dpu_encoder_virt *dpu_enc;
18511826 	struct dpu_encoder_phys *phys;
18521827 	ktime_t wakeup_time;
1828
+	unsigned long timeout_ms;
18531829 	unsigned int i;
18541830 
1855
-	if (!drm_enc) {
1856
-		DPU_ERROR("invalid encoder\n");
1857
-		return;
1858
-	}
18591831 	DPU_ATRACE_BEGIN("encoder_kickoff");
18601832 	dpu_enc = to_dpu_encoder_virt(drm_enc);
18611833 
18621834 	trace_dpu_enc_kickoff(DRMID(drm_enc));
18631835 
1864
-	atomic_set(&dpu_enc->frame_done_timeout,
1865
-			DPU_FRAME_DONE_TIMEOUT * 1000 /
1866
-			drm_enc->crtc->state->adjusted_mode.vrefresh);
1867
-	mod_timer(&dpu_enc->frame_done_timer, jiffies +
1868
-		((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000));
1836
+	timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1837
+			drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1838
+
1839
+	atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1840
+	mod_timer(&dpu_enc->frame_done_timer,
1841
+			jiffies + msecs_to_jiffies(timeout_ms));
18691842 
18701843 	/* All phys encs are ready to go, trigger the kickoff */
18711844 	_dpu_encoder_kickoff_phys(dpu_enc);
....@@ -1873,12 +1846,12 @@
18731846 	/* allow phys encs to handle any post-kickoff business */
18741847 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
18751848 		phys = dpu_enc->phys_encs[i];
1876
-		if (phys && phys->ops.handle_post_kickoff)
1849
+		if (phys->ops.handle_post_kickoff)
18771850 			phys->ops.handle_post_kickoff(phys);
18781851 	}
18791852 
1880
-	if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
1881
-			!_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) {
1853
+	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1854
+			!dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
18821855 		trace_dpu_enc_early_kickoff(DRMID(drm_enc),
18831856 					    ktime_to_ms(wakeup_time));
18841857 		mod_timer(&dpu_enc->vsync_event_timer,
....@@ -1902,7 +1875,7 @@
19021875 
19031876 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
19041877 		phys = dpu_enc->phys_encs[i];
1905
-		if (phys && phys->ops.prepare_commit)
1878
+		if (phys->ops.prepare_commit)
19061879 			phys->ops.prepare_commit(phys);
19071880 	}
19081881 }
....@@ -1910,20 +1883,12 @@
19101883 #ifdef CONFIG_DEBUG_FS
19111884 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
19121885 {
1913
-	struct dpu_encoder_virt *dpu_enc;
1886
+	struct dpu_encoder_virt *dpu_enc = s->private;
19141887 	int i;
1915
-
1916
-	if (!s || !s->private)
1917
-		return -EINVAL;
1918
-
1919
-	dpu_enc = s->private;
19201888 
19211889 	mutex_lock(&dpu_enc->enc_lock);
19221890 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
19231891 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1924
-
1925
-		if (!phys)
1926
-			continue;
19271892 
19281893 		seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
19291894 				phys->intf_idx - INTF_0,
....@@ -1947,193 +1912,42 @@
19471912 	return 0;
19481913 }
19491914 
1950
-static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1951
-		struct file *file)
1952
-{
1953
-	return single_open(file, _dpu_encoder_status_show, inode->i_private);
1954
-}
1955
-
1956
-static ssize_t _dpu_encoder_misr_setup(struct file *file,
1957
-		const char __user *user_buf, size_t count, loff_t *ppos)
1958
-{
1959
-	struct dpu_encoder_virt *dpu_enc;
1960
-	int i = 0, rc;
1961
-	char buf[MISR_BUFF_SIZE + 1];
1962
-	size_t buff_copy;
1963
-	u32 frame_count, enable;
1964
-
1965
-	if (!file || !file->private_data)
1966
-		return -EINVAL;
1967
-
1968
-	dpu_enc = file->private_data;
1969
-
1970
-	buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
1971
-	if (copy_from_user(buf, user_buf, buff_copy))
1972
-		return -EINVAL;
1973
-
1974
-	buf[buff_copy] = 0; /* end of string */
1975
-
1976
-	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
1977
-		return -EINVAL;
1978
-
1979
-	rc = _dpu_encoder_power_enable(dpu_enc, true);
1980
-	if (rc)
1981
-		return rc;
1982
-
1983
-	mutex_lock(&dpu_enc->enc_lock);
1984
-	dpu_enc->misr_enable = enable;
1985
-	dpu_enc->misr_frame_count = frame_count;
1986
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1987
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1988
-
1989
-		if (!phys || !phys->ops.setup_misr)
1990
-			continue;
1991
-
1992
-		phys->ops.setup_misr(phys, enable, frame_count);
1993
-	}
1994
-	mutex_unlock(&dpu_enc->enc_lock);
1995
-	_dpu_encoder_power_enable(dpu_enc, false);
1996
-
1997
-	return count;
1998
-}
1999
-
2000
-static ssize_t _dpu_encoder_misr_read(struct file *file,
2001
-		char __user *user_buff, size_t count, loff_t *ppos)
2002
-{
2003
-	struct dpu_encoder_virt *dpu_enc;
2004
-	int i = 0, len = 0;
2005
-	char buf[MISR_BUFF_SIZE + 1] = {'\0'};
2006
-	int rc;
2007
-
2008
-	if (*ppos)
2009
-		return 0;
2010
-
2011
-	if (!file || !file->private_data)
2012
-		return -EINVAL;
2013
-
2014
-	dpu_enc = file->private_data;
2015
-
2016
-	rc = _dpu_encoder_power_enable(dpu_enc, true);
2017
-	if (rc)
2018
-		return rc;
2019
-
2020
-	mutex_lock(&dpu_enc->enc_lock);
2021
-	if (!dpu_enc->misr_enable) {
2022
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2023
-			"disabled\n");
2024
-		goto buff_check;
2025
-	} else if (dpu_enc->disp_info.capabilities &
2026
-						~MSM_DISPLAY_CAP_VID_MODE) {
2027
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2028
-			"unsupported\n");
2029
-		goto buff_check;
2030
-	}
2031
-
2032
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2033
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2034
-
2035
-		if (!phys || !phys->ops.collect_misr)
2036
-			continue;
2037
-
2038
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2039
-			"Intf idx:%d\n", phys->intf_idx - INTF_0);
2040
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
2041
-					phys->ops.collect_misr(phys));
2042
-	}
2043
-
2044
-buff_check:
2045
-	if (count <= len) {
2046
-		len = 0;
2047
-		goto end;
2048
-	}
2049
-
2050
-	if (copy_to_user(user_buff, buf, len)) {
2051
-		len = -EFAULT;
2052
-		goto end;
2053
-	}
2054
-
2055
-	*ppos += len;   /* increase offset */
2056
-
2057
-end:
2058
-	mutex_unlock(&dpu_enc->enc_lock);
2059
-	_dpu_encoder_power_enable(dpu_enc, false);
2060
-	return len;
2061
-}
1915
+DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
20621916 
20631917 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
20641918 {
2065
-	struct dpu_encoder_virt *dpu_enc;
2066
-	struct msm_drm_private *priv;
2067
-	struct dpu_kms *dpu_kms;
1919
+	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
20681920 	int i;
2069
-
2070
-	static const struct file_operations debugfs_status_fops = {
2071
-		.open =		_dpu_encoder_debugfs_status_open,
2072
-		.read =		seq_read,
2073
-		.llseek =	seq_lseek,
2074
-		.release =	single_release,
2075
-	};
2076
-
2077
-	static const struct file_operations debugfs_misr_fops = {
2078
-		.open = simple_open,
2079
-		.read = _dpu_encoder_misr_read,
2080
-		.write = _dpu_encoder_misr_setup,
2081
-	};
20821921 
20831922 	char name[DPU_NAME_SIZE];
20841923 
2085
-	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
1924
+	if (!drm_enc->dev) {
20861925 		DPU_ERROR("invalid encoder or kms\n");
20871926 		return -EINVAL;
20881927 	}
2089
-
2090
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
2091
-	priv = drm_enc->dev->dev_private;
2092
-	dpu_kms = to_dpu_kms(priv->kms);
20931928 
20941929 	snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
20951930 
20961931 	/* create overall sub-directory for the encoder */
20971932 	dpu_enc->debugfs_root = debugfs_create_dir(name,
20981933 			drm_enc->dev->primary->debugfs_root);
2099
-	if (!dpu_enc->debugfs_root)
2100
-		return -ENOMEM;
21011934 
21021935 	/* don't error check these */
21031936 	debugfs_create_file("status", 0600,
2104
-		dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
2105
-
2106
-	debugfs_create_file("misr_data", 0600,
2107
-		dpu_enc->debugfs_root, dpu_enc, &debugfs_misr_fops);
1937
+		dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
21081938 
21091939 	for (i = 0; i < dpu_enc->num_phys_encs; i++)
2110
-		if (dpu_enc->phys_encs[i] &&
2111
-				dpu_enc->phys_encs[i]->ops.late_register)
1940
+		if (dpu_enc->phys_encs[i]->ops.late_register)
21121941 			dpu_enc->phys_encs[i]->ops.late_register(
21131942 					dpu_enc->phys_encs[i],
21141943 					dpu_enc->debugfs_root);
21151944 
21161945 	return 0;
21171946 }
2118
-
2119
-static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
2120
-{
2121
-	struct dpu_encoder_virt *dpu_enc;
2122
-
2123
-	if (!drm_enc)
2124
-		return;
2125
-
2126
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
2127
-	debugfs_remove_recursive(dpu_enc->debugfs_root);
2128
-}
21291947 #else
21301948 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
21311949 {
21321950 	return 0;
2133
-}
2134
-
2135
-static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
2136
-{
21371951 }
21381952 #endif
21391953 
....@@ -2144,7 +1958,9 @@
21441958 
21451959 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
21461960 {
2147
-	_dpu_encoder_destroy_debugfs(encoder);
1961
+	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1962
+
1963
+	debugfs_remove_recursive(dpu_enc->debugfs_root);
21481964 }
21491965 
21501966 static int dpu_encoder_virt_add_phys_encs(
....@@ -2173,7 +1989,7 @@
21731989 		if (IS_ERR_OR_NULL(enc)) {
21741990 			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
21751991 				PTR_ERR(enc));
2176
-			return enc == 0 ? -EINVAL : PTR_ERR(enc);
1992
+			return enc == NULL ? -EINVAL : PTR_ERR(enc);
21771993 		}
21781994 
21791995 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
....@@ -2186,12 +2002,17 @@
21862002 		if (IS_ERR_OR_NULL(enc)) {
21872003 			DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
21882004 				PTR_ERR(enc));
2189
-			return enc == 0 ? -EINVAL : PTR_ERR(enc);
2005
+			return enc == NULL ? -EINVAL : PTR_ERR(enc);
21902006 		}
21912007 
21922008 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
21932009 		++dpu_enc->num_phys_encs;
21942010 	}
2011
+
2012
+	if (params->split_role == ENC_ROLE_SLAVE)
2013
+		dpu_enc->cur_slave = enc;
2014
+	else
2015
+		dpu_enc->cur_master = enc;
21952016 
21962017 	return 0;
21972018 }
....@@ -2204,19 +2025,19 @@
22042025 
22052026 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
22062027 				 struct dpu_kms *dpu_kms,
2207
-				 struct msm_display_info *disp_info,
2208
-				 int *drm_enc_mode)
2028
+				 struct msm_display_info *disp_info)
22092029 {
22102030 	int ret = 0;
22112031 	int i = 0;
2212
-	enum dpu_intf_type intf_type;
2032
+	enum dpu_intf_type intf_type = INTF_NONE;
22132033 	struct dpu_enc_phys_init_params phys_params;
22142034 
2215
-	if (!dpu_enc || !dpu_kms) {
2216
-		DPU_ERROR("invalid arg(s), enc %d kms %d\n",
2217
-				dpu_enc != 0, dpu_kms != 0);
2035
+	if (!dpu_enc) {
2036
+		DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
22182037 		return -EINVAL;
22192038 	}
2039
+
2040
+	dpu_enc->cur_master = NULL;
22202041 
22212042 	memset(&phys_params, 0, sizeof(phys_params));
22222043 	phys_params.dpu_kms = dpu_kms;
....@@ -2226,23 +2047,16 @@
22262047 
22272048 	DPU_DEBUG("\n");
22282049 
2229
-	if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
2230
-		*drm_enc_mode = DRM_MODE_ENCODER_DSI;
2050
+	switch (disp_info->intf_type) {
2051
+	case DRM_MODE_ENCODER_DSI:
22312052 		intf_type = INTF_DSI;
2232
-	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
2233
-		*drm_enc_mode = DRM_MODE_ENCODER_TMDS;
2234
-		intf_type = INTF_HDMI;
2235
-	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
2236
-		*drm_enc_mode = DRM_MODE_ENCODER_TMDS;
2053
+		break;
2054
+	case DRM_MODE_ENCODER_TMDS:
22372055 		intf_type = INTF_DP;
2238
-	} else {
2239
-		DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2240
-		return -EINVAL;
2056
+		break;
22412057 	}
22422058 
22432059 	WARN_ON(disp_info->num_of_h_tiles < 1);
2244
-
2245
-	dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
22462060 
22472061 	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
22482062 
....@@ -2292,11 +2106,8 @@
22922106 
22932107 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
22942108 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2295
-
2296
-		if (phys) {
2297
-			atomic_set(&phys->vsync_cnt, 0);
2298
-			atomic_set(&phys->underrun_cnt, 0);
2299
-		}
2109
+		atomic_set(&phys->vsync_cnt, 0);
2110
+		atomic_set(&phys->underrun_cnt, 0);
23002111 	}
23012112 	mutex_unlock(&dpu_enc->enc_lock);
23022113 
....@@ -2308,20 +2119,18 @@
23082119 	struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
23092120 			frame_done_timer);
23102121 	struct drm_encoder *drm_enc = &dpu_enc->base;
2311
-	struct msm_drm_private *priv;
23122122 	u32 event;
23132123 
2314
-	if (!drm_enc->dev || !drm_enc->dev->dev_private) {
2124
+	if (!drm_enc->dev) {
23152125 		DPU_ERROR("invalid parameters\n");
23162126 		return;
23172127 	}
2318
-	priv = drm_enc->dev->dev_private;
23192128 
23202129 	if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
23212130 		DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
23222131 			      DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
23232132 		return;
2324
-	} else if (!atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
2133
+	} else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
23252134 		DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
23262135 		return;
23272136 	}
....@@ -2356,32 +2165,25 @@
23562165 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
23572166 	struct drm_encoder *drm_enc = NULL;
23582167 	struct dpu_encoder_virt *dpu_enc = NULL;
2359
-	int drm_enc_mode = DRM_MODE_ENCODER_NONE;
23602168 	int ret = 0;
23612169 
23622170 	dpu_enc = to_dpu_encoder_virt(enc);
23632171 
2364
-	mutex_init(&dpu_enc->enc_lock);
2365
-	ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info,
2366
-			&drm_enc_mode);
2172
+	ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
23672173 	if (ret)
23682174 		goto fail;
23692175 
2370
-	dpu_enc->cur_master = NULL;
2371
-	spin_lock_init(&dpu_enc->enc_spinlock);
2372
-
2373
-	atomic_set(&dpu_enc->frame_done_timeout, 0);
2176
+	atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
23742177 	timer_setup(&dpu_enc->frame_done_timer,
23752178 			dpu_encoder_frame_done_timeout, 0);
23762179 
2377
-	if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
2180
+	if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
23782181 		timer_setup(&dpu_enc->vsync_event_timer,
23792182 				dpu_encoder_vsync_event_handler,
23802183 				0);
23812184 
23822185 
2383
-	mutex_init(&dpu_enc->rc_lock);
2384
-	kthread_init_delayed_work(&dpu_enc->delayed_off_work,
2186
+	INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
23852187 			dpu_encoder_off_work);
23862188 	dpu_enc->idle_timeout = IDLE_TIMEOUT;
23872189 
....@@ -2423,6 +2225,11 @@
24232225 
24242226 	drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
24252227 
2228
+	spin_lock_init(&dpu_enc->enc_spinlock);
2229
+	dpu_enc->enabled = false;
2230
+	mutex_init(&dpu_enc->enc_lock);
2231
+	mutex_init(&dpu_enc->rc_lock);
2232
+
24262233 	return &dpu_enc->base;
24272234 }
24282235 
....@@ -2442,8 +2249,6 @@
24422249 
24432250 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
24442251 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2445
-		if (!phys)
2446
-			continue;
24472252 
24482253 		switch (event) {
24492254 		case MSM_ENC_COMMIT_DONE:
....@@ -2459,7 +2264,7 @@
24592264 			DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
24602265 					event);
24612266 			return -EINVAL;
2462
-		};
2267
+		}
24632268 
24642269 		if (fn_wait) {
24652270 			DPU_ATRACE_BEGIN("wait_for_completion_event");
....@@ -2476,7 +2281,6 @@
24762281 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
24772282 {
24782283 	struct dpu_encoder_virt *dpu_enc = NULL;
2479
-	int i;
24802284 
24812285 	if (!encoder) {
24822286 		DPU_ERROR("invalid encoder\n");
....@@ -2487,12 +2291,8 @@
24872291 	if (dpu_enc->cur_master)
24882292 		return dpu_enc->cur_master->intf_mode;
24892293 
2490
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2491
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2492
-
2493
-		if (phys)
2494
-			return phys->intf_mode;
2495
-	}
2294
+	if (dpu_enc->num_phys_encs)
2295
+		return dpu_enc->phys_encs[0]->intf_mode;
24962296 
24972297 	return INTF_MODE_NONE;
24982298 }