forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -54,10 +56,13 @@
5456 	CACHE_FLUSH_TS = 4,
5557 	CONTEXT_DONE = 5,
5658 	CACHE_FLUSH = 6,
57
-	HLSQ_FLUSH = 7,
5859 	VIZQUERY_START = 7,
60
+	HLSQ_FLUSH = 7,
5961 	VIZQUERY_END = 8,
6062 	SC_WAIT_WC = 9,
63
+	WRITE_PRIMITIVE_COUNTS = 9,
64
+	START_PRIMITIVE_CTRS = 11,
65
+	STOP_PRIMITIVE_CTRS = 12,
6166 	RST_PIX_CNT = 13,
6267 	RST_VTX_CNT = 14,
6368 	TILE_FLUSH = 15,
....@@ -65,23 +70,31 @@
6570 	CACHE_FLUSH_AND_INV_TS_EVENT = 20,
6671 	ZPASS_DONE = 21,
6772 	CACHE_FLUSH_AND_INV_EVENT = 22,
73
+	RB_DONE_TS = 22,
6874 	PERFCOUNTER_START = 23,
6975 	PERFCOUNTER_STOP = 24,
7076 	VS_FETCH_DONE = 27,
7177 	FACENESS_FLUSH = 28,
78
+	WT_DONE_TS = 8,
7279 	FLUSH_SO_0 = 17,
7380 	FLUSH_SO_1 = 18,
7481 	FLUSH_SO_2 = 19,
7582 	FLUSH_SO_3 = 20,
7683 	PC_CCU_INVALIDATE_DEPTH = 24,
7784 	PC_CCU_INVALIDATE_COLOR = 25,
78
-	UNK_1C = 28,
79
-	UNK_1D = 29,
85
+	PC_CCU_RESOLVE_TS = 26,
86
+	PC_CCU_FLUSH_DEPTH_TS = 28,
87
+	PC_CCU_FLUSH_COLOR_TS = 29,
8088 	BLIT = 30,
8189 	UNK_25 = 37,
8290 	LRZ_FLUSH = 38,
91
+	BLIT_OP_FILL_2D = 39,
92
+	BLIT_OP_COPY_2D = 40,
93
+	BLIT_OP_SCALE_2D = 42,
94
+	CONTEXT_DONE_2D = 43,
8395 	UNK_2C = 44,
8496 	UNK_2D = 45,
97
+	CACHE_INVALIDATE = 49,
8598 };
8699 
87100 enum pc_di_primtype {
....@@ -99,13 +112,52 @@
99112 	DI_PT_LINESTRIP_ADJ = 11,
100113 	DI_PT_TRI_ADJ = 12,
101114 	DI_PT_TRISTRIP_ADJ = 13,
115
+	DI_PT_PATCHES0 = 31,
116
+	DI_PT_PATCHES1 = 32,
117
+	DI_PT_PATCHES2 = 33,
118
+	DI_PT_PATCHES3 = 34,
119
+	DI_PT_PATCHES4 = 35,
120
+	DI_PT_PATCHES5 = 36,
121
+	DI_PT_PATCHES6 = 37,
122
+	DI_PT_PATCHES7 = 38,
123
+	DI_PT_PATCHES8 = 39,
124
+	DI_PT_PATCHES9 = 40,
125
+	DI_PT_PATCHES10 = 41,
126
+	DI_PT_PATCHES11 = 42,
127
+	DI_PT_PATCHES12 = 43,
128
+	DI_PT_PATCHES13 = 44,
129
+	DI_PT_PATCHES14 = 45,
130
+	DI_PT_PATCHES15 = 46,
131
+	DI_PT_PATCHES16 = 47,
132
+	DI_PT_PATCHES17 = 48,
133
+	DI_PT_PATCHES18 = 49,
134
+	DI_PT_PATCHES19 = 50,
135
+	DI_PT_PATCHES20 = 51,
136
+	DI_PT_PATCHES21 = 52,
137
+	DI_PT_PATCHES22 = 53,
138
+	DI_PT_PATCHES23 = 54,
139
+	DI_PT_PATCHES24 = 55,
140
+	DI_PT_PATCHES25 = 56,
141
+	DI_PT_PATCHES26 = 57,
142
+	DI_PT_PATCHES27 = 58,
143
+	DI_PT_PATCHES28 = 59,
144
+	DI_PT_PATCHES29 = 60,
145
+	DI_PT_PATCHES30 = 61,
146
+	DI_PT_PATCHES31 = 62,
102147 };
103148 
104149 enum pc_di_src_sel {
105150 	DI_SRC_SEL_DMA = 0,
106151 	DI_SRC_SEL_IMMEDIATE = 1,
107152 	DI_SRC_SEL_AUTO_INDEX = 2,
108
-	DI_SRC_SEL_RESERVED = 3,
153
+	DI_SRC_SEL_AUTO_XFB = 3,
154
+};
155
+
156
+enum pc_di_face_cull_sel {
157
+	DI_FACE_CULL_NONE = 0,
158
+	DI_FACE_CULL_FETCH = 1,
159
+	DI_FACE_BACKFACE_CULL = 2,
160
+	DI_FACE_FRONTFACE_CULL = 3,
109161 };
110162 
111163 enum pc_di_index_size {
....@@ -136,6 +188,7 @@
136188 	CP_PREEMPT_ENABLE = 28,
137189 	CP_PREEMPT_TOKEN = 30,
138190 	CP_INDIRECT_BUFFER = 63,
191
+	CP_INDIRECT_BUFFER_CHAIN = 87,
139192 	CP_INDIRECT_BUFFER_PFD = 55,
140193 	CP_WAIT_FOR_IDLE = 38,
141194 	CP_WAIT_REG_MEM = 60,
....@@ -192,6 +245,7 @@
192245 	CP_DRAW_INDX_OFFSET = 56,
193246 	CP_DRAW_INDIRECT = 40,
194247 	CP_DRAW_INDX_INDIRECT = 41,
248
+	CP_DRAW_INDIRECT_MULTI = 42,
195249 	CP_DRAW_AUTO = 36,
196250 	CP_UNKNOWN_19 = 25,
197251 	CP_UNKNOWN_1A = 26,
....@@ -225,6 +279,7 @@
225279 	CP_SET_MODE = 99,
226280 	CP_LOAD_STATE6_GEOM = 50,
227281 	CP_LOAD_STATE6_FRAG = 52,
282
+	CP_LOAD_STATE6 = 54,
228283 	IN_IB_PREFETCH_END = 23,
229284 	IN_SUBBLK_PREFETCH = 31,
230285 	IN_INSTR_PREFETCH = 32,
....@@ -234,10 +289,16 @@
234289 	IN_INCR_UPDT_CONST = 86,
235290 	IN_INCR_UPDT_INSTR = 87,
236291 	PKT4 = 4,
237
-	CP_UNK_A6XX_14 = 20,
238
-	CP_UNK_A6XX_36 = 54,
239
-	CP_UNK_A6XX_55 = 85,
240
-	UNK_A6XX_6D = 109,
292
+	CP_SCRATCH_WRITE = 76,
293
+	CP_REG_TO_MEM_OFFSET_MEM = 116,
294
+	CP_REG_TO_MEM_OFFSET_REG = 114,
295
+	CP_WAIT_MEM_GTE = 20,
296
+	CP_WAIT_TWO_REGS = 112,
297
+	CP_MEMCPY = 117,
298
+	CP_SET_BIN_DATA5_OFFSET = 46,
299
+	CP_SET_CTXSWITCH_IB = 85,
300
+	CP_REG_WRITE = 109,
301
+	CP_WHERE_AM_I = 98,
241302 };
242303 
243304 enum adreno_state_block {
....@@ -285,6 +346,7 @@
285346 enum a4xx_state_type {
286347 	ST4_SHADER = 0,
287348 	ST4_CONSTANTS = 1,
349
+	ST4_UBO = 2,
288350 };
289351 
290352 enum a4xx_state_src {
....@@ -305,24 +367,39 @@
305367 	SB6_GS_SHADER = 11,
306368 	SB6_FS_SHADER = 12,
307369 	SB6_CS_SHADER = 13,
308
-	SB6_SSBO = 14,
309
-	SB6_CS_SSBO = 15,
370
+	SB6_IBO = 14,
371
+	SB6_CS_IBO = 15,
310372 };
311373 
312374 enum a6xx_state_type {
313375 	ST6_SHADER = 0,
314376 	ST6_CONSTANTS = 1,
377
+	ST6_UBO = 2,
378
+	ST6_IBO = 3,
315379 };
316380 
317381 enum a6xx_state_src {
318382 	SS6_DIRECT = 0,
383
+	SS6_BINDLESS = 1,
319384 	SS6_INDIRECT = 2,
385
+	SS6_UBO = 3,
320386 };
321387 
322388 enum a4xx_index_size {
323389 	INDEX4_SIZE_8_BIT = 0,
324390 	INDEX4_SIZE_16_BIT = 1,
325391 	INDEX4_SIZE_32_BIT = 2,
392
+};
393
+
394
+enum a6xx_patch_type {
395
+	TESS_QUADS = 0,
396
+	TESS_TRIANGLES = 1,
397
+	TESS_ISOLINES = 2,
398
+};
399
+
400
+enum a6xx_draw_indirect_opcode {
401
+	INDIRECT_OP_NORMAL = 2,
402
+	INDIRECT_OP_INDEXED = 4,
326403 };
327404 
328405 enum cp_cond_function {
....@@ -354,8 +431,15 @@
354431 	RM6_BYPASS = 1,
355432 	RM6_BINNING = 2,
356433 	RM6_GMEM = 4,
357
-	RM6_BLIT2D = 5,
434
+	RM6_ENDVIS = 5,
358435 	RM6_RESOLVE = 6,
436
+	RM6_YIELD = 7,
437
+	RM6_COMPUTE = 8,
438
+	RM6_BLIT2DSCALE = 12,
439
+	RM6_IB1LIST_START = 13,
440
+	RM6_IB1LIST_END = 14,
441
+	RM6_IFPC_ENABLE = 256,
442
+	RM6_IFPC_DISABLE = 257,
359443 };
360444 
361445 enum pseudo_reg {
....@@ -364,6 +448,25 @@
364448 	SECURE_SAVE_ADDR = 2,
365449 	NON_PRIV_SAVE_ADDR = 3,
366450 	COUNTER = 4,
451
+};
452
+
453
+enum compare_mode {
454
+	PRED_TEST = 1,
455
+	REG_COMPARE = 2,
456
+	RENDER_MODE = 3,
457
+};
458
+
459
+enum ctxswitch_ib {
460
+	RESTORE_IB = 0,
461
+	YIELD_RESTORE_IB = 1,
462
+	SAVE_IB = 2,
463
+	RB_SAVE_IB = 3,
464
+};
465
+
466
+enum reg_tracker {
467
+	TRACK_CNTL_REG = 1,
468
+	TRACK_RENDER_CNTL = 2,
469
+	UNK_EVENT_WRITE = 4,
367470 };
368471 
369472 #define REG_CP_LOAD_STATE_0					0x00000000
....@@ -461,7 +564,7 @@
461564 {
462565 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
463566 }
464
-#define CP_LOAD_STATE6_0_STATE_TYPE__MASK			0x00004000
567
+#define CP_LOAD_STATE6_0_STATE_TYPE__MASK			0x0000c000
465568 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT			14
466569 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
467570 {
....@@ -501,6 +604,8 @@
501604 {
502605 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
503606 }
607
+
608
+#define REG_CP_LOAD_STATE6_EXT_SRC_ADDR				0x00000001
504609 
505610 #define REG_CP_DRAW_INDX_0					0x00000000
506611 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff
....@@ -645,12 +750,14 @@
645750 {
646751 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
647752 }
648
-#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK			0x01f00000
649
-#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT			20
650
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
753
+#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK			0x00003000
754
+#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT			12
755
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
651756 {
652
-	return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
757
+	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
653758 }
759
+#define CP_DRAW_INDX_OFFSET_0_GS_ENABLE				0x00010000
760
+#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE			0x00020000
654761 
655762 #define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
656763 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK		0xffffffff
....@@ -669,6 +776,39 @@
669776 }
670777 
671778 #define REG_CP_DRAW_INDX_OFFSET_3				0x00000003
779
+#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK			0xffffffff
780
+#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT			0
781
+static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
782
+{
783
+	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
784
+}
785
+
786
+
787
+#define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
788
+#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK		0xffffffff
789
+#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT		0
790
+static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
791
+{
792
+	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
793
+}
794
+
795
+#define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
796
+#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK		0xffffffff
797
+#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT		0
798
+static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
799
+{
800
+	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
801
+}
802
+
803
+#define REG_CP_DRAW_INDX_OFFSET_INDX_BASE			0x00000004
804
+
805
+#define REG_CP_DRAW_INDX_OFFSET_6				0x00000006
806
+#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK			0xffffffff
807
+#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT		0
808
+static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
809
+{
810
+	return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
811
+}
672812 
673813 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
674814 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK			0xffffffff
....@@ -711,12 +851,15 @@
711851 {
712852 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
713853 }
714
-#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK			0x01f00000
715
-#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT		20
716
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
854
+#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
855
+#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT		12
856
+static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
717857 {
718
-	return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
858
+	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
719859 }
860
+#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE			0x00010000
861
+#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE			0x00020000
862
+
720863 
721864 #define REG_A4XX_CP_DRAW_INDIRECT_1				0x00000001
722865 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK			0xffffffff
....@@ -727,6 +870,14 @@
727870 }
728871 
729872 
873
+#define REG_A5XX_CP_DRAW_INDIRECT_1				0x00000001
874
+#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK		0xffffffff
875
+#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT		0
876
+static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
877
+{
878
+	return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
879
+}
880
+
730881 #define REG_A5XX_CP_DRAW_INDIRECT_2				0x00000002
731882 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK		0xffffffff
732883 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT		0
....@@ -734,6 +885,8 @@
734885 {
735886 	return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
736887 }
888
+
889
+#define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT			0x00000001
737890 
738891 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0			0x00000000
739892 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK		0x0000003f
....@@ -760,12 +913,14 @@
760913 {
761914 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
762915 }
763
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK		0x01f00000
764
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT		20
765
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
916
+#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
917
+#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT		12
918
+static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
766919 {
767
-	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
920
+	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
768921 }
922
+#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE			0x00010000
923
+#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE		0x00020000
769924 
770925 
771926 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
....@@ -809,6 +964,8 @@
809964 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
810965 }
811966 
967
+#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE		0x00000001
968
+
812969 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
813970 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK		0xffffffff
814971 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT		0
....@@ -833,6 +990,84 @@
833990 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
834991 }
835992 
993
+#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT			0x00000004
994
+
995
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0			0x00000000
996
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK		0x0000003f
997
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT		0
998
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
999
+{
1000
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1001
+}
1002
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK	0x000000c0
1003
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT	6
1004
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1005
+{
1006
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1007
+}
1008
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK		0x00000300
1009
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT		8
1010
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1011
+{
1012
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1013
+}
1014
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK		0x00000c00
1015
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT		10
1016
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1017
+{
1018
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1019
+}
1020
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK		0x00003000
1021
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT		12
1022
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1023
+{
1024
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1025
+}
1026
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE			0x00010000
1027
+#define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE		0x00020000
1028
+
1029
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1			0x00000001
1030
+#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK		0x0000000f
1031
+#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT		0
1032
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1033
+{
1034
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1035
+}
1036
+#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK		0x003fff00
1037
+#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT		8
1038
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1039
+{
1040
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1041
+}
1042
+
1043
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2			0x00000002
1044
+#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK		0xffffffff
1045
+#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT		0
1046
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
1047
+{
1048
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
1049
+}
1050
+
1051
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0		0x00000003
1052
+
1053
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5			0x00000005
1054
+#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK		0xffffffff
1055
+#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT		0
1056
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
1057
+{
1058
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
1059
+}
1060
+
1061
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT		0x00000006
1062
+
1063
+#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8			0x00000008
1064
+#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK		0xffffffff
1065
+#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT		0
1066
+static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
1067
+{
1068
+	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
1069
+}
1070
+
8361071 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
8371072 
8381073 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
....@@ -846,12 +1081,9 @@
8461081 #define CP_SET_DRAW_STATE__0_DISABLE				0x00020000
8471082 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS			0x00040000
8481083 #define CP_SET_DRAW_STATE__0_LOAD_IMMED				0x00080000
849
-#define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK			0x00f00000
850
-#define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT			20
851
-static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
852
-{
853
-	return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
854
-}
1084
+#define CP_SET_DRAW_STATE__0_BINNING				0x00100000
1085
+#define CP_SET_DRAW_STATE__0_GMEM				0x00200000
1086
+#define CP_SET_DRAW_STATE__0_SYSMEM				0x00400000
8551087 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK			0x1f000000
8561088 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT			24
8571089 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
....@@ -968,30 +1200,101 @@
9681200 }
9691201 
9701202 #define REG_CP_SET_BIN_DATA5_5					0x00000005
971
-#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK			0xffffffff
972
-#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT		0
973
-static inline uint32_t CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO(uint32_t val)
1203
+#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK		0xffffffff
1204
+#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT		0
1205
+static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
9741206 {
975
-	return ((val) << CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK;
1207
+	return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
9761208 }
9771209 
9781210 #define REG_CP_SET_BIN_DATA5_6					0x00000006
979
-#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK			0xffffffff
980
-#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT		0
981
-static inline uint32_t CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI(uint32_t val)
1211
+#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK		0xffffffff
1212
+#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT		0
1213
+static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
9821214 {
983
-	return ((val) << CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK;
1215
+	return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1216
+}
1217
+
1218
+#define REG_CP_SET_BIN_DATA5_OFFSET_0				0x00000000
1219
+#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK		0x003f0000
1220
+#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT		16
1221
+static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1222
+{
1223
+	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1224
+}
1225
+#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK			0x07c00000
1226
+#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT			22
1227
+static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1228
+{
1229
+	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1230
+}
1231
+
1232
+#define REG_CP_SET_BIN_DATA5_OFFSET_1				0x00000001
1233
+#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK		0xffffffff
1234
+#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT	0
1235
+static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1236
+{
1237
+	return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1238
+}
1239
+
1240
+#define REG_CP_SET_BIN_DATA5_OFFSET_2				0x00000002
1241
+#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK		0xffffffff
1242
+#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT	0
1243
+static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1244
+{
1245
+	return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1246
+}
1247
+
1248
+#define REG_CP_SET_BIN_DATA5_OFFSET_3				0x00000003
1249
+#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK	0xffffffff
1250
+#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT	0
1251
+static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1252
+{
1253
+	return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1254
+}
1255
+
1256
+#define REG_CP_REG_RMW_0					0x00000000
1257
+#define CP_REG_RMW_0_DST_REG__MASK				0x0003ffff
1258
+#define CP_REG_RMW_0_DST_REG__SHIFT				0
1259
+static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1260
+{
1261
+	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1262
+}
1263
+#define CP_REG_RMW_0_ROTATE__MASK				0x1f000000
1264
+#define CP_REG_RMW_0_ROTATE__SHIFT				24
1265
+static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1266
+{
1267
+	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1268
+}
1269
+#define CP_REG_RMW_0_SRC1_ADD					0x20000000
1270
+#define CP_REG_RMW_0_SRC1_IS_REG				0x40000000
1271
+#define CP_REG_RMW_0_SRC0_IS_REG				0x80000000
1272
+
1273
+#define REG_CP_REG_RMW_1					0x00000001
1274
+#define CP_REG_RMW_1_SRC0__MASK					0xffffffff
1275
+#define CP_REG_RMW_1_SRC0__SHIFT				0
1276
+static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1277
+{
1278
+	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1279
+}
1280
+
1281
+#define REG_CP_REG_RMW_2					0x00000002
1282
+#define CP_REG_RMW_2_SRC1__MASK					0xffffffff
1283
+#define CP_REG_RMW_2_SRC1__SHIFT				0
1284
+static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1285
+{
1286
+	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
9841287 }
9851288 
9861289 #define REG_CP_REG_TO_MEM_0					0x00000000
987
-#define CP_REG_TO_MEM_0_REG__MASK				0x0000ffff
1290
+#define CP_REG_TO_MEM_0_REG__MASK				0x0003ffff
9881291 #define CP_REG_TO_MEM_0_REG__SHIFT				0
9891292 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
9901293 {
9911294 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
9921295 }
993
-#define CP_REG_TO_MEM_0_CNT__MASK				0x3ff80000
994
-#define CP_REG_TO_MEM_0_CNT__SHIFT				19
1296
+#define CP_REG_TO_MEM_0_CNT__MASK				0x3ffc0000
1297
+#define CP_REG_TO_MEM_0_CNT__SHIFT				18
9951298 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
9961299 {
9971300 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
....@@ -1015,8 +1318,97 @@
10151318 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
10161319 }
10171320 
1321
+#define REG_CP_REG_TO_MEM_OFFSET_REG_0				0x00000000
1322
+#define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK			0x0003ffff
1323
+#define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT			0
1324
+static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1325
+{
1326
+	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1327
+}
1328
+#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK			0x3ffc0000
1329
+#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT			18
1330
+static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1331
+{
1332
+	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1333
+}
1334
+#define CP_REG_TO_MEM_OFFSET_REG_0_64B				0x40000000
1335
+#define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE			0x80000000
1336
+
1337
+#define REG_CP_REG_TO_MEM_OFFSET_REG_1				0x00000001
1338
+#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK			0xffffffff
1339
+#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT			0
1340
+static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1341
+{
1342
+	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1343
+}
1344
+
1345
+#define REG_CP_REG_TO_MEM_OFFSET_REG_2				0x00000002
1346
+#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK		0xffffffff
1347
+#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT		0
1348
+static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1349
+{
1350
+	return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1351
+}
1352
+
1353
+#define REG_CP_REG_TO_MEM_OFFSET_REG_3				0x00000003
1354
+#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK		0x0003ffff
1355
+#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT		0
1356
+static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1357
+{
1358
+	return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1359
+}
1360
+#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH		0x00080000
1361
+
1362
+#define REG_CP_REG_TO_MEM_OFFSET_MEM_0				0x00000000
1363
+#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK			0x0003ffff
1364
+#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT			0
1365
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1366
+{
1367
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1368
+}
1369
+#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK			0x3ffc0000
1370
+#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT			18
1371
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1372
+{
1373
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1374
+}
1375
+#define CP_REG_TO_MEM_OFFSET_MEM_0_64B				0x40000000
1376
+#define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE			0x80000000
1377
+
1378
+#define REG_CP_REG_TO_MEM_OFFSET_MEM_1				0x00000001
1379
+#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK			0xffffffff
1380
+#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT			0
1381
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1382
+{
1383
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1384
+}
1385
+
1386
+#define REG_CP_REG_TO_MEM_OFFSET_MEM_2				0x00000002
1387
+#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK		0xffffffff
1388
+#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT		0
1389
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1390
+{
1391
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1392
+}
1393
+
1394
+#define REG_CP_REG_TO_MEM_OFFSET_MEM_3				0x00000003
1395
+#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK		0xffffffff
1396
+#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT		0
1397
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1398
+{
1399
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1400
+}
1401
+
1402
+#define REG_CP_REG_TO_MEM_OFFSET_MEM_4				0x00000004
1403
+#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK		0xffffffff
1404
+#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT		0
1405
+static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1406
+{
1407
+	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1408
+}
1409
+
10181410 #define REG_CP_MEM_TO_REG_0					0x00000000
1019
-#define CP_MEM_TO_REG_0_REG__MASK				0x0000ffff
1411
+#define CP_MEM_TO_REG_0_REG__MASK				0x0003ffff
10201412 #define CP_MEM_TO_REG_0_REG__SHIFT				0
10211413 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
10221414 {
....@@ -1028,8 +1420,8 @@
10281420 {
10291421 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
10301422 }
1031
-#define CP_MEM_TO_REG_0_64B					0x40000000
1032
-#define CP_MEM_TO_REG_0_ACCUMULATE				0x80000000
1423
+#define CP_MEM_TO_REG_0_SHIFT_BY_2				0x40000000
1424
+#define CP_MEM_TO_REG_0_UNK31					0x80000000
10331425 
10341426 #define REG_CP_MEM_TO_REG_1					0x00000001
10351427 #define CP_MEM_TO_REG_1_SRC__MASK				0xffffffff
....@@ -1052,6 +1444,113 @@
10521444 #define CP_MEM_TO_MEM_0_NEG_B					0x00000002
10531445 #define CP_MEM_TO_MEM_0_NEG_C					0x00000004
10541446 #define CP_MEM_TO_MEM_0_DOUBLE					0x20000000
1447
+#define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES			0x40000000
1448
+#define CP_MEM_TO_MEM_0_UNK31					0x80000000
1449
+
1450
+#define REG_CP_MEMCPY_0						0x00000000
1451
+#define CP_MEMCPY_0_DWORDS__MASK				0xffffffff
1452
+#define CP_MEMCPY_0_DWORDS__SHIFT				0
1453
+static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1454
+{
1455
+	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1456
+}
1457
+
1458
+#define REG_CP_MEMCPY_1						0x00000001
1459
+#define CP_MEMCPY_1_SRC_LO__MASK				0xffffffff
1460
+#define CP_MEMCPY_1_SRC_LO__SHIFT				0
1461
+static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1462
+{
1463
+	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1464
+}
1465
+
1466
+#define REG_CP_MEMCPY_2						0x00000002
1467
+#define CP_MEMCPY_2_SRC_HI__MASK				0xffffffff
1468
+#define CP_MEMCPY_2_SRC_HI__SHIFT				0
1469
+static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1470
+{
1471
+	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1472
+}
1473
+
1474
+#define REG_CP_MEMCPY_3						0x00000003
1475
+#define CP_MEMCPY_3_DST_LO__MASK				0xffffffff
1476
+#define CP_MEMCPY_3_DST_LO__SHIFT				0
1477
+static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1478
+{
1479
+	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1480
+}
1481
+
1482
+#define REG_CP_MEMCPY_4						0x00000004
1483
+#define CP_MEMCPY_4_DST_HI__MASK				0xffffffff
1484
+#define CP_MEMCPY_4_DST_HI__SHIFT				0
1485
+static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1486
+{
1487
+	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1488
+}
1489
+
1490
+#define REG_CP_REG_TO_SCRATCH_0					0x00000000
1491
+#define CP_REG_TO_SCRATCH_0_REG__MASK				0x0003ffff
1492
+#define CP_REG_TO_SCRATCH_0_REG__SHIFT				0
1493
+static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1494
+{
1495
+	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1496
+}
1497
+#define CP_REG_TO_SCRATCH_0_SCRATCH__MASK			0x00700000
1498
+#define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT			20
1499
+static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1500
+{
1501
+	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1502
+}
1503
+#define CP_REG_TO_SCRATCH_0_CNT__MASK				0x07000000
1504
+#define CP_REG_TO_SCRATCH_0_CNT__SHIFT				24
1505
+static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1506
+{
1507
+	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1508
+}
1509
+
1510
+#define REG_CP_SCRATCH_TO_REG_0					0x00000000
1511
+#define CP_SCRATCH_TO_REG_0_REG__MASK				0x0003ffff
1512
+#define CP_SCRATCH_TO_REG_0_REG__SHIFT				0
1513
+static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1514
+{
1515
+	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1516
+}
1517
+#define CP_SCRATCH_TO_REG_0_UNK18				0x00040000
1518
+#define CP_SCRATCH_TO_REG_0_SCRATCH__MASK			0x00700000
1519
+#define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT			20
1520
+static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1521
+{
1522
+	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1523
+}
1524
+#define CP_SCRATCH_TO_REG_0_CNT__MASK				0x07000000
1525
+#define CP_SCRATCH_TO_REG_0_CNT__SHIFT				24
1526
+static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1527
+{
1528
+	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1529
+}
1530
+
1531
+#define REG_CP_SCRATCH_WRITE_0					0x00000000
1532
+#define CP_SCRATCH_WRITE_0_SCRATCH__MASK			0x00700000
1533
+#define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT			20
1534
+static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1535
+{
1536
+	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1537
+}
1538
+
1539
+#define REG_CP_MEM_WRITE_0					0x00000000
1540
+#define CP_MEM_WRITE_0_ADDR_LO__MASK				0xffffffff
1541
+#define CP_MEM_WRITE_0_ADDR_LO__SHIFT				0
1542
+static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1543
+{
1544
+	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1545
+}
1546
+
1547
+#define REG_CP_MEM_WRITE_1					0x00000001
1548
+#define CP_MEM_WRITE_1_ADDR_HI__MASK				0xffffffff
1549
+#define CP_MEM_WRITE_1_ADDR_HI__SHIFT				0
1550
+static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1551
+{
1552
+	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1553
+}
10551554 
10561555 #define REG_CP_COND_WRITE_0					0x00000000
10571556 #define CP_COND_WRITE_0_FUNCTION__MASK				0x00000007
....@@ -1110,7 +1609,9 @@
11101609 {
11111610 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
11121611 }
1612
+#define CP_COND_WRITE5_0_SIGNED_COMPARE				0x00000008
11131613 #define CP_COND_WRITE5_0_POLL_MEMORY				0x00000010
1614
+#define CP_COND_WRITE5_0_POLL_SCRATCH				0x00000020
11141615 #define CP_COND_WRITE5_0_WRITE_MEMORY				0x00000100
11151616 
11161617 #define REG_CP_COND_WRITE5_1					0x00000001
....@@ -1167,6 +1668,114 @@
11671668 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
11681669 {
11691670 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1671
+}
1672
+
1673
+#define REG_CP_WAIT_MEM_GTE_0					0x00000000
1674
+#define CP_WAIT_MEM_GTE_0_RESERVED__MASK			0xffffffff
1675
+#define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT			0
1676
+static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1677
+{
1678
+	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1679
+}
1680
+
1681
+#define REG_CP_WAIT_MEM_GTE_1					0x00000001
1682
+#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK			0xffffffff
1683
+#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT			0
1684
+static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1685
+{
1686
+	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1687
+}
1688
+
1689
+#define REG_CP_WAIT_MEM_GTE_2					0x00000002
1690
+#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK			0xffffffff
1691
+#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT			0
1692
+static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1693
+{
1694
+	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1695
+}
1696
+
1697
+#define REG_CP_WAIT_MEM_GTE_3					0x00000003
1698
+#define CP_WAIT_MEM_GTE_3_REF__MASK				0xffffffff
1699
+#define CP_WAIT_MEM_GTE_3_REF__SHIFT				0
1700
+static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1701
+{
1702
+	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1703
+}
1704
+
1705
+#define REG_CP_WAIT_REG_MEM_0					0x00000000
1706
+#define CP_WAIT_REG_MEM_0_FUNCTION__MASK			0x00000007
1707
+#define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT			0
1708
+static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1709
+{
1710
+	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1711
+}
1712
+#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE			0x00000008
1713
+#define CP_WAIT_REG_MEM_0_POLL_MEMORY				0x00000010
1714
+#define CP_WAIT_REG_MEM_0_POLL_SCRATCH				0x00000020
1715
+#define CP_WAIT_REG_MEM_0_WRITE_MEMORY				0x00000100
1716
+
1717
+#define REG_CP_WAIT_REG_MEM_1					0x00000001
1718
+#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK			0xffffffff
1719
+#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT			0
1720
+static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1721
+{
1722
+	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1723
+}
1724
+
1725
+#define REG_CP_WAIT_REG_MEM_2					0x00000002
1726
+#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK			0xffffffff
1727
+#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT			0
1728
+static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1729
+{
1730
+	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1731
+}
1732
+
1733
+#define REG_CP_WAIT_REG_MEM_3					0x00000003
1734
+#define CP_WAIT_REG_MEM_3_REF__MASK				0xffffffff
1735
+#define CP_WAIT_REG_MEM_3_REF__SHIFT				0
1736
+static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1737
+{
1738
+	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1739
+}
1740
+
1741
+#define REG_CP_WAIT_REG_MEM_4					0x00000004
1742
+#define CP_WAIT_REG_MEM_4_MASK__MASK				0xffffffff
1743
+#define CP_WAIT_REG_MEM_4_MASK__SHIFT				0
1744
+static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1745
+{
1746
+	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1747
+}
1748
+
1749
+#define REG_CP_WAIT_REG_MEM_5					0x00000005
1750
+#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK		0xffffffff
1751
+#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT		0
1752
+static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1753
+{
1754
+	return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1755
+}
1756
+
1757
+#define REG_CP_WAIT_TWO_REGS_0					0x00000000
1758
+#define CP_WAIT_TWO_REGS_0_REG0__MASK				0x0003ffff
1759
+#define CP_WAIT_TWO_REGS_0_REG0__SHIFT				0
1760
+static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1761
+{
1762
+	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1763
+}
1764
+
1765
+#define REG_CP_WAIT_TWO_REGS_1					0x00000001
1766
+#define CP_WAIT_TWO_REGS_1_REG1__MASK				0x0003ffff
1767
+#define CP_WAIT_TWO_REGS_1_REG1__SHIFT				0
1768
+static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1769
+{
1770
+	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1771
+}
1772
+
1773
+#define REG_CP_WAIT_TWO_REGS_2					0x00000002
1774
+#define CP_WAIT_TWO_REGS_2_REF__MASK				0xffffffff
1775
+#define CP_WAIT_TWO_REGS_2_REF__SHIFT				0
1776
+static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1777
+{
1778
+	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
11701779 }
11711780 
11721781 #define REG_CP_DISPATCH_COMPUTE_0				0x00000000
....@@ -1321,6 +1930,7 @@
13211930 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
13221931 }
13231932 #define CP_EVENT_WRITE_0_TIMESTAMP				0x40000000
1933
+#define CP_EVENT_WRITE_0_IRQ					0x80000000
13241934 
13251935 #define REG_CP_EVENT_WRITE_1					0x00000001
13261936 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK			0xffffffff
....@@ -1498,61 +2108,209 @@
14982108 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
14992109 }
15002110 
1501
-#define REG_A2XX_CP_SET_MARKER_0				0x00000000
1502
-#define A2XX_CP_SET_MARKER_0_MARKER__MASK			0x0000000f
1503
-#define A2XX_CP_SET_MARKER_0_MARKER__SHIFT			0
1504
-static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
2111
+#define REG_A6XX_CP_SET_MARKER_0				0x00000000
2112
+#define A6XX_CP_SET_MARKER_0_MODE__MASK				0x000001ff
2113
+#define A6XX_CP_SET_MARKER_0_MODE__SHIFT			0
2114
+static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
15052115 {
1506
-	return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
2116
+	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
15072117 }
1508
-#define A2XX_CP_SET_MARKER_0_MODE__MASK				0x0000000f
1509
-#define A2XX_CP_SET_MARKER_0_MODE__SHIFT			0
1510
-static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
2118
+#define A6XX_CP_SET_MARKER_0_MARKER__MASK			0x0000000f
2119
+#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT			0
2120
+static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)
15112121 {
1512
-	return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
1513
-}
1514
-#define A2XX_CP_SET_MARKER_0_IFPC				0x00000100
1515
-
1516
-static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1517
-
1518
-static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1519
-#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK		0x00000007
1520
-#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT		0
1521
-static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
1522
-{
1523
-	return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2122
+	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
15242123 }
15252124 
1526
-static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1527
-#define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK			0xffffffff
1528
-#define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT			0
1529
-static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2125
+static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2126
+
2127
+static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2128
+#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK		0x00000007
2129
+#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT		0
2130
+static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
15302131 {
1531
-	return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2132
+	return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
15322133 }
15332134 
1534
-static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1535
-#define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK			0xffffffff
1536
-#define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT			0
1537
-static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2135
+static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2136
+#define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK			0xffffffff
2137
+#define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT			0
2138
+static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
15382139 {
1539
-	return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2140
+	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
15402141 }
15412142 
1542
-#define REG_A2XX_CP_REG_TEST_0					0x00000000
1543
-#define A2XX_CP_REG_TEST_0_REG__MASK				0x00000fff
1544
-#define A2XX_CP_REG_TEST_0_REG__SHIFT				0
1545
-static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
2143
+static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2144
+#define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK			0xffffffff
2145
+#define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT			0
2146
+static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
15462147 {
1547
-	return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
2148
+	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
15482149 }
1549
-#define A2XX_CP_REG_TEST_0_BIT__MASK				0x01f00000
1550
-#define A2XX_CP_REG_TEST_0_BIT__SHIFT				20
1551
-static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
2150
+
2151
+#define REG_A6XX_CP_REG_TEST_0					0x00000000
2152
+#define A6XX_CP_REG_TEST_0_REG__MASK				0x0003ffff
2153
+#define A6XX_CP_REG_TEST_0_REG__SHIFT				0
2154
+static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
15522155 {
1553
-	return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
2156
+	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
15542157 }
1555
-#define A2XX_CP_REG_TEST_0_UNK25				0x02000000
2158
+#define A6XX_CP_REG_TEST_0_BIT__MASK				0x01f00000
2159
+#define A6XX_CP_REG_TEST_0_BIT__SHIFT				20
2160
+static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2161
+{
2162
+	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2163
+}
2164
+#define A6XX_CP_REG_TEST_0_WAIT_FOR_ME				0x02000000
2165
+
2166
+#define REG_CP_COND_REG_EXEC_0					0x00000000
2167
+#define CP_COND_REG_EXEC_0_REG0__MASK				0x0003ffff
2168
+#define CP_COND_REG_EXEC_0_REG0__SHIFT				0
2169
+static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2170
+{
2171
+	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2172
+}
2173
+#define CP_COND_REG_EXEC_0_BINNING				0x02000000
2174
+#define CP_COND_REG_EXEC_0_GMEM					0x04000000
2175
+#define CP_COND_REG_EXEC_0_SYSMEM				0x08000000
2176
+#define CP_COND_REG_EXEC_0_MODE__MASK				0xf0000000
2177
+#define CP_COND_REG_EXEC_0_MODE__SHIFT				28
2178
+static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2179
+{
2180
+	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2181
+}
2182
+
2183
+#define REG_CP_COND_REG_EXEC_1					0x00000001
2184
+#define CP_COND_REG_EXEC_1_DWORDS__MASK				0xffffffff
2185
+#define CP_COND_REG_EXEC_1_DWORDS__SHIFT			0
2186
+static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2187
+{
2188
+	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
2189
+}
2190
+
2191
+#define REG_CP_COND_EXEC_0					0x00000000
2192
+#define CP_COND_EXEC_0_ADDR0_LO__MASK				0xffffffff
2193
+#define CP_COND_EXEC_0_ADDR0_LO__SHIFT				0
2194
+static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2195
+{
2196
+	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2197
+}
2198
+
2199
+#define REG_CP_COND_EXEC_1					0x00000001
2200
+#define CP_COND_EXEC_1_ADDR0_HI__MASK				0xffffffff
2201
+#define CP_COND_EXEC_1_ADDR0_HI__SHIFT				0
2202
+static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2203
+{
2204
+	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2205
+}
2206
+
2207
+#define REG_CP_COND_EXEC_2					0x00000002
2208
+#define CP_COND_EXEC_2_ADDR1_LO__MASK				0xffffffff
2209
+#define CP_COND_EXEC_2_ADDR1_LO__SHIFT				0
2210
+static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2211
+{
2212
+	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2213
+}
2214
+
2215
+#define REG_CP_COND_EXEC_3					0x00000003
2216
+#define CP_COND_EXEC_3_ADDR1_HI__MASK				0xffffffff
2217
+#define CP_COND_EXEC_3_ADDR1_HI__SHIFT				0
2218
+static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2219
+{
2220
+	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2221
+}
2222
+
2223
+#define REG_CP_COND_EXEC_4					0x00000004
2224
+#define CP_COND_EXEC_4_REF__MASK				0xffffffff
2225
+#define CP_COND_EXEC_4_REF__SHIFT				0
2226
+static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2227
+{
2228
+	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2229
+}
2230
+
2231
+#define REG_CP_COND_EXEC_5					0x00000005
2232
+#define CP_COND_EXEC_5_DWORDS__MASK				0xffffffff
2233
+#define CP_COND_EXEC_5_DWORDS__SHIFT				0
2234
+static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2235
+{
2236
+	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2237
+}
2238
+
2239
+#define REG_CP_SET_CTXSWITCH_IB_0				0x00000000
2240
+#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK			0xffffffff
2241
+#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT			0
2242
+static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2243
+{
2244
+	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2245
+}
2246
+
2247
+#define REG_CP_SET_CTXSWITCH_IB_1				0x00000001
2248
+#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK			0xffffffff
2249
+#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT			0
2250
+static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2251
+{
2252
+	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2253
+}
2254
+
2255
+#define REG_CP_SET_CTXSWITCH_IB_2				0x00000002
2256
+#define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK			0x000fffff
2257
+#define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT			0
2258
+static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2259
+{
2260
+	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2261
+}
2262
+#define CP_SET_CTXSWITCH_IB_2_TYPE__MASK			0x00300000
2263
+#define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT			20
2264
+static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2265
+{
2266
+	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2267
+}
2268
+
2269
+#define REG_CP_REG_WRITE_0					0x00000000
2270
+#define CP_REG_WRITE_0_TRACKER__MASK				0x00000007
2271
+#define CP_REG_WRITE_0_TRACKER__SHIFT				0
2272
+static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2273
+{
2274
+	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2275
+}
2276
+
2277
+#define REG_CP_SMMU_TABLE_UPDATE_0				0x00000000
2278
+#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK			0xffffffff
2279
+#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT			0
2280
+static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2281
+{
2282
+	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2283
+}
2284
+
2285
+#define REG_CP_SMMU_TABLE_UPDATE_1				0x00000001
2286
+#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK			0x0000ffff
2287
+#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT			0
2288
+static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2289
+{
2290
+	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2291
+}
2292
+#define CP_SMMU_TABLE_UPDATE_1_ASID__MASK			0xffff0000
2293
+#define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT			16
2294
+static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2295
+{
2296
+	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2297
+}
2298
+
2299
+#define REG_CP_SMMU_TABLE_UPDATE_2				0x00000002
2300
+#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK			0xffffffff
2301
+#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT		0
2302
+static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2303
+{
2304
+	return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2305
+}
2306
+
2307
+#define REG_CP_SMMU_TABLE_UPDATE_3				0x00000003
2308
+#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK		0xffffffff
2309
+#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT		0
2310
+static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2311
+{
2312
+	return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2313
+}
15562314 
15572315 
15582316 #endif /* ADRENO_PM4_XML */