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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/msm/adreno/adreno_gpu.h
....@@ -1,52 +1,23 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013 Red Hat
34  * Author: Rob Clark <robdclark@gmail.com>
45  *
5
- * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License version 2 as published by
9
- * the Free Software Foundation.
10
- *
11
- * This program is distributed in the hope that it will be useful, but WITHOUT
12
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14
- * more details.
15
- *
16
- * You should have received a copy of the GNU General Public License along with
17
- * this program.  If not, see <http://www.gnu.org/licenses/>.
6
+ * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
187  */
198 
209 #ifndef __ADRENO_GPU_H__
2110 #define __ADRENO_GPU_H__
2211 
2312 #include <linux/firmware.h>
13
+#include <linux/iopoll.h>
2414 
2515 #include "msm_gpu.h"
2616 
2717 #include "adreno_common.xml.h"
2818 #include "adreno_pm4.xml.h"
2919 
30
-#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
31
-#define REG_SKIP ~0
32
-#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
33
-
34
-/**
35
- * adreno_regs: List of registers that are used in across all
36
- * 3D devices. Each device type has different offset value for the same
37
- * register, so an array of register offsets are declared for every device
38
- * and are indexed by the enumeration values defined in this enum
39
- */
40
-enum adreno_regs {
41
-	REG_ADRENO_CP_RB_BASE,
42
-	REG_ADRENO_CP_RB_BASE_HI,
43
-	REG_ADRENO_CP_RB_RPTR_ADDR,
44
-	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
45
-	REG_ADRENO_CP_RB_RPTR,
46
-	REG_ADRENO_CP_RB_WPTR,
47
-	REG_ADRENO_CP_RB_CNTL,
48
-	REG_ADRENO_REGISTER_MAX,
49
-};
20
+extern bool snapshot_debugbus;
5021 
5122 enum {
5223 	ADRENO_FW_PM4 = 0,
....@@ -57,10 +28,9 @@
5728 	ADRENO_FW_MAX,
5829 };
5930 
60
-enum adreno_quirks {
61
-	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
62
-	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
63
-};
31
+#define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
32
+#define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
33
+#define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
6434 
6535 struct adreno_rev {
6636 	uint8_t  core;
....@@ -77,16 +47,24 @@
7747 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
7848 };
7949 
50
+struct adreno_reglist {
51
+	u32 offset;
52
+	u32 value;
53
+};
54
+
55
+extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
56
+
8057 struct adreno_info {
8158 	struct adreno_rev rev;
8259 	uint32_t revn;
8360 	const char *name;
8461 	const char *fw[ADRENO_FW_MAX];
8562 	uint32_t gmem;
86
-	enum adreno_quirks quirks;
63
+	u64 quirks;
8764 	struct msm_gpu *(*init)(struct drm_device *dev);
8865 	const char *zapfw;
8966 	u32 inactive_period;
67
+	const struct adreno_reglist *hwcg;
9068 };
9169 
9270 const struct adreno_info *adreno_info(struct adreno_rev rev);
....@@ -135,6 +113,12 @@
135113 };
136114 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
137115 
116
+struct adreno_ocmem {
117
+	struct ocmem *ocmem;
118
+	unsigned long base;
119
+	void *hdl;
120
+};
121
+
138122 /* platform config data (ie. from DT, or pdata) */
139123 struct adreno_platform_config {
140124 	struct adreno_rev rev;
....@@ -154,10 +138,19 @@
154138 	__ret;                                             \
155139 })
156140 
157
-
158
-static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
141
+static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
159142 {
160
-	return (gpu->revn >= 300) && (gpu->revn < 400);
143
+	return (gpu->revn < 300);
144
+}
145
+
146
+static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
147
+{
148
+	return (gpu->revn < 210);
149
+}
150
+
151
+static inline bool adreno_is_a225(struct adreno_gpu *gpu)
152
+{
153
+	return gpu->revn == 225;
161154 }
162155 
163156 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
....@@ -186,9 +179,9 @@
186179 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
187180 }
188181 
189
-static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
182
+static inline int adreno_is_a405(struct adreno_gpu *gpu)
190183 {
191
-	return (gpu->revn >= 400) && (gpu->revn < 500);
184
+	return gpu->revn == 405;
192185 }
193186 
194187 static inline int adreno_is_a420(struct adreno_gpu *gpu)
....@@ -201,9 +194,39 @@
201194        return gpu->revn == 430;
202195 }
203196 
197
+static inline int adreno_is_a510(struct adreno_gpu *gpu)
198
+{
199
+	return gpu->revn == 510;
200
+}
201
+
204202 static inline int adreno_is_a530(struct adreno_gpu *gpu)
205203 {
206204 	return gpu->revn == 530;
205
+}
206
+
207
+static inline int adreno_is_a540(struct adreno_gpu *gpu)
208
+{
209
+	return gpu->revn == 540;
210
+}
211
+
212
+static inline int adreno_is_a618(struct adreno_gpu *gpu)
213
+{
214
+       return gpu->revn == 618;
215
+}
216
+
217
+static inline int adreno_is_a630(struct adreno_gpu *gpu)
218
+{
219
+       return gpu->revn == 630;
220
+}
221
+
222
+static inline int adreno_is_a640(struct adreno_gpu *gpu)
223
+{
224
+       return gpu->revn == 640;
225
+}
226
+
227
+static inline int adreno_is_a650(struct adreno_gpu *gpu)
228
+{
229
+       return gpu->revn == 650;
207230 }
208231 
209232 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
....@@ -213,9 +236,7 @@
213236 		const struct firmware *fw, u64 *iova);
214237 int adreno_hw_init(struct msm_gpu *gpu);
215238 void adreno_recover(struct msm_gpu *gpu);
216
-void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
217
-		struct msm_file_private *ctx);
218
-void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
239
+void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
219240 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
220241 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
221242 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
....@@ -225,6 +246,10 @@
225246 void adreno_dump(struct msm_gpu *gpu);
226247 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
227248 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
249
+
250
+int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
251
+			  struct adreno_ocmem *ocmem);
252
+void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
228253 
229254 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
230255 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
....@@ -236,6 +261,20 @@
236261 
237262 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
238263 int adreno_gpu_state_put(struct msm_gpu_state *state);
264
+
265
+/*
266
+ * Common helper function to initialize the default address space for arm-smmu
267
+ * attached targets
268
+ */
269
+struct msm_gem_address_space *
270
+adreno_iommu_create_address_space(struct msm_gpu *gpu,
271
+		struct platform_device *pdev);
272
+
273
+/*
274
+ * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
275
+ * out of secure mode
276
+ */
277
+int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
239278 
240279 /* ringbuffer helpers (the parts that are adreno specific) */
241280 
....@@ -291,60 +330,11 @@
291330 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
292331 }
293332 
294
-/*
295
- * adreno_reg_check() - Checks the validity of a register enum
296
- * @gpu:		Pointer to struct adreno_gpu
297
- * @offset_name:	The register enum that is checked
298
- */
299
-static inline bool adreno_reg_check(struct adreno_gpu *gpu,
300
-		enum adreno_regs offset_name)
301
-{
302
-	if (offset_name >= REG_ADRENO_REGISTER_MAX ||
303
-			!gpu->reg_offsets[offset_name]) {
304
-		BUG();
305
-	}
306
-
307
-	/*
308
-	 * REG_SKIP is a special value that tell us that the register in
309
-	 * question isn't implemented on target but don't trigger a BUG(). This
310
-	 * is used to cleanly implement adreno_gpu_write64() and
311
-	 * adreno_gpu_read64() in a generic fashion
312
-	 */
313
-	if (gpu->reg_offsets[offset_name] == REG_SKIP)
314
-		return false;
315
-
316
-	return true;
317
-}
318
-
319
-static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
320
-		enum adreno_regs offset_name)
321
-{
322
-	u32 reg = gpu->reg_offsets[offset_name];
323
-	u32 val = 0;
324
-	if(adreno_reg_check(gpu,offset_name))
325
-		val = gpu_read(&gpu->base, reg - 1);
326
-	return val;
327
-}
328
-
329
-static inline void adreno_gpu_write(struct adreno_gpu *gpu,
330
-		enum adreno_regs offset_name, u32 data)
331
-{
332
-	u32 reg = gpu->reg_offsets[offset_name];
333
-	if(adreno_reg_check(gpu, offset_name))
334
-		gpu_write(&gpu->base, reg - 1, data);
335
-}
336
-
333
+struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
337334 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
338335 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
339336 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
340337 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
341
-
342
-static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
343
-		enum adreno_regs lo, enum adreno_regs hi, u64 data)
344
-{
345
-	adreno_gpu_write(gpu, lo, lower_32_bits(data));
346
-	adreno_gpu_write(gpu, hi, upper_32_bits(data));
347
-}
348338 
349339 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
350340 {
....@@ -375,4 +365,9 @@
375365 	((1 << 29) \
376366 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
377367 
368
+
369
+#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
370
+	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
371
+		interval, timeout)
372
+
378373 #endif /* __ADRENO_GPU_H__ */