modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
..
..
@@ -8,19 +8,21 @@
8
8
 git clone https://github.com/freedreno/envytools.git
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9
 
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10
 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
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-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
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-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
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-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
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+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
22
24
 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
24
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 - Rob Clark <robdclark@gmail.com> (robclark)
25
27
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
28
 
..
..
@@ -46,24 +48,109 @@
46
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 */
47
49
 
48
50
 
49
-#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB			0x00800000
50
-#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB		0x40000000
51
-#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK			0x00400000
52
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK			0x40000000
53
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK			0x40000000
54
-#define A6XX_GMU_OOB_DCVS_SET_MASK				0x00800000
55
-#define A6XX_GMU_OOB_DCVS_CHECK_MASK				0x80000000
56
-#define A6XX_GMU_OOB_DCVS_CLEAR_MASK				0x80000000
57
-#define A6XX_GMU_OOB_GPU_SET_MASK				0x00040000
58
-#define A6XX_GMU_OOB_GPU_CHECK_MASK				0x04000000
59
-#define A6XX_GMU_OOB_GPU_CLEAR_MASK				0x04000000
60
-#define A6XX_GMU_OOB_PERFCNTR_SET_MASK				0x00020000
61
-#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK			0x02000000
62
-#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK			0x02000000
51
+#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK		0x00800000
52
+#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT		23
53
+static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)
54
+{
55
+	return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK;
56
+}
57
+#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK	0x40000000
58
+#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT	30
59
+static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)
60
+{
61
+	return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK;
62
+}
63
+#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK		0x00400000
64
+#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT		22
65
+static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)
66
+{
67
+	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK;
68
+}
69
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK		0x40000000
70
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT		30
71
+static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)
72
+{
73
+	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK;
74
+}
75
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK		0x40000000
76
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT		30
77
+static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)
78
+{
79
+	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK;
80
+}
81
+#define A6XX_GMU_OOB_DCVS_SET_MASK__MASK			0x00800000
82
+#define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT			23
83
+static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)
84
+{
85
+	return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK;
86
+}
87
+#define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK			0x80000000
88
+#define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT			31
89
+static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)
90
+{
91
+	return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK;
92
+}
93
+#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK			0x80000000
94
+#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT			31
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+static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)
96
+{
97
+	return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK;
98
+}
99
+#define A6XX_GMU_OOB_GPU_SET_MASK__MASK				0x00040000
100
+#define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT			18
101
+static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)
102
+{
103
+	return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK;
104
+}
105
+#define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK			0x04000000
106
+#define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT			26
107
+static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)
108
+{
109
+	return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK;
110
+}
111
+#define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK			0x04000000
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+#define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT			26
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+static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)
114
+{
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+	return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK;
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+}
117
+#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK			0x00020000
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+#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT			17
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+static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)
120
+{
121
+	return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK;
122
+}
123
+#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK			0x02000000
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+#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT			25
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+static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)
126
+{
127
+	return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK;
128
+}
129
+#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK			0x02000000
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+#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT			25
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+static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)
132
+{
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+	return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK;
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+}
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 #define A6XX_HFI_IRQ_MSGQ_MASK					0x00000001
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-#define A6XX_HFI_IRQ_DSGQ_MASK					0x00000002
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-#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK				0x00000004
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-#define A6XX_HFI_IRQ_CM3_FAULT_MASK				0x00800000
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+#define A6XX_HFI_IRQ_DSGQ_MASK__MASK				0x00000002
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+#define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT				1
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+static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)
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+{
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+	return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK;
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+}
142
+#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK			0x00000004
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+#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT			2
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+static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)
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+{
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+	return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK;
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+}
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+#define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK			0x00800000
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+#define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT			23
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+static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)
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+{
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+	return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK;
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+}
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 #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK				0x007f0000
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 #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT			16
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 static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
..
..
@@ -100,6 +187,10 @@
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 #define REG_A6XX_GMU_DCVS_BW_SETTING				0x000023fe
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 #define REG_A6XX_GMU_DCVS_RETURN				0x000023ff
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+
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+#define REG_A6XX_GMU_ICACHE_CONFIG				0x00004c00
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+
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+#define REG_A6XX_GMU_DCACHE_CONFIG				0x00004c01
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 #define REG_A6XX_GMU_SYS_BUS_CONFIG				0x00004c0f
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..
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@@ -167,8 +258,8 @@
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 #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS			0x000050d0
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 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF	0x00000001
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 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON	0x00000002
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-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON	0x00000004
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-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF	0x00000008
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+#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF	0x00000004
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+#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON	0x00000008
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 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF		0x00000010
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 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE	0x00000020
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 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF	0x00000040
..
..
@@ -198,6 +289,12 @@
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 #define REG_A6XX_GMU_RPMH_HYST_CTRL				0x000050e9
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 #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE		0x000050ec
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+
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+#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF			0x000050f0
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+
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+#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG			0x00005100
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+
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+#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP			0x00005101
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 #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE			0x000051f0
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..
..
@@ -330,8 +427,6 @@
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331
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 #define REG_A6XX_GMU_AO_SPARE_CNTL				0x00009316
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429
 
333
-#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0			0x00008c04
334
-
335
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 #define REG_A6XX_GMU_RSCC_CONTROL_REQ				0x00009307
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431
 
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 #define REG_A6XX_GMU_RSCC_CONTROL_ACK				0x00009308
..
..
@@ -344,39 +439,41 @@
344
439
 
345
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 #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC				0x00009d42
346
441
 
347
-#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR			0x00008c08
442
+#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0			0x00000004
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443
 
349
-#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO			0x00008c09
444
+#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR			0x00000008
350
445
 
351
-#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI			0x00008c0a
446
+#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO			0x00000009
352
447
 
353
-#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0				0x00008c0b
448
+#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI			0x0000000a
354
449
 
355
-#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR			0x00008c0d
450
+#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0				0x0000000b
356
451
 
357
-#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA			0x00008c0e
452
+#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR			0x0000000d
358
453
 
359
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0		0x00008c82
454
+#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA			0x0000000e
360
455
 
361
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0		0x00008c83
456
+#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0		0x00000082
362
457
 
363
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0			0x00008c89
458
+#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0		0x00000083
364
459
 
365
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0		0x00008c8c
460
+#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0			0x00000089
366
461
 
367
-#define REG_A6XX_RSCC_OVERRIDE_START_ADDR			0x00008d00
462
+#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0		0x0000008c
368
463
 
369
-#define REG_A6XX_RSCC_SEQ_BUSY_DRV0				0x00008d01
464
+#define REG_A6XX_RSCC_OVERRIDE_START_ADDR			0x00000100
370
465
 
371
-#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0				0x00008d80
466
+#define REG_A6XX_RSCC_SEQ_BUSY_DRV0				0x00000101
372
467
 
373
-#define REG_A6XX_RSCC_TCS0_DRV0_STATUS				0x00008f46
468
+#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0				0x00000180
374
469
 
375
-#define REG_A6XX_RSCC_TCS1_DRV0_STATUS				0x000090ae
470
+#define REG_A6XX_RSCC_TCS0_DRV0_STATUS				0x00000346
376
471
 
377
-#define REG_A6XX_RSCC_TCS2_DRV0_STATUS				0x00009216
472
+#define REG_A6XX_RSCC_TCS1_DRV0_STATUS				0x000003ee
378
473
 
379
-#define REG_A6XX_RSCC_TCS3_DRV0_STATUS				0x0000937e
474
+#define REG_A6XX_RSCC_TCS2_DRV0_STATUS				0x00000496
475
+
476
+#define REG_A6XX_RSCC_TCS3_DRV0_STATUS				0x0000053e
380
477
 
381
478
 
382
479
 #endif /* A6XX_GMU_XML */