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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/msm/adreno/a6xx.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -46,219 +48,134 @@
4648 */
4749 
4850 
49
-enum a6xx_color_fmt {
50
-	RB6_A8_UNORM = 2,
51
-	RB6_R8_UNORM = 3,
52
-	RB6_R8_SNORM = 4,
53
-	RB6_R8_UINT = 5,
54
-	RB6_R8_SINT = 6,
55
-	RB6_R4G4B4A4_UNORM = 8,
56
-	RB6_R5G5B5A1_UNORM = 10,
57
-	RB6_R5G6B5_UNORM = 14,
58
-	RB6_R8G8_UNORM = 15,
59
-	RB6_R8G8_SNORM = 16,
60
-	RB6_R8G8_UINT = 17,
61
-	RB6_R8G8_SINT = 18,
62
-	RB6_R16_UNORM = 21,
63
-	RB6_R16_SNORM = 22,
64
-	RB6_R16_FLOAT = 23,
65
-	RB6_R16_UINT = 24,
66
-	RB6_R16_SINT = 25,
67
-	RB6_R8G8B8A8_UNORM = 48,
68
-	RB6_R8G8B8_UNORM = 49,
69
-	RB6_R8G8B8A8_SNORM = 50,
70
-	RB6_R8G8B8A8_UINT = 51,
71
-	RB6_R8G8B8A8_SINT = 52,
72
-	RB6_R10G10B10A2_UNORM = 55,
73
-	RB6_R10G10B10A2_UINT = 58,
74
-	RB6_R11G11B10_FLOAT = 66,
75
-	RB6_R16G16_UNORM = 67,
76
-	RB6_R16G16_SNORM = 68,
77
-	RB6_R16G16_FLOAT = 69,
78
-	RB6_R16G16_UINT = 70,
79
-	RB6_R16G16_SINT = 71,
80
-	RB6_R32_FLOAT = 74,
81
-	RB6_R32_UINT = 75,
82
-	RB6_R32_SINT = 76,
83
-	RB6_R16G16B16A16_UNORM = 96,
84
-	RB6_R16G16B16A16_SNORM = 97,
85
-	RB6_R16G16B16A16_FLOAT = 98,
86
-	RB6_R16G16B16A16_UINT = 99,
87
-	RB6_R16G16B16A16_SINT = 100,
88
-	RB6_R32G32_FLOAT = 103,
89
-	RB6_R32G32_UINT = 104,
90
-	RB6_R32G32_SINT = 105,
91
-	RB6_R32G32B32A32_FLOAT = 130,
92
-	RB6_R32G32B32A32_UINT = 131,
93
-	RB6_R32G32B32A32_SINT = 132,
94
-	RB6_X8Z24_UNORM = 160,
95
-};
96
-
9751 enum a6xx_tile_mode {
9852 	TILE6_LINEAR = 0,
9953 	TILE6_2 = 2,
10054 	TILE6_3 = 3,
10155 };
10256 
103
-enum a6xx_vtx_fmt {
104
-	VFMT6_8_UNORM = 3,
105
-	VFMT6_8_SNORM = 4,
106
-	VFMT6_8_UINT = 5,
107
-	VFMT6_8_SINT = 6,
108
-	VFMT6_8_8_UNORM = 15,
109
-	VFMT6_8_8_SNORM = 16,
110
-	VFMT6_8_8_UINT = 17,
111
-	VFMT6_8_8_SINT = 18,
112
-	VFMT6_16_UNORM = 21,
113
-	VFMT6_16_SNORM = 22,
114
-	VFMT6_16_FLOAT = 23,
115
-	VFMT6_16_UINT = 24,
116
-	VFMT6_16_SINT = 25,
117
-	VFMT6_8_8_8_UNORM = 33,
118
-	VFMT6_8_8_8_SNORM = 34,
119
-	VFMT6_8_8_8_UINT = 35,
120
-	VFMT6_8_8_8_SINT = 36,
121
-	VFMT6_8_8_8_8_UNORM = 48,
122
-	VFMT6_8_8_8_8_SNORM = 50,
123
-	VFMT6_8_8_8_8_UINT = 51,
124
-	VFMT6_8_8_8_8_SINT = 52,
125
-	VFMT6_10_10_10_2_UNORM = 54,
126
-	VFMT6_10_10_10_2_SNORM = 57,
127
-	VFMT6_10_10_10_2_UINT = 58,
128
-	VFMT6_10_10_10_2_SINT = 59,
129
-	VFMT6_11_11_10_FLOAT = 66,
130
-	VFMT6_16_16_UNORM = 67,
131
-	VFMT6_16_16_SNORM = 68,
132
-	VFMT6_16_16_FLOAT = 69,
133
-	VFMT6_16_16_UINT = 70,
134
-	VFMT6_16_16_SINT = 71,
135
-	VFMT6_32_UNORM = 72,
136
-	VFMT6_32_SNORM = 73,
137
-	VFMT6_32_FLOAT = 74,
138
-	VFMT6_32_UINT = 75,
139
-	VFMT6_32_SINT = 76,
140
-	VFMT6_32_FIXED = 77,
141
-	VFMT6_16_16_16_UNORM = 88,
142
-	VFMT6_16_16_16_SNORM = 89,
143
-	VFMT6_16_16_16_FLOAT = 90,
144
-	VFMT6_16_16_16_UINT = 91,
145
-	VFMT6_16_16_16_SINT = 92,
146
-	VFMT6_16_16_16_16_UNORM = 96,
147
-	VFMT6_16_16_16_16_SNORM = 97,
148
-	VFMT6_16_16_16_16_FLOAT = 98,
149
-	VFMT6_16_16_16_16_UINT = 99,
150
-	VFMT6_16_16_16_16_SINT = 100,
151
-	VFMT6_32_32_UNORM = 101,
152
-	VFMT6_32_32_SNORM = 102,
153
-	VFMT6_32_32_FLOAT = 103,
154
-	VFMT6_32_32_UINT = 104,
155
-	VFMT6_32_32_SINT = 105,
156
-	VFMT6_32_32_FIXED = 106,
157
-	VFMT6_32_32_32_UNORM = 112,
158
-	VFMT6_32_32_32_SNORM = 113,
159
-	VFMT6_32_32_32_UINT = 114,
160
-	VFMT6_32_32_32_SINT = 115,
161
-	VFMT6_32_32_32_FLOAT = 116,
162
-	VFMT6_32_32_32_FIXED = 117,
163
-	VFMT6_32_32_32_32_UNORM = 128,
164
-	VFMT6_32_32_32_32_SNORM = 129,
165
-	VFMT6_32_32_32_32_FLOAT = 130,
166
-	VFMT6_32_32_32_32_UINT = 131,
167
-	VFMT6_32_32_32_32_SINT = 132,
168
-	VFMT6_32_32_32_32_FIXED = 133,
57
+enum a6xx_format {
58
+	FMT6_A8_UNORM = 2,
59
+	FMT6_8_UNORM = 3,
60
+	FMT6_8_SNORM = 4,
61
+	FMT6_8_UINT = 5,
62
+	FMT6_8_SINT = 6,
63
+	FMT6_4_4_4_4_UNORM = 8,
64
+	FMT6_5_5_5_1_UNORM = 10,
65
+	FMT6_1_5_5_5_UNORM = 12,
66
+	FMT6_5_6_5_UNORM = 14,
67
+	FMT6_8_8_UNORM = 15,
68
+	FMT6_8_8_SNORM = 16,
69
+	FMT6_8_8_UINT = 17,
70
+	FMT6_8_8_SINT = 18,
71
+	FMT6_L8_A8_UNORM = 19,
72
+	FMT6_16_UNORM = 21,
73
+	FMT6_16_SNORM = 22,
74
+	FMT6_16_FLOAT = 23,
75
+	FMT6_16_UINT = 24,
76
+	FMT6_16_SINT = 25,
77
+	FMT6_8_8_8_UNORM = 33,
78
+	FMT6_8_8_8_SNORM = 34,
79
+	FMT6_8_8_8_UINT = 35,
80
+	FMT6_8_8_8_SINT = 36,
81
+	FMT6_8_8_8_8_UNORM = 48,
82
+	FMT6_8_8_8_X8_UNORM = 49,
83
+	FMT6_8_8_8_8_SNORM = 50,
84
+	FMT6_8_8_8_8_UINT = 51,
85
+	FMT6_8_8_8_8_SINT = 52,
86
+	FMT6_9_9_9_E5_FLOAT = 53,
87
+	FMT6_10_10_10_2_UNORM = 54,
88
+	FMT6_10_10_10_2_UNORM_DEST = 55,
89
+	FMT6_10_10_10_2_SNORM = 57,
90
+	FMT6_10_10_10_2_UINT = 58,
91
+	FMT6_10_10_10_2_SINT = 59,
92
+	FMT6_11_11_10_FLOAT = 66,
93
+	FMT6_16_16_UNORM = 67,
94
+	FMT6_16_16_SNORM = 68,
95
+	FMT6_16_16_FLOAT = 69,
96
+	FMT6_16_16_UINT = 70,
97
+	FMT6_16_16_SINT = 71,
98
+	FMT6_32_UNORM = 72,
99
+	FMT6_32_SNORM = 73,
100
+	FMT6_32_FLOAT = 74,
101
+	FMT6_32_UINT = 75,
102
+	FMT6_32_SINT = 76,
103
+	FMT6_32_FIXED = 77,
104
+	FMT6_16_16_16_UNORM = 88,
105
+	FMT6_16_16_16_SNORM = 89,
106
+	FMT6_16_16_16_FLOAT = 90,
107
+	FMT6_16_16_16_UINT = 91,
108
+	FMT6_16_16_16_SINT = 92,
109
+	FMT6_16_16_16_16_UNORM = 96,
110
+	FMT6_16_16_16_16_SNORM = 97,
111
+	FMT6_16_16_16_16_FLOAT = 98,
112
+	FMT6_16_16_16_16_UINT = 99,
113
+	FMT6_16_16_16_16_SINT = 100,
114
+	FMT6_32_32_UNORM = 101,
115
+	FMT6_32_32_SNORM = 102,
116
+	FMT6_32_32_FLOAT = 103,
117
+	FMT6_32_32_UINT = 104,
118
+	FMT6_32_32_SINT = 105,
119
+	FMT6_32_32_FIXED = 106,
120
+	FMT6_32_32_32_UNORM = 112,
121
+	FMT6_32_32_32_SNORM = 113,
122
+	FMT6_32_32_32_UINT = 114,
123
+	FMT6_32_32_32_SINT = 115,
124
+	FMT6_32_32_32_FLOAT = 116,
125
+	FMT6_32_32_32_FIXED = 117,
126
+	FMT6_32_32_32_32_UNORM = 128,
127
+	FMT6_32_32_32_32_SNORM = 129,
128
+	FMT6_32_32_32_32_FLOAT = 130,
129
+	FMT6_32_32_32_32_UINT = 131,
130
+	FMT6_32_32_32_32_SINT = 132,
131
+	FMT6_32_32_32_32_FIXED = 133,
132
+	FMT6_G8R8B8R8_422_UNORM = 140,
133
+	FMT6_R8G8R8B8_422_UNORM = 141,
134
+	FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
135
+	FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
136
+	FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
137
+	FMT6_8_PLANE_UNORM = 148,
138
+	FMT6_Z24_UNORM_S8_UINT = 160,
139
+	FMT6_ETC2_RG11_UNORM = 171,
140
+	FMT6_ETC2_RG11_SNORM = 172,
141
+	FMT6_ETC2_R11_UNORM = 173,
142
+	FMT6_ETC2_R11_SNORM = 174,
143
+	FMT6_ETC1 = 175,
144
+	FMT6_ETC2_RGB8 = 176,
145
+	FMT6_ETC2_RGBA8 = 177,
146
+	FMT6_ETC2_RGB8A1 = 178,
147
+	FMT6_DXT1 = 179,
148
+	FMT6_DXT3 = 180,
149
+	FMT6_DXT5 = 181,
150
+	FMT6_RGTC1_UNORM = 183,
151
+	FMT6_RGTC1_SNORM = 184,
152
+	FMT6_RGTC2_UNORM = 187,
153
+	FMT6_RGTC2_SNORM = 188,
154
+	FMT6_BPTC_UFLOAT = 190,
155
+	FMT6_BPTC_FLOAT = 191,
156
+	FMT6_BPTC = 192,
157
+	FMT6_ASTC_4x4 = 193,
158
+	FMT6_ASTC_5x4 = 194,
159
+	FMT6_ASTC_5x5 = 195,
160
+	FMT6_ASTC_6x5 = 196,
161
+	FMT6_ASTC_6x6 = 197,
162
+	FMT6_ASTC_8x5 = 198,
163
+	FMT6_ASTC_8x6 = 199,
164
+	FMT6_ASTC_8x8 = 200,
165
+	FMT6_ASTC_10x5 = 201,
166
+	FMT6_ASTC_10x6 = 202,
167
+	FMT6_ASTC_10x8 = 203,
168
+	FMT6_ASTC_10x10 = 204,
169
+	FMT6_ASTC_12x10 = 205,
170
+	FMT6_ASTC_12x12 = 206,
171
+	FMT6_S8Z24_UINT = 234,
172
+	FMT6_NONE = 255,
169173 };
170174 
171
-enum a6xx_tex_fmt {
172
-	TFMT6_A8_UNORM = 2,
173
-	TFMT6_8_UNORM = 3,
174
-	TFMT6_8_SNORM = 4,
175
-	TFMT6_8_UINT = 5,
176
-	TFMT6_8_SINT = 6,
177
-	TFMT6_4_4_4_4_UNORM = 8,
178
-	TFMT6_5_5_5_1_UNORM = 10,
179
-	TFMT6_5_6_5_UNORM = 14,
180
-	TFMT6_8_8_UNORM = 15,
181
-	TFMT6_8_8_SNORM = 16,
182
-	TFMT6_8_8_UINT = 17,
183
-	TFMT6_8_8_SINT = 18,
184
-	TFMT6_L8_A8_UNORM = 19,
185
-	TFMT6_16_UNORM = 21,
186
-	TFMT6_16_SNORM = 22,
187
-	TFMT6_16_FLOAT = 23,
188
-	TFMT6_16_UINT = 24,
189
-	TFMT6_16_SINT = 25,
190
-	TFMT6_8_8_8_8_UNORM = 48,
191
-	TFMT6_8_8_8_UNORM = 49,
192
-	TFMT6_8_8_8_8_SNORM = 50,
193
-	TFMT6_8_8_8_8_UINT = 51,
194
-	TFMT6_8_8_8_8_SINT = 52,
195
-	TFMT6_9_9_9_E5_FLOAT = 53,
196
-	TFMT6_10_10_10_2_UNORM = 54,
197
-	TFMT6_10_10_10_2_UINT = 58,
198
-	TFMT6_11_11_10_FLOAT = 66,
199
-	TFMT6_16_16_UNORM = 67,
200
-	TFMT6_16_16_SNORM = 68,
201
-	TFMT6_16_16_FLOAT = 69,
202
-	TFMT6_16_16_UINT = 70,
203
-	TFMT6_16_16_SINT = 71,
204
-	TFMT6_32_FLOAT = 74,
205
-	TFMT6_32_UINT = 75,
206
-	TFMT6_32_SINT = 76,
207
-	TFMT6_16_16_16_16_UNORM = 96,
208
-	TFMT6_16_16_16_16_SNORM = 97,
209
-	TFMT6_16_16_16_16_FLOAT = 98,
210
-	TFMT6_16_16_16_16_UINT = 99,
211
-	TFMT6_16_16_16_16_SINT = 100,
212
-	TFMT6_32_32_FLOAT = 103,
213
-	TFMT6_32_32_UINT = 104,
214
-	TFMT6_32_32_SINT = 105,
215
-	TFMT6_32_32_32_UINT = 114,
216
-	TFMT6_32_32_32_SINT = 115,
217
-	TFMT6_32_32_32_FLOAT = 116,
218
-	TFMT6_32_32_32_32_FLOAT = 130,
219
-	TFMT6_32_32_32_32_UINT = 131,
220
-	TFMT6_32_32_32_32_SINT = 132,
221
-	TFMT6_X8Z24_UNORM = 160,
222
-	TFMT6_ETC2_RG11_UNORM = 171,
223
-	TFMT6_ETC2_RG11_SNORM = 172,
224
-	TFMT6_ETC2_R11_UNORM = 173,
225
-	TFMT6_ETC2_R11_SNORM = 174,
226
-	TFMT6_ETC1 = 175,
227
-	TFMT6_ETC2_RGB8 = 176,
228
-	TFMT6_ETC2_RGBA8 = 177,
229
-	TFMT6_ETC2_RGB8A1 = 178,
230
-	TFMT6_DXT1 = 179,
231
-	TFMT6_DXT3 = 180,
232
-	TFMT6_DXT5 = 181,
233
-	TFMT6_RGTC1_UNORM = 183,
234
-	TFMT6_RGTC1_SNORM = 184,
235
-	TFMT6_RGTC2_UNORM = 187,
236
-	TFMT6_RGTC2_SNORM = 188,
237
-	TFMT6_BPTC_UFLOAT = 190,
238
-	TFMT6_BPTC_FLOAT = 191,
239
-	TFMT6_BPTC = 192,
240
-	TFMT6_ASTC_4x4 = 193,
241
-	TFMT6_ASTC_5x4 = 194,
242
-	TFMT6_ASTC_5x5 = 195,
243
-	TFMT6_ASTC_6x5 = 196,
244
-	TFMT6_ASTC_6x6 = 197,
245
-	TFMT6_ASTC_8x5 = 198,
246
-	TFMT6_ASTC_8x6 = 199,
247
-	TFMT6_ASTC_8x8 = 200,
248
-	TFMT6_ASTC_10x5 = 201,
249
-	TFMT6_ASTC_10x6 = 202,
250
-	TFMT6_ASTC_10x8 = 203,
251
-	TFMT6_ASTC_10x10 = 204,
252
-	TFMT6_ASTC_12x10 = 205,
253
-	TFMT6_ASTC_12x12 = 206,
254
-};
255
-
256
-enum a6xx_tex_fetchsize {
257
-	TFETCH6_1_BYTE = 0,
258
-	TFETCH6_2_BYTE = 1,
259
-	TFETCH6_4_BYTE = 2,
260
-	TFETCH6_8_BYTE = 3,
261
-	TFETCH6_16_BYTE = 4,
175
+enum a6xx_polygon_mode {
176
+	POLYMODE6_POINTS = 1,
177
+	POLYMODE6_LINES = 2,
178
+	POLYMODE6_TRIANGLES = 3,
262179 };
263180 
264181 enum a6xx_depth_format {
....@@ -268,14 +185,733 @@
268185 	DEPTH6_32 = 4,
269186 };
270187 
188
+enum a6xx_shader_id {
189
+	A6XX_TP0_TMO_DATA = 9,
190
+	A6XX_TP0_SMO_DATA = 10,
191
+	A6XX_TP0_MIPMAP_BASE_DATA = 11,
192
+	A6XX_TP1_TMO_DATA = 25,
193
+	A6XX_TP1_SMO_DATA = 26,
194
+	A6XX_TP1_MIPMAP_BASE_DATA = 27,
195
+	A6XX_SP_INST_DATA = 41,
196
+	A6XX_SP_LB_0_DATA = 42,
197
+	A6XX_SP_LB_1_DATA = 43,
198
+	A6XX_SP_LB_2_DATA = 44,
199
+	A6XX_SP_LB_3_DATA = 45,
200
+	A6XX_SP_LB_4_DATA = 46,
201
+	A6XX_SP_LB_5_DATA = 47,
202
+	A6XX_SP_CB_BINDLESS_DATA = 48,
203
+	A6XX_SP_CB_LEGACY_DATA = 49,
204
+	A6XX_SP_UAV_DATA = 50,
205
+	A6XX_SP_INST_TAG = 51,
206
+	A6XX_SP_CB_BINDLESS_TAG = 52,
207
+	A6XX_SP_TMO_UMO_TAG = 53,
208
+	A6XX_SP_SMO_TAG = 54,
209
+	A6XX_SP_STATE_DATA = 55,
210
+	A6XX_HLSQ_CHUNK_CVS_RAM = 73,
211
+	A6XX_HLSQ_CHUNK_CPS_RAM = 74,
212
+	A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
213
+	A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
214
+	A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
215
+	A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
216
+	A6XX_HLSQ_CVS_MISC_RAM = 80,
217
+	A6XX_HLSQ_CPS_MISC_RAM = 81,
218
+	A6XX_HLSQ_INST_RAM = 82,
219
+	A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
220
+	A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
221
+	A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
222
+	A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
223
+	A6XX_HLSQ_INST_RAM_TAG = 87,
224
+	A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
225
+	A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
226
+	A6XX_HLSQ_PWR_REST_RAM = 90,
227
+	A6XX_HLSQ_PWR_REST_TAG = 91,
228
+	A6XX_HLSQ_DATAPATH_META = 96,
229
+	A6XX_HLSQ_FRONTEND_META = 97,
230
+	A6XX_HLSQ_INDIRECT_META = 98,
231
+	A6XX_HLSQ_BACKEND_META = 99,
232
+};
233
+
234
+enum a6xx_debugbus_id {
235
+	A6XX_DBGBUS_CP = 1,
236
+	A6XX_DBGBUS_RBBM = 2,
237
+	A6XX_DBGBUS_VBIF = 3,
238
+	A6XX_DBGBUS_HLSQ = 4,
239
+	A6XX_DBGBUS_UCHE = 5,
240
+	A6XX_DBGBUS_DPM = 6,
241
+	A6XX_DBGBUS_TESS = 7,
242
+	A6XX_DBGBUS_PC = 8,
243
+	A6XX_DBGBUS_VFDP = 9,
244
+	A6XX_DBGBUS_VPC = 10,
245
+	A6XX_DBGBUS_TSE = 11,
246
+	A6XX_DBGBUS_RAS = 12,
247
+	A6XX_DBGBUS_VSC = 13,
248
+	A6XX_DBGBUS_COM = 14,
249
+	A6XX_DBGBUS_LRZ = 16,
250
+	A6XX_DBGBUS_A2D = 17,
251
+	A6XX_DBGBUS_CCUFCHE = 18,
252
+	A6XX_DBGBUS_GMU_CX = 19,
253
+	A6XX_DBGBUS_RBP = 20,
254
+	A6XX_DBGBUS_DCS = 21,
255
+	A6XX_DBGBUS_DBGC = 22,
256
+	A6XX_DBGBUS_CX = 23,
257
+	A6XX_DBGBUS_GMU_GX = 24,
258
+	A6XX_DBGBUS_TPFCHE = 25,
259
+	A6XX_DBGBUS_GBIF_GX = 26,
260
+	A6XX_DBGBUS_GPC = 29,
261
+	A6XX_DBGBUS_LARC = 30,
262
+	A6XX_DBGBUS_HLSQ_SPTP = 31,
263
+	A6XX_DBGBUS_RB_0 = 32,
264
+	A6XX_DBGBUS_RB_1 = 33,
265
+	A6XX_DBGBUS_UCHE_WRAPPER = 36,
266
+	A6XX_DBGBUS_CCU_0 = 40,
267
+	A6XX_DBGBUS_CCU_1 = 41,
268
+	A6XX_DBGBUS_VFD_0 = 56,
269
+	A6XX_DBGBUS_VFD_1 = 57,
270
+	A6XX_DBGBUS_VFD_2 = 58,
271
+	A6XX_DBGBUS_VFD_3 = 59,
272
+	A6XX_DBGBUS_SP_0 = 64,
273
+	A6XX_DBGBUS_SP_1 = 65,
274
+	A6XX_DBGBUS_TPL1_0 = 72,
275
+	A6XX_DBGBUS_TPL1_1 = 73,
276
+	A6XX_DBGBUS_TPL1_2 = 74,
277
+	A6XX_DBGBUS_TPL1_3 = 75,
278
+};
279
+
271280 enum a6xx_cp_perfcounter_select {
272281 	PERF_CP_ALWAYS_COUNT = 0,
282
+	PERF_CP_BUSY_GFX_CORE_IDLE = 1,
283
+	PERF_CP_BUSY_CYCLES = 2,
284
+	PERF_CP_NUM_PREEMPTIONS = 3,
285
+	PERF_CP_PREEMPTION_REACTION_DELAY = 4,
286
+	PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
287
+	PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
288
+	PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
289
+	PERF_CP_PREDICATED_DRAWS_KILLED = 8,
290
+	PERF_CP_MODE_SWITCH = 9,
291
+	PERF_CP_ZPASS_DONE = 10,
292
+	PERF_CP_CONTEXT_DONE = 11,
293
+	PERF_CP_CACHE_FLUSH = 12,
294
+	PERF_CP_LONG_PREEMPTIONS = 13,
295
+	PERF_CP_SQE_I_CACHE_STARVE = 14,
296
+	PERF_CP_SQE_IDLE = 15,
297
+	PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
298
+	PERF_CP_SQE_PM4_STARVE_SDS = 17,
299
+	PERF_CP_SQE_MRB_STARVE = 18,
300
+	PERF_CP_SQE_RRB_STARVE = 19,
301
+	PERF_CP_SQE_VSD_STARVE = 20,
302
+	PERF_CP_VSD_DECODE_STARVE = 21,
303
+	PERF_CP_SQE_PIPE_OUT_STALL = 22,
304
+	PERF_CP_SQE_SYNC_STALL = 23,
305
+	PERF_CP_SQE_PM4_WFI_STALL = 24,
306
+	PERF_CP_SQE_SYS_WFI_STALL = 25,
307
+	PERF_CP_SQE_T4_EXEC = 26,
308
+	PERF_CP_SQE_LOAD_STATE_EXEC = 27,
309
+	PERF_CP_SQE_SAVE_SDS_STATE = 28,
310
+	PERF_CP_SQE_DRAW_EXEC = 29,
311
+	PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
312
+	PERF_CP_SQE_EXEC_PROFILED = 31,
313
+	PERF_CP_MEMORY_POOL_EMPTY = 32,
314
+	PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
315
+	PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
316
+	PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
317
+	PERF_CP_AHB_STALL_SQE_GMU = 36,
318
+	PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
319
+	PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
320
+	PERF_CP_CLUSTER0_EMPTY = 39,
321
+	PERF_CP_CLUSTER1_EMPTY = 40,
322
+	PERF_CP_CLUSTER2_EMPTY = 41,
323
+	PERF_CP_CLUSTER3_EMPTY = 42,
324
+	PERF_CP_CLUSTER4_EMPTY = 43,
325
+	PERF_CP_CLUSTER5_EMPTY = 44,
326
+	PERF_CP_PM4_DATA = 45,
327
+	PERF_CP_PM4_HEADERS = 46,
328
+	PERF_CP_VBIF_READ_BEATS = 47,
329
+	PERF_CP_VBIF_WRITE_BEATS = 48,
330
+	PERF_CP_SQE_INSTR_COUNTER = 49,
331
+};
332
+
333
+enum a6xx_rbbm_perfcounter_select {
334
+	PERF_RBBM_ALWAYS_COUNT = 0,
335
+	PERF_RBBM_ALWAYS_ON = 1,
336
+	PERF_RBBM_TSE_BUSY = 2,
337
+	PERF_RBBM_RAS_BUSY = 3,
338
+	PERF_RBBM_PC_DCALL_BUSY = 4,
339
+	PERF_RBBM_PC_VSD_BUSY = 5,
340
+	PERF_RBBM_STATUS_MASKED = 6,
341
+	PERF_RBBM_COM_BUSY = 7,
342
+	PERF_RBBM_DCOM_BUSY = 8,
343
+	PERF_RBBM_VBIF_BUSY = 9,
344
+	PERF_RBBM_VSC_BUSY = 10,
345
+	PERF_RBBM_TESS_BUSY = 11,
346
+	PERF_RBBM_UCHE_BUSY = 12,
347
+	PERF_RBBM_HLSQ_BUSY = 13,
348
+};
349
+
350
+enum a6xx_pc_perfcounter_select {
351
+	PERF_PC_BUSY_CYCLES = 0,
352
+	PERF_PC_WORKING_CYCLES = 1,
353
+	PERF_PC_STALL_CYCLES_VFD = 2,
354
+	PERF_PC_STALL_CYCLES_TSE = 3,
355
+	PERF_PC_STALL_CYCLES_VPC = 4,
356
+	PERF_PC_STALL_CYCLES_UCHE = 5,
357
+	PERF_PC_STALL_CYCLES_TESS = 6,
358
+	PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
359
+	PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
360
+	PERF_PC_PASS1_TF_STALL_CYCLES = 9,
361
+	PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
362
+	PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
363
+	PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
364
+	PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
365
+	PERF_PC_STARVE_CYCLES_DI = 14,
366
+	PERF_PC_VIS_STREAMS_LOADED = 15,
367
+	PERF_PC_INSTANCES = 16,
368
+	PERF_PC_VPC_PRIMITIVES = 17,
369
+	PERF_PC_DEAD_PRIM = 18,
370
+	PERF_PC_LIVE_PRIM = 19,
371
+	PERF_PC_VERTEX_HITS = 20,
372
+	PERF_PC_IA_VERTICES = 21,
373
+	PERF_PC_IA_PRIMITIVES = 22,
374
+	PERF_PC_GS_PRIMITIVES = 23,
375
+	PERF_PC_HS_INVOCATIONS = 24,
376
+	PERF_PC_DS_INVOCATIONS = 25,
377
+	PERF_PC_VS_INVOCATIONS = 26,
378
+	PERF_PC_GS_INVOCATIONS = 27,
379
+	PERF_PC_DS_PRIMITIVES = 28,
380
+	PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
381
+	PERF_PC_3D_DRAWCALLS = 30,
382
+	PERF_PC_2D_DRAWCALLS = 31,
383
+	PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
384
+	PERF_TESS_BUSY_CYCLES = 33,
385
+	PERF_TESS_WORKING_CYCLES = 34,
386
+	PERF_TESS_STALL_CYCLES_PC = 35,
387
+	PERF_TESS_STARVE_CYCLES_PC = 36,
388
+	PERF_PC_TSE_TRANSACTION = 37,
389
+	PERF_PC_TSE_VERTEX = 38,
390
+	PERF_PC_TESS_PC_UV_TRANS = 39,
391
+	PERF_PC_TESS_PC_UV_PATCHES = 40,
392
+	PERF_PC_TESS_FACTOR_TRANS = 41,
393
+};
394
+
395
+enum a6xx_vfd_perfcounter_select {
396
+	PERF_VFD_BUSY_CYCLES = 0,
397
+	PERF_VFD_STALL_CYCLES_UCHE = 1,
398
+	PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
399
+	PERF_VFD_STALL_CYCLES_SP_INFO = 3,
400
+	PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
401
+	PERF_VFD_STARVE_CYCLES_UCHE = 5,
402
+	PERF_VFD_RBUFFER_FULL = 6,
403
+	PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
404
+	PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
405
+	PERF_VFD_NUM_ATTRIBUTES = 9,
406
+	PERF_VFD_UPPER_SHADER_FIBERS = 10,
407
+	PERF_VFD_LOWER_SHADER_FIBERS = 11,
408
+	PERF_VFD_MODE_0_FIBERS = 12,
409
+	PERF_VFD_MODE_1_FIBERS = 13,
410
+	PERF_VFD_MODE_2_FIBERS = 14,
411
+	PERF_VFD_MODE_3_FIBERS = 15,
412
+	PERF_VFD_MODE_4_FIBERS = 16,
413
+	PERF_VFD_TOTAL_VERTICES = 17,
414
+	PERF_VFDP_STALL_CYCLES_VFD = 18,
415
+	PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
416
+	PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
417
+	PERF_VFDP_STARVE_CYCLES_PC = 21,
418
+	PERF_VFDP_VS_STAGE_WAVES = 22,
419
+};
420
+
421
+enum a6xx_hlsq_perfcounter_select {
422
+	PERF_HLSQ_BUSY_CYCLES = 0,
423
+	PERF_HLSQ_STALL_CYCLES_UCHE = 1,
424
+	PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
425
+	PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
426
+	PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
427
+	PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
428
+	PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
429
+	PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
430
+	PERF_HLSQ_QUADS = 8,
431
+	PERF_HLSQ_CS_INVOCATIONS = 9,
432
+	PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
433
+	PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
434
+	PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
435
+	PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
436
+	PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
437
+	PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
438
+	PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
439
+	PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
440
+	PERF_HLSQ_STALL_CYCLES_VPC = 18,
441
+	PERF_HLSQ_PIXELS = 19,
442
+	PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
443
+};
444
+
445
+enum a6xx_vpc_perfcounter_select {
446
+	PERF_VPC_BUSY_CYCLES = 0,
447
+	PERF_VPC_WORKING_CYCLES = 1,
448
+	PERF_VPC_STALL_CYCLES_UCHE = 2,
449
+	PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
450
+	PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
451
+	PERF_VPC_STALL_CYCLES_PC = 5,
452
+	PERF_VPC_STALL_CYCLES_SP_LM = 6,
453
+	PERF_VPC_STARVE_CYCLES_SP = 7,
454
+	PERF_VPC_STARVE_CYCLES_LRZ = 8,
455
+	PERF_VPC_PC_PRIMITIVES = 9,
456
+	PERF_VPC_SP_COMPONENTS = 10,
457
+	PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
458
+	PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
459
+	PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
460
+	PERF_VPC_LM_TRANSACTION = 14,
461
+	PERF_VPC_STREAMOUT_TRANSACTION = 15,
462
+	PERF_VPC_VS_BUSY_CYCLES = 16,
463
+	PERF_VPC_PS_BUSY_CYCLES = 17,
464
+	PERF_VPC_VS_WORKING_CYCLES = 18,
465
+	PERF_VPC_PS_WORKING_CYCLES = 19,
466
+	PERF_VPC_STARVE_CYCLES_RB = 20,
467
+	PERF_VPC_NUM_VPCRAM_READ_POS = 21,
468
+	PERF_VPC_WIT_FULL_CYCLES = 22,
469
+	PERF_VPC_VPCRAM_FULL_CYCLES = 23,
470
+	PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
471
+	PERF_VPC_NUM_VPCRAM_WRITE = 25,
472
+	PERF_VPC_NUM_VPCRAM_READ_SO = 26,
473
+	PERF_VPC_NUM_ATTR_REQ_LM = 27,
474
+};
475
+
476
+enum a6xx_tse_perfcounter_select {
477
+	PERF_TSE_BUSY_CYCLES = 0,
478
+	PERF_TSE_CLIPPING_CYCLES = 1,
479
+	PERF_TSE_STALL_CYCLES_RAS = 2,
480
+	PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
481
+	PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
482
+	PERF_TSE_STARVE_CYCLES_PC = 5,
483
+	PERF_TSE_INPUT_PRIM = 6,
484
+	PERF_TSE_INPUT_NULL_PRIM = 7,
485
+	PERF_TSE_TRIVAL_REJ_PRIM = 8,
486
+	PERF_TSE_CLIPPED_PRIM = 9,
487
+	PERF_TSE_ZERO_AREA_PRIM = 10,
488
+	PERF_TSE_FACENESS_CULLED_PRIM = 11,
489
+	PERF_TSE_ZERO_PIXEL_PRIM = 12,
490
+	PERF_TSE_OUTPUT_NULL_PRIM = 13,
491
+	PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
492
+	PERF_TSE_CINVOCATION = 15,
493
+	PERF_TSE_CPRIMITIVES = 16,
494
+	PERF_TSE_2D_INPUT_PRIM = 17,
495
+	PERF_TSE_2D_ALIVE_CYCLES = 18,
496
+	PERF_TSE_CLIP_PLANES = 19,
497
+};
498
+
499
+enum a6xx_ras_perfcounter_select {
500
+	PERF_RAS_BUSY_CYCLES = 0,
501
+	PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
502
+	PERF_RAS_STALL_CYCLES_LRZ = 2,
503
+	PERF_RAS_STARVE_CYCLES_TSE = 3,
504
+	PERF_RAS_SUPER_TILES = 4,
505
+	PERF_RAS_8X4_TILES = 5,
506
+	PERF_RAS_MASKGEN_ACTIVE = 6,
507
+	PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
508
+	PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
509
+	PERF_RAS_PRIM_KILLED_INVISILBE = 9,
510
+	PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
511
+	PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
512
+	PERF_RAS_BLOCKS = 12,
513
+};
514
+
515
+enum a6xx_uche_perfcounter_select {
516
+	PERF_UCHE_BUSY_CYCLES = 0,
517
+	PERF_UCHE_STALL_CYCLES_ARBITER = 1,
518
+	PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
519
+	PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
520
+	PERF_UCHE_VBIF_READ_BEATS_TP = 4,
521
+	PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
522
+	PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
523
+	PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
524
+	PERF_UCHE_VBIF_READ_BEATS_SP = 8,
525
+	PERF_UCHE_READ_REQUESTS_TP = 9,
526
+	PERF_UCHE_READ_REQUESTS_VFD = 10,
527
+	PERF_UCHE_READ_REQUESTS_HLSQ = 11,
528
+	PERF_UCHE_READ_REQUESTS_LRZ = 12,
529
+	PERF_UCHE_READ_REQUESTS_SP = 13,
530
+	PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
531
+	PERF_UCHE_WRITE_REQUESTS_SP = 15,
532
+	PERF_UCHE_WRITE_REQUESTS_VPC = 16,
533
+	PERF_UCHE_WRITE_REQUESTS_VSC = 17,
534
+	PERF_UCHE_EVICTS = 18,
535
+	PERF_UCHE_BANK_REQ0 = 19,
536
+	PERF_UCHE_BANK_REQ1 = 20,
537
+	PERF_UCHE_BANK_REQ2 = 21,
538
+	PERF_UCHE_BANK_REQ3 = 22,
539
+	PERF_UCHE_BANK_REQ4 = 23,
540
+	PERF_UCHE_BANK_REQ5 = 24,
541
+	PERF_UCHE_BANK_REQ6 = 25,
542
+	PERF_UCHE_BANK_REQ7 = 26,
543
+	PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
544
+	PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
545
+	PERF_UCHE_GMEM_READ_BEATS = 29,
546
+	PERF_UCHE_TPH_REF_FULL = 30,
547
+	PERF_UCHE_TPH_VICTIM_FULL = 31,
548
+	PERF_UCHE_TPH_EXT_FULL = 32,
549
+	PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
550
+	PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
551
+	PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
552
+	PERF_UCHE_VBIF_READ_BEATS_PC = 36,
553
+	PERF_UCHE_READ_REQUESTS_PC = 37,
554
+	PERF_UCHE_RAM_READ_REQ = 38,
555
+	PERF_UCHE_RAM_WRITE_REQ = 39,
556
+};
557
+
558
+enum a6xx_tp_perfcounter_select {
559
+	PERF_TP_BUSY_CYCLES = 0,
560
+	PERF_TP_STALL_CYCLES_UCHE = 1,
561
+	PERF_TP_LATENCY_CYCLES = 2,
562
+	PERF_TP_LATENCY_TRANS = 3,
563
+	PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
564
+	PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
565
+	PERF_TP_L1_CACHELINE_REQUESTS = 6,
566
+	PERF_TP_L1_CACHELINE_MISSES = 7,
567
+	PERF_TP_SP_TP_TRANS = 8,
568
+	PERF_TP_TP_SP_TRANS = 9,
569
+	PERF_TP_OUTPUT_PIXELS = 10,
570
+	PERF_TP_FILTER_WORKLOAD_16BIT = 11,
571
+	PERF_TP_FILTER_WORKLOAD_32BIT = 12,
572
+	PERF_TP_QUADS_RECEIVED = 13,
573
+	PERF_TP_QUADS_OFFSET = 14,
574
+	PERF_TP_QUADS_SHADOW = 15,
575
+	PERF_TP_QUADS_ARRAY = 16,
576
+	PERF_TP_QUADS_GRADIENT = 17,
577
+	PERF_TP_QUADS_1D = 18,
578
+	PERF_TP_QUADS_2D = 19,
579
+	PERF_TP_QUADS_BUFFER = 20,
580
+	PERF_TP_QUADS_3D = 21,
581
+	PERF_TP_QUADS_CUBE = 22,
582
+	PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
583
+	PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
584
+	PERF_TP_OUTPUT_PIXELS_POINT = 25,
585
+	PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
586
+	PERF_TP_OUTPUT_PIXELS_MIP = 27,
587
+	PERF_TP_OUTPUT_PIXELS_ANISO = 28,
588
+	PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
589
+	PERF_TP_FLAG_CACHE_REQUESTS = 30,
590
+	PERF_TP_FLAG_CACHE_MISSES = 31,
591
+	PERF_TP_L1_5_L2_REQUESTS = 32,
592
+	PERF_TP_2D_OUTPUT_PIXELS = 33,
593
+	PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
594
+	PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
595
+	PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
596
+	PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
597
+	PERF_TP_TPA2TPC_TRANS = 38,
598
+	PERF_TP_L1_MISSES_ASTC_1TILE = 39,
599
+	PERF_TP_L1_MISSES_ASTC_2TILE = 40,
600
+	PERF_TP_L1_MISSES_ASTC_4TILE = 41,
601
+	PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
602
+	PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
603
+	PERF_TP_L1_BANK_CONFLICT = 44,
604
+	PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
605
+	PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
606
+	PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
607
+	PERF_TP_FRONTEND_WORKING_CYCLES = 48,
608
+	PERF_TP_L1_TAG_WORKING_CYCLES = 49,
609
+	PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
610
+	PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
611
+	PERF_TP_BACKEND_WORKING_CYCLES = 52,
612
+	PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
613
+	PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
614
+	PERF_TP_STARVE_CYCLES_SP = 55,
615
+	PERF_TP_STARVE_CYCLES_UCHE = 56,
616
+};
617
+
618
+enum a6xx_sp_perfcounter_select {
619
+	PERF_SP_BUSY_CYCLES = 0,
620
+	PERF_SP_ALU_WORKING_CYCLES = 1,
621
+	PERF_SP_EFU_WORKING_CYCLES = 2,
622
+	PERF_SP_STALL_CYCLES_VPC = 3,
623
+	PERF_SP_STALL_CYCLES_TP = 4,
624
+	PERF_SP_STALL_CYCLES_UCHE = 5,
625
+	PERF_SP_STALL_CYCLES_RB = 6,
626
+	PERF_SP_NON_EXECUTION_CYCLES = 7,
627
+	PERF_SP_WAVE_CONTEXTS = 8,
628
+	PERF_SP_WAVE_CONTEXT_CYCLES = 9,
629
+	PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
630
+	PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
631
+	PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
632
+	PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
633
+	PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
634
+	PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
635
+	PERF_SP_WAVE_CTRL_CYCLES = 16,
636
+	PERF_SP_WAVE_LOAD_CYCLES = 17,
637
+	PERF_SP_WAVE_EMIT_CYCLES = 18,
638
+	PERF_SP_WAVE_NOP_CYCLES = 19,
639
+	PERF_SP_WAVE_WAIT_CYCLES = 20,
640
+	PERF_SP_WAVE_FETCH_CYCLES = 21,
641
+	PERF_SP_WAVE_IDLE_CYCLES = 22,
642
+	PERF_SP_WAVE_END_CYCLES = 23,
643
+	PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
644
+	PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
645
+	PERF_SP_WAVE_JOIN_CYCLES = 26,
646
+	PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
647
+	PERF_SP_LM_STORE_INSTRUCTIONS = 28,
648
+	PERF_SP_LM_ATOMICS = 29,
649
+	PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
650
+	PERF_SP_GM_STORE_INSTRUCTIONS = 31,
651
+	PERF_SP_GM_ATOMICS = 32,
652
+	PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
653
+	PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
654
+	PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
655
+	PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
656
+	PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
657
+	PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
658
+	PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
659
+	PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
660
+	PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
661
+	PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
662
+	PERF_SP_VS_INSTRUCTIONS = 43,
663
+	PERF_SP_FS_INSTRUCTIONS = 44,
664
+	PERF_SP_ADDR_LOCK_COUNT = 45,
665
+	PERF_SP_UCHE_READ_TRANS = 46,
666
+	PERF_SP_UCHE_WRITE_TRANS = 47,
667
+	PERF_SP_EXPORT_VPC_TRANS = 48,
668
+	PERF_SP_EXPORT_RB_TRANS = 49,
669
+	PERF_SP_PIXELS_KILLED = 50,
670
+	PERF_SP_ICL1_REQUESTS = 51,
671
+	PERF_SP_ICL1_MISSES = 52,
672
+	PERF_SP_HS_INSTRUCTIONS = 53,
673
+	PERF_SP_DS_INSTRUCTIONS = 54,
674
+	PERF_SP_GS_INSTRUCTIONS = 55,
675
+	PERF_SP_CS_INSTRUCTIONS = 56,
676
+	PERF_SP_GPR_READ = 57,
677
+	PERF_SP_GPR_WRITE = 58,
678
+	PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
679
+	PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
680
+	PERF_SP_LM_BANK_CONFLICTS = 61,
681
+	PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
682
+	PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
683
+	PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
684
+	PERF_SP_LM_WORKING_CYCLES = 65,
685
+	PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
686
+	PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
687
+	PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
688
+	PERF_SP_STARVE_CYCLES_HLSQ = 69,
689
+	PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
690
+	PERF_SP_WORKING_EU = 71,
691
+	PERF_SP_ANY_EU_WORKING = 72,
692
+	PERF_SP_WORKING_EU_FS_STAGE = 73,
693
+	PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
694
+	PERF_SP_WORKING_EU_VS_STAGE = 75,
695
+	PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
696
+	PERF_SP_WORKING_EU_CS_STAGE = 77,
697
+	PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
698
+	PERF_SP_GPR_READ_PREFETCH = 79,
699
+	PERF_SP_GPR_READ_CONFLICT = 80,
700
+	PERF_SP_GPR_WRITE_CONFLICT = 81,
701
+	PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
702
+	PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
703
+	PERF_SP_EXECUTABLE_WAVES = 84,
704
+};
705
+
706
+enum a6xx_rb_perfcounter_select {
707
+	PERF_RB_BUSY_CYCLES = 0,
708
+	PERF_RB_STALL_CYCLES_HLSQ = 1,
709
+	PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
710
+	PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
711
+	PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
712
+	PERF_RB_STARVE_CYCLES_SP = 5,
713
+	PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
714
+	PERF_RB_STARVE_CYCLES_CCU = 7,
715
+	PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
716
+	PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
717
+	PERF_RB_Z_WORKLOAD = 10,
718
+	PERF_RB_HLSQ_ACTIVE = 11,
719
+	PERF_RB_Z_READ = 12,
720
+	PERF_RB_Z_WRITE = 13,
721
+	PERF_RB_C_READ = 14,
722
+	PERF_RB_C_WRITE = 15,
723
+	PERF_RB_TOTAL_PASS = 16,
724
+	PERF_RB_Z_PASS = 17,
725
+	PERF_RB_Z_FAIL = 18,
726
+	PERF_RB_S_FAIL = 19,
727
+	PERF_RB_BLENDED_FXP_COMPONENTS = 20,
728
+	PERF_RB_BLENDED_FP16_COMPONENTS = 21,
729
+	PERF_RB_PS_INVOCATIONS = 22,
730
+	PERF_RB_2D_ALIVE_CYCLES = 23,
731
+	PERF_RB_2D_STALL_CYCLES_A2D = 24,
732
+	PERF_RB_2D_STARVE_CYCLES_SRC = 25,
733
+	PERF_RB_2D_STARVE_CYCLES_SP = 26,
734
+	PERF_RB_2D_STARVE_CYCLES_DST = 27,
735
+	PERF_RB_2D_VALID_PIXELS = 28,
736
+	PERF_RB_3D_PIXELS = 29,
737
+	PERF_RB_BLENDER_WORKING_CYCLES = 30,
738
+	PERF_RB_ZPROC_WORKING_CYCLES = 31,
739
+	PERF_RB_CPROC_WORKING_CYCLES = 32,
740
+	PERF_RB_SAMPLER_WORKING_CYCLES = 33,
741
+	PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
742
+	PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
743
+	PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
744
+	PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
745
+	PERF_RB_STALL_CYCLES_VPC = 38,
746
+	PERF_RB_2D_INPUT_TRANS = 39,
747
+	PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
748
+	PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
749
+	PERF_RB_BLENDED_FP32_COMPONENTS = 42,
750
+	PERF_RB_COLOR_PIX_TILES = 43,
751
+	PERF_RB_STALL_CYCLES_CCU = 44,
752
+	PERF_RB_EARLY_Z_ARB3_GRANT = 45,
753
+	PERF_RB_LATE_Z_ARB3_GRANT = 46,
754
+	PERF_RB_EARLY_Z_SKIP_GRANT = 47,
755
+};
756
+
757
+enum a6xx_vsc_perfcounter_select {
758
+	PERF_VSC_BUSY_CYCLES = 0,
759
+	PERF_VSC_WORKING_CYCLES = 1,
760
+	PERF_VSC_STALL_CYCLES_UCHE = 2,
761
+	PERF_VSC_EOT_NUM = 3,
762
+	PERF_VSC_INPUT_TILES = 4,
763
+};
764
+
765
+enum a6xx_ccu_perfcounter_select {
766
+	PERF_CCU_BUSY_CYCLES = 0,
767
+	PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
768
+	PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
769
+	PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
770
+	PERF_CCU_DEPTH_BLOCKS = 4,
771
+	PERF_CCU_COLOR_BLOCKS = 5,
772
+	PERF_CCU_DEPTH_BLOCK_HIT = 6,
773
+	PERF_CCU_COLOR_BLOCK_HIT = 7,
774
+	PERF_CCU_PARTIAL_BLOCK_READ = 8,
775
+	PERF_CCU_GMEM_READ = 9,
776
+	PERF_CCU_GMEM_WRITE = 10,
777
+	PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
778
+	PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
779
+	PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
780
+	PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
781
+	PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
782
+	PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
783
+	PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
784
+	PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
785
+	PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
786
+	PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
787
+	PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
788
+	PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
789
+	PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
790
+	PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
791
+	PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
792
+	PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
793
+	PERF_CCU_2D_RD_REQ = 27,
794
+	PERF_CCU_2D_WR_REQ = 28,
795
+};
796
+
797
+enum a6xx_lrz_perfcounter_select {
798
+	PERF_LRZ_BUSY_CYCLES = 0,
799
+	PERF_LRZ_STARVE_CYCLES_RAS = 1,
800
+	PERF_LRZ_STALL_CYCLES_RB = 2,
801
+	PERF_LRZ_STALL_CYCLES_VSC = 3,
802
+	PERF_LRZ_STALL_CYCLES_VPC = 4,
803
+	PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
804
+	PERF_LRZ_STALL_CYCLES_UCHE = 6,
805
+	PERF_LRZ_LRZ_READ = 7,
806
+	PERF_LRZ_LRZ_WRITE = 8,
807
+	PERF_LRZ_READ_LATENCY = 9,
808
+	PERF_LRZ_MERGE_CACHE_UPDATING = 10,
809
+	PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
810
+	PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
811
+	PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
812
+	PERF_LRZ_FULL_8X8_TILES = 14,
813
+	PERF_LRZ_PARTIAL_8X8_TILES = 15,
814
+	PERF_LRZ_TILE_KILLED = 16,
815
+	PERF_LRZ_TOTAL_PIXEL = 17,
816
+	PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
817
+	PERF_LRZ_FULLY_COVERED_TILES = 19,
818
+	PERF_LRZ_PARTIAL_COVERED_TILES = 20,
819
+	PERF_LRZ_FEEDBACK_ACCEPT = 21,
820
+	PERF_LRZ_FEEDBACK_DISCARD = 22,
821
+	PERF_LRZ_FEEDBACK_STALL = 23,
822
+	PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
823
+	PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
824
+	PERF_LRZ_STALL_CYCLES_VC = 26,
825
+	PERF_LRZ_RAS_MASK_TRANS = 27,
826
+};
827
+
828
+enum a6xx_cmp_perfcounter_select {
829
+	PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
830
+	PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
831
+	PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
832
+	PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
833
+	PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
834
+	PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
835
+	PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
836
+	PERF_CMPDECMP_VBIF_READ_DATA = 7,
837
+	PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
838
+	PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
839
+	PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
840
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
841
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
842
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
843
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
844
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
845
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
846
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
847
+	PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
848
+	PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
849
+	PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
850
+	PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
851
+	PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
852
+	PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
853
+	PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
854
+	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
855
+	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
856
+	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
857
+	PERF_CMPDECMP_2D_RD_DATA = 28,
858
+	PERF_CMPDECMP_2D_WR_DATA = 29,
859
+	PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
860
+	PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
861
+	PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
862
+	PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
863
+	PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
864
+	PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
865
+	PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
866
+	PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
867
+	PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
868
+	PERF_CMPDECMP_2D_PIXELS = 39,
869
+};
870
+
871
+enum a6xx_2d_ifmt {
872
+	R2D_UNORM8 = 16,
873
+	R2D_INT32 = 7,
874
+	R2D_INT16 = 6,
875
+	R2D_INT8 = 5,
876
+	R2D_FLOAT32 = 4,
877
+	R2D_FLOAT16 = 3,
878
+	R2D_UNORM8_SRGB = 1,
879
+	R2D_RAW = 0,
880
+};
881
+
882
+enum a6xx_ztest_mode {
883
+	A6XX_EARLY_Z = 0,
884
+	A6XX_LATE_Z = 1,
885
+	A6XX_EARLY_LRZ_LATE_Z = 2,
886
+};
887
+
888
+enum a6xx_rotation {
889
+	ROTATE_0 = 0,
890
+	ROTATE_90 = 1,
891
+	ROTATE_180 = 2,
892
+	ROTATE_270 = 3,
893
+	ROTATE_HFLIP = 4,
894
+	ROTATE_VFLIP = 5,
895
+};
896
+
897
+enum a6xx_tess_spacing {
898
+	TESS_EQUAL = 0,
899
+	TESS_FRACTIONAL_ODD = 2,
900
+	TESS_FRACTIONAL_EVEN = 3,
901
+};
902
+
903
+enum a6xx_tess_output {
904
+	TESS_POINTS = 0,
905
+	TESS_LINES = 1,
906
+	TESS_CW_TRIS = 2,
907
+	TESS_CCW_TRIS = 3,
273908 };
274909 
275910 enum a6xx_tex_filter {
276911 	A6XX_TEX_NEAREST = 0,
277912 	A6XX_TEX_LINEAR = 1,
278913 	A6XX_TEX_ANISO = 2,
914
+	A6XX_TEX_CUBIC = 3,
279915 };
280916 
281917 enum a6xx_tex_clamp {
....@@ -292,6 +928,12 @@
292928 	A6XX_TEX_ANISO_4 = 2,
293929 	A6XX_TEX_ANISO_8 = 3,
294930 	A6XX_TEX_ANISO_16 = 4,
931
+};
932
+
933
+enum a6xx_reduction_mode {
934
+	A6XX_REDUCTION_MODE_AVERAGE = 0,
935
+	A6XX_REDUCTION_MODE_MIN = 1,
936
+	A6XX_REDUCTION_MODE_MAX = 2,
295937 };
296938 
297939 enum a6xx_tex_swiz {
....@@ -356,6 +998,9 @@
356998 
357999 #define REG_A6XX_CP_SQE_CNTL					0x00000808
3581000 
1001
+#define REG_A6XX_CP_CP2GMU_STATUS				0x00000812
1002
+#define A6XX_CP_CP2GMU_STATUS_IFPC				0x00000001
1003
+
3591004 #define REG_A6XX_CP_HW_FAULT					0x00000821
3601005 
3611006 #define REG_A6XX_CP_INTERRUPT_STATUS				0x00000823
....@@ -368,9 +1013,47 @@
3681013 
3691014 #define REG_A6XX_CP_MISC_CNTL					0x00000840
3701015 
1016
+#define REG_A6XX_CP_APRIV_CNTL					0x00000844
1017
+
3711018 #define REG_A6XX_CP_ROQ_THRESHOLDS_1				0x000008c1
1019
+#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK			0x000000ff
1020
+#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT			0
1021
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
1022
+{
1023
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
1024
+}
1025
+#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK			0x0000ff00
1026
+#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT			8
1027
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
1028
+{
1029
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
1030
+}
1031
+#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK		0x00ff0000
1032
+#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT		16
1033
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1034
+{
1035
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1036
+}
1037
+#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK		0xff000000
1038
+#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT		24
1039
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1040
+{
1041
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1042
+}
3721043 
3731044 #define REG_A6XX_CP_ROQ_THRESHOLDS_2				0x000008c2
1045
+#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK		0x000001ff
1046
+#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT		0
1047
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1048
+{
1049
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1050
+}
1051
+#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK			0xffff0000
1052
+#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT		16
1053
+static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1054
+{
1055
+	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1056
+}
3741057 
3751058 #define REG_A6XX_CP_MEM_POOL_SIZE				0x000008c3
3761059 
....@@ -489,6 +1172,36 @@
4891172 
4901173 #define REG_A6XX_CP_IB2_REM_SIZE				0x0000092d
4911174 
1175
+#define REG_A6XX_CP_SDS_BASE					0x0000092e
1176
+
1177
+#define REG_A6XX_CP_SDS_BASE_HI					0x0000092f
1178
+
1179
+#define REG_A6XX_CP_SDS_REM_SIZE				0x0000092e
1180
+
1181
+#define REG_A6XX_CP_BIN_SIZE_ADDRESS				0x00000931
1182
+
1183
+#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI				0x00000932
1184
+
1185
+#define REG_A6XX_CP_BIN_DATA_ADDR				0x00000934
1186
+
1187
+#define REG_A6XX_CP_BIN_DATA_ADDR_HI				0x00000935
1188
+
1189
+#define REG_A6XX_CP_CSQ_IB1_STAT				0x00000949
1190
+#define A6XX_CP_CSQ_IB1_STAT_REM__MASK				0xffff0000
1191
+#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT				16
1192
+static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1193
+{
1194
+	return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1195
+}
1196
+
1197
+#define REG_A6XX_CP_CSQ_IB2_STAT				0x0000094a
1198
+#define A6XX_CP_CSQ_IB2_STAT_REM__MASK				0xffff0000
1199
+#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT				16
1200
+static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1201
+{
1202
+	return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1203
+}
1204
+
4921205 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO			0x00000980
4931206 
4941207 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI			0x00000981
....@@ -530,6 +1243,7 @@
5301243 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER			0x00000001
5311244 
5321245 #define REG_A6XX_RBBM_STATUS3					0x00000213
1246
+#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
5331247 
5341248 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS			0x00000215
5351249 
....@@ -734,18 +1448,6 @@
7341448 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI				0x00000463
7351449 
7361450 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO				0x00000464
737
-
738
-#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI				0x00000465
739
-
740
-#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO				0x00000466
741
-
742
-#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI				0x00000467
743
-
744
-#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO				0x00000468
745
-
746
-#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI				0x00000469
747
-
748
-#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO				0x0000046a
7491451 
7501452 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI				0x00000465
7511453 
....@@ -1071,6 +1773,50 @@
10711773 
10721774 #define REG_A6XX_RBBM_ISDB_CNT					0x00000533
10731775 
1776
+#define REG_A6XX_RBBM_PRIMCTR_0_LO				0x00000540
1777
+
1778
+#define REG_A6XX_RBBM_PRIMCTR_0_HI				0x00000541
1779
+
1780
+#define REG_A6XX_RBBM_PRIMCTR_1_LO				0x00000542
1781
+
1782
+#define REG_A6XX_RBBM_PRIMCTR_1_HI				0x00000543
1783
+
1784
+#define REG_A6XX_RBBM_PRIMCTR_2_LO				0x00000544
1785
+
1786
+#define REG_A6XX_RBBM_PRIMCTR_2_HI				0x00000545
1787
+
1788
+#define REG_A6XX_RBBM_PRIMCTR_3_LO				0x00000546
1789
+
1790
+#define REG_A6XX_RBBM_PRIMCTR_3_HI				0x00000547
1791
+
1792
+#define REG_A6XX_RBBM_PRIMCTR_4_LO				0x00000548
1793
+
1794
+#define REG_A6XX_RBBM_PRIMCTR_4_HI				0x00000549
1795
+
1796
+#define REG_A6XX_RBBM_PRIMCTR_5_LO				0x0000054a
1797
+
1798
+#define REG_A6XX_RBBM_PRIMCTR_5_HI				0x0000054b
1799
+
1800
+#define REG_A6XX_RBBM_PRIMCTR_6_LO				0x0000054c
1801
+
1802
+#define REG_A6XX_RBBM_PRIMCTR_6_HI				0x0000054d
1803
+
1804
+#define REG_A6XX_RBBM_PRIMCTR_7_LO				0x0000054e
1805
+
1806
+#define REG_A6XX_RBBM_PRIMCTR_7_HI				0x0000054f
1807
+
1808
+#define REG_A6XX_RBBM_PRIMCTR_8_LO				0x00000550
1809
+
1810
+#define REG_A6XX_RBBM_PRIMCTR_8_HI				0x00000551
1811
+
1812
+#define REG_A6XX_RBBM_PRIMCTR_9_LO				0x00000552
1813
+
1814
+#define REG_A6XX_RBBM_PRIMCTR_9_HI				0x00000553
1815
+
1816
+#define REG_A6XX_RBBM_PRIMCTR_10_LO				0x00000554
1817
+
1818
+#define REG_A6XX_RBBM_PRIMCTR_10_HI				0x00000555
1819
+
10741820 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
10751821 
10761822 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800
....@@ -1084,6 +1830,11 @@
10841830 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
10851831 
10861832 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL			0x00000010
1833
+
1834
+#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL			0x00000011
1835
+
1836
+#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD			0x0000001c
1837
+#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE		0x00000001
10871838 
10881839 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000001f
10891840 
....@@ -1313,6 +2064,14 @@
13132064 
13142065 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ				0x0000011c
13152066 
2067
+#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ				0x0000011d
2068
+
2069
+#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE			0x00000120
2070
+
2071
+#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE			0x00000121
2072
+
2073
+#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE			0x00000122
2074
+
13162075 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A				0x00000600
13172076 
13182077 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B				0x00000601
....@@ -1485,94 +2244,6 @@
14852244 
14862245 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1				0x00000cd9
14872246 
1488
-#define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601
1489
-
1490
-#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0				0x00008610
1491
-
1492
-#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1				0x00008611
1493
-
1494
-#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2				0x00008612
1495
-
1496
-#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3				0x00008613
1497
-
1498
-#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0				0x00008614
1499
-
1500
-#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1				0x00008615
1501
-
1502
-#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2				0x00008616
1503
-
1504
-#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3				0x00008617
1505
-
1506
-#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0				0x00008618
1507
-
1508
-#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1				0x00008619
1509
-
1510
-#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2				0x0000861a
1511
-
1512
-#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3				0x0000861b
1513
-
1514
-#define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05
1515
-
1516
-#define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
1517
-
1518
-#define REG_A6XX_RB_PERFCTR_RB_SEL_0				0x00008e10
1519
-
1520
-#define REG_A6XX_RB_PERFCTR_RB_SEL_1				0x00008e11
1521
-
1522
-#define REG_A6XX_RB_PERFCTR_RB_SEL_2				0x00008e12
1523
-
1524
-#define REG_A6XX_RB_PERFCTR_RB_SEL_3				0x00008e13
1525
-
1526
-#define REG_A6XX_RB_PERFCTR_RB_SEL_4				0x00008e14
1527
-
1528
-#define REG_A6XX_RB_PERFCTR_RB_SEL_5				0x00008e15
1529
-
1530
-#define REG_A6XX_RB_PERFCTR_RB_SEL_6				0x00008e16
1531
-
1532
-#define REG_A6XX_RB_PERFCTR_RB_SEL_7				0x00008e17
1533
-
1534
-#define REG_A6XX_RB_PERFCTR_CCU_SEL_0				0x00008e18
1535
-
1536
-#define REG_A6XX_RB_PERFCTR_CCU_SEL_1				0x00008e19
1537
-
1538
-#define REG_A6XX_RB_PERFCTR_CCU_SEL_2				0x00008e1a
1539
-
1540
-#define REG_A6XX_RB_PERFCTR_CCU_SEL_3				0x00008e1b
1541
-
1542
-#define REG_A6XX_RB_PERFCTR_CCU_SEL_4				0x00008e1c
1543
-
1544
-#define REG_A6XX_RB_PERFCTR_CMP_SEL_0				0x00008e2c
1545
-
1546
-#define REG_A6XX_RB_PERFCTR_CMP_SEL_1				0x00008e2d
1547
-
1548
-#define REG_A6XX_RB_PERFCTR_CMP_SEL_2				0x00008e2e
1549
-
1550
-#define REG_A6XX_RB_PERFCTR_CMP_SEL_3				0x00008e2f
1551
-
1552
-#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d
1553
-
1554
-#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50
1555
-
1556
-#define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00
1557
-
1558
-#define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01
1559
-
1560
-#define REG_A6XX_PC_PERFCTR_PC_SEL_0				0x00009e34
1561
-
1562
-#define REG_A6XX_PC_PERFCTR_PC_SEL_1				0x00009e35
1563
-
1564
-#define REG_A6XX_PC_PERFCTR_PC_SEL_2				0x00009e36
1565
-
1566
-#define REG_A6XX_PC_PERFCTR_PC_SEL_3				0x00009e37
1567
-
1568
-#define REG_A6XX_PC_PERFCTR_PC_SEL_4				0x00009e38
1569
-
1570
-#define REG_A6XX_PC_PERFCTR_PC_SEL_5				0x00009e39
1571
-
1572
-#define REG_A6XX_PC_PERFCTR_PC_SEL_6				0x00009e3a
1573
-
1574
-#define REG_A6XX_PC_PERFCTR_PC_SEL_7				0x00009e3b
1575
-
15762247 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL				0x0000be05
15772248 
15782249 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x0000be10
....@@ -1608,20 +2279,6 @@
16082279 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6				0x0000a616
16092280 
16102281 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7				0x0000a617
1611
-
1612
-#define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601
1613
-
1614
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0				0x00009604
1615
-
1616
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1				0x00009605
1617
-
1618
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2				0x00009606
1619
-
1620
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3				0x00009607
1621
-
1622
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4				0x00009608
1623
-
1624
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5				0x00009609
16252282 
16262283 #define REG_A6XX_UCHE_ADDR_MODE_CNTL				0x00000e00
16272284 
....@@ -1739,6 +2396,16 @@
17392396 
17402397 #define REG_A6XX_TPL1_NC_MODE_CNTL				0x0000b604
17412398 
2399
+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0			0x0000b608
2400
+
2401
+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1			0x0000b609
2402
+
2403
+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2			0x0000b60a
2404
+
2405
+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3			0x0000b60b
2406
+
2407
+#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4			0x0000b60c
2408
+
17422409 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0				0x0000b610
17432410 
17442411 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1				0x0000b611
....@@ -1765,11 +2432,38 @@
17652432 
17662433 #define REG_A6XX_VBIF_VERSION					0x00003000
17672434 
2435
+#define REG_A6XX_VBIF_CLKON					0x00003001
2436
+#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000002
2437
+
17682438 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
17692439 
17702440 #define REG_A6XX_VBIF_XIN_HALT_CTRL0				0x00003080
17712441 
17722442 #define REG_A6XX_VBIF_XIN_HALT_CTRL1				0x00003081
2443
+
2444
+#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
2445
+
2446
+#define REG_A6XX_VBIF_TEST_BUS1_CTRL0				0x00003085
2447
+
2448
+#define REG_A6XX_VBIF_TEST_BUS1_CTRL1				0x00003086
2449
+#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK		0x0000000f
2450
+#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT		0
2451
+static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2452
+{
2453
+	return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2454
+}
2455
+
2456
+#define REG_A6XX_VBIF_TEST_BUS2_CTRL0				0x00003087
2457
+
2458
+#define REG_A6XX_VBIF_TEST_BUS2_CTRL1				0x00003088
2459
+#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK		0x000001ff
2460
+#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT		0
2461
+static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2462
+{
2463
+	return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2464
+}
2465
+
2466
+#define REG_A6XX_VBIF_TEST_BUS_OUT				0x0000308c
17732467 
17742468 #define REG_A6XX_VBIF_PERF_CNT_SEL0				0x000030d0
17752469 
....@@ -1813,313 +2507,82 @@
18132507 
18142508 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
18152509 
1816
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00018400
2510
+#define REG_A6XX_GBIF_SCACHE_CNTL1				0x00003c02
18172511 
1818
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00018401
2512
+#define REG_A6XX_GBIF_QSB_SIDE0					0x00003c03
18192513 
1820
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00018402
2514
+#define REG_A6XX_GBIF_QSB_SIDE1					0x00003c04
18212515 
1822
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00018403
1823
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK		0x000000ff
1824
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT		0
1825
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
2516
+#define REG_A6XX_GBIF_QSB_SIDE2					0x00003c05
2517
+
2518
+#define REG_A6XX_GBIF_QSB_SIDE3					0x00003c06
2519
+
2520
+#define REG_A6XX_GBIF_HALT					0x00003c45
2521
+
2522
+#define REG_A6XX_GBIF_HALT_ACK					0x00003c46
2523
+
2524
+#define REG_A6XX_GBIF_PERF_PWR_CNT_EN				0x00003cc0
2525
+
2526
+#define REG_A6XX_GBIF_PERF_CNT_SEL				0x00003cc2
2527
+
2528
+#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL				0x00003cc3
2529
+
2530
+#define REG_A6XX_GBIF_PERF_CNT_LOW0				0x00003cc4
2531
+
2532
+#define REG_A6XX_GBIF_PERF_CNT_LOW1				0x00003cc5
2533
+
2534
+#define REG_A6XX_GBIF_PERF_CNT_LOW2				0x00003cc6
2535
+
2536
+#define REG_A6XX_GBIF_PERF_CNT_LOW3				0x00003cc7
2537
+
2538
+#define REG_A6XX_GBIF_PERF_CNT_HIGH0				0x00003cc8
2539
+
2540
+#define REG_A6XX_GBIF_PERF_CNT_HIGH1				0x00003cc9
2541
+
2542
+#define REG_A6XX_GBIF_PERF_CNT_HIGH2				0x00003cca
2543
+
2544
+#define REG_A6XX_GBIF_PERF_CNT_HIGH3				0x00003ccb
2545
+
2546
+#define REG_A6XX_GBIF_PWR_CNT_LOW0				0x00003ccc
2547
+
2548
+#define REG_A6XX_GBIF_PWR_CNT_LOW1				0x00003ccd
2549
+
2550
+#define REG_A6XX_GBIF_PWR_CNT_LOW2				0x00003cce
2551
+
2552
+#define REG_A6XX_GBIF_PWR_CNT_HIGH0				0x00003ccf
2553
+
2554
+#define REG_A6XX_GBIF_PWR_CNT_HIGH1				0x00003cd0
2555
+
2556
+#define REG_A6XX_GBIF_PWR_CNT_HIGH2				0x00003cd1
2557
+
2558
+#define REG_A6XX_SP_WINDOW_OFFSET				0x0000b4d1
2559
+#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2560
+#define A6XX_SP_WINDOW_OFFSET_X__MASK				0x00007fff
2561
+#define A6XX_SP_WINDOW_OFFSET_X__SHIFT				0
2562
+static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
18262563 {
1827
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
2564
+	return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
18282565 }
1829
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK	0x0000ff00
1830
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT	8
1831
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
2566
+#define A6XX_SP_WINDOW_OFFSET_Y__MASK				0x7fff0000
2567
+#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT				16
2568
+static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
18322569 {
1833
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
2570
+	return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
18342571 }
18352572 
1836
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00018404
1837
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
1838
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
1839
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
2573
+#define REG_A6XX_SP_TP_WINDOW_OFFSET				0x0000b307
2574
+#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2575
+#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK			0x00007fff
2576
+#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT			0
2577
+static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
18402578 {
1841
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
2579
+	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
18422580 }
1843
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
1844
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT		12
1845
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
2581
+#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK			0x7fff0000
2582
+#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT			16
2583
+static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
18462584 {
1847
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1848
-}
1849
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
1850
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT		28
1851
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1852
-{
1853
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1854
-}
1855
-
1856
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00018405
1857
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
1858
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT		24
1859
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1860
-{
1861
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1862
-}
1863
-
1864
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00018408
1865
-
1866
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00018409
1867
-
1868
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0001840a
1869
-
1870
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0001840b
1871
-
1872
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0001840c
1873
-
1874
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0001840d
1875
-
1876
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0001840e
1877
-
1878
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0001840f
1879
-
1880
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00018410
1881
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
1882
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
1883
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1884
-{
1885
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1886
-}
1887
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
1888
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT		4
1889
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1890
-{
1891
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1892
-}
1893
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
1894
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT		8
1895
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1896
-{
1897
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1898
-}
1899
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
1900
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT		12
1901
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1902
-{
1903
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1904
-}
1905
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
1906
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT		16
1907
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1908
-{
1909
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1910
-}
1911
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
1912
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT		20
1913
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1914
-{
1915
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1916
-}
1917
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
1918
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT		24
1919
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1920
-{
1921
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1922
-}
1923
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
1924
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT		28
1925
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1926
-{
1927
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1928
-}
1929
-
1930
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00018411
1931
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
1932
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
1933
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1934
-{
1935
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1936
-}
1937
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
1938
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT		4
1939
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1940
-{
1941
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1942
-}
1943
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
1944
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT		8
1945
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1946
-{
1947
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1948
-}
1949
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
1950
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT		12
1951
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1952
-{
1953
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1954
-}
1955
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
1956
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT		16
1957
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1958
-{
1959
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1960
-}
1961
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
1962
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT		20
1963
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1964
-{
1965
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1966
-}
1967
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
1968
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT		24
1969
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1970
-{
1971
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1972
-}
1973
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
1974
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT		28
1975
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1976
-{
1977
-	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1978
-}
1979
-
1980
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0001842f
1981
-
1982
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00018430
1983
-
1984
-#define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00021140
1985
-
1986
-#define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00021148
1987
-
1988
-#define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00021540
1989
-
1990
-#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00021541
1991
-
1992
-#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00021542
1993
-
1994
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00021543
1995
-
1996
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00021544
1997
-
1998
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00021545
1999
-
2000
-#define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00021572
2001
-
2002
-#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00021573
2003
-
2004
-#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00021574
2005
-
2006
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00021575
2007
-
2008
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00021576
2009
-
2010
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00021577
2011
-
2012
-#define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000215a4
2013
-
2014
-#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000215a5
2015
-
2016
-#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000215a6
2017
-
2018
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000215a7
2019
-
2020
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000215a8
2021
-
2022
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000215a9
2023
-
2024
-#define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000215d6
2025
-
2026
-#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000215d7
2027
-
2028
-#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000215d8
2029
-
2030
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000215d9
2031
-
2032
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000215da
2033
-
2034
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000215db
2035
-
2036
-#define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x000a0000
2037
-
2038
-#define REG_A6XX_X1_WINDOW_OFFSET				0x000088d4
2039
-#define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2040
-#define A6XX_X1_WINDOW_OFFSET_X__MASK				0x00007fff
2041
-#define A6XX_X1_WINDOW_OFFSET_X__SHIFT				0
2042
-static inline uint32_t A6XX_X1_WINDOW_OFFSET_X(uint32_t val)
2043
-{
2044
-	return ((val) << A6XX_X1_WINDOW_OFFSET_X__SHIFT) & A6XX_X1_WINDOW_OFFSET_X__MASK;
2045
-}
2046
-#define A6XX_X1_WINDOW_OFFSET_Y__MASK				0x7fff0000
2047
-#define A6XX_X1_WINDOW_OFFSET_Y__SHIFT				16
2048
-static inline uint32_t A6XX_X1_WINDOW_OFFSET_Y(uint32_t val)
2049
-{
2050
-	return ((val) << A6XX_X1_WINDOW_OFFSET_Y__SHIFT) & A6XX_X1_WINDOW_OFFSET_Y__MASK;
2051
-}
2052
-
2053
-#define REG_A6XX_X2_WINDOW_OFFSET				0x0000b4d1
2054
-#define A6XX_X2_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2055
-#define A6XX_X2_WINDOW_OFFSET_X__MASK				0x00007fff
2056
-#define A6XX_X2_WINDOW_OFFSET_X__SHIFT				0
2057
-static inline uint32_t A6XX_X2_WINDOW_OFFSET_X(uint32_t val)
2058
-{
2059
-	return ((val) << A6XX_X2_WINDOW_OFFSET_X__SHIFT) & A6XX_X2_WINDOW_OFFSET_X__MASK;
2060
-}
2061
-#define A6XX_X2_WINDOW_OFFSET_Y__MASK				0x7fff0000
2062
-#define A6XX_X2_WINDOW_OFFSET_Y__SHIFT				16
2063
-static inline uint32_t A6XX_X2_WINDOW_OFFSET_Y(uint32_t val)
2064
-{
2065
-	return ((val) << A6XX_X2_WINDOW_OFFSET_Y__SHIFT) & A6XX_X2_WINDOW_OFFSET_Y__MASK;
2066
-}
2067
-
2068
-#define REG_A6XX_X3_WINDOW_OFFSET				0x0000b307
2069
-#define A6XX_X3_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2070
-#define A6XX_X3_WINDOW_OFFSET_X__MASK				0x00007fff
2071
-#define A6XX_X3_WINDOW_OFFSET_X__SHIFT				0
2072
-static inline uint32_t A6XX_X3_WINDOW_OFFSET_X(uint32_t val)
2073
-{
2074
-	return ((val) << A6XX_X3_WINDOW_OFFSET_X__SHIFT) & A6XX_X3_WINDOW_OFFSET_X__MASK;
2075
-}
2076
-#define A6XX_X3_WINDOW_OFFSET_Y__MASK				0x7fff0000
2077
-#define A6XX_X3_WINDOW_OFFSET_Y__SHIFT				16
2078
-static inline uint32_t A6XX_X3_WINDOW_OFFSET_Y(uint32_t val)
2079
-{
2080
-	return ((val) << A6XX_X3_WINDOW_OFFSET_Y__SHIFT) & A6XX_X3_WINDOW_OFFSET_Y__MASK;
2081
-}
2082
-
2083
-#define REG_A6XX_X1_BIN_SIZE					0x000080a1
2084
-#define A6XX_X1_BIN_SIZE_WIDTH__MASK				0x000000ff
2085
-#define A6XX_X1_BIN_SIZE_WIDTH__SHIFT				0
2086
-static inline uint32_t A6XX_X1_BIN_SIZE_WIDTH(uint32_t val)
2087
-{
2088
-	return ((val >> 5) << A6XX_X1_BIN_SIZE_WIDTH__SHIFT) & A6XX_X1_BIN_SIZE_WIDTH__MASK;
2089
-}
2090
-#define A6XX_X1_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2091
-#define A6XX_X1_BIN_SIZE_HEIGHT__SHIFT				8
2092
-static inline uint32_t A6XX_X1_BIN_SIZE_HEIGHT(uint32_t val)
2093
-{
2094
-	return ((val >> 4) << A6XX_X1_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X1_BIN_SIZE_HEIGHT__MASK;
2095
-}
2096
-
2097
-#define REG_A6XX_X2_BIN_SIZE					0x00008800
2098
-#define A6XX_X2_BIN_SIZE_WIDTH__MASK				0x000000ff
2099
-#define A6XX_X2_BIN_SIZE_WIDTH__SHIFT				0
2100
-static inline uint32_t A6XX_X2_BIN_SIZE_WIDTH(uint32_t val)
2101
-{
2102
-	return ((val >> 5) << A6XX_X2_BIN_SIZE_WIDTH__SHIFT) & A6XX_X2_BIN_SIZE_WIDTH__MASK;
2103
-}
2104
-#define A6XX_X2_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2105
-#define A6XX_X2_BIN_SIZE_HEIGHT__SHIFT				8
2106
-static inline uint32_t A6XX_X2_BIN_SIZE_HEIGHT(uint32_t val)
2107
-{
2108
-	return ((val >> 4) << A6XX_X2_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X2_BIN_SIZE_HEIGHT__MASK;
2109
-}
2110
-
2111
-#define REG_A6XX_X3_BIN_SIZE					0x000088d3
2112
-#define A6XX_X3_BIN_SIZE_WIDTH__MASK				0x000000ff
2113
-#define A6XX_X3_BIN_SIZE_WIDTH__SHIFT				0
2114
-static inline uint32_t A6XX_X3_BIN_SIZE_WIDTH(uint32_t val)
2115
-{
2116
-	return ((val >> 5) << A6XX_X3_BIN_SIZE_WIDTH__SHIFT) & A6XX_X3_BIN_SIZE_WIDTH__MASK;
2117
-}
2118
-#define A6XX_X3_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2119
-#define A6XX_X3_BIN_SIZE_HEIGHT__SHIFT				8
2120
-static inline uint32_t A6XX_X3_BIN_SIZE_HEIGHT(uint32_t val)
2121
-{
2122
-	return ((val >> 4) << A6XX_X3_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X3_BIN_SIZE_HEIGHT__MASK;
2585
+	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
21232586 }
21242587 
21252588 #define REG_A6XX_VSC_BIN_SIZE					0x00000c02
....@@ -2136,9 +2599,11 @@
21362599 	return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
21372600 }
21382601 
2139
-#define REG_A6XX_VSC_SIZE_ADDRESS_LO				0x00000c03
2602
+#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO			0x00000c03
21402603 
2141
-#define REG_A6XX_VSC_SIZE_ADDRESS_HI				0x00000c04
2604
+#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI			0x00000c04
2605
+
2606
+#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS			0x00000c03
21422607 
21432608 #define REG_A6XX_VSC_BIN_COUNT					0x00000c06
21442609 #define A6XX_VSC_BIN_COUNT_NX__MASK				0x000007fe
....@@ -2182,95 +2647,188 @@
21822647 	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
21832648 }
21842649 
2185
-#define REG_A6XX_VSC_XXX_ADDRESS_LO				0x00000c30
2650
+#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO			0x00000c30
21862651 
2187
-#define REG_A6XX_VSC_XXX_ADDRESS_HI				0x00000c31
2652
+#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI			0x00000c31
21882653 
2189
-#define REG_A6XX_VSC_XXX_PITCH					0x00000c32
2654
+#define REG_A6XX_VSC_PRIM_STRM_ADDRESS				0x00000c30
21902655 
2191
-#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO			0x00000c34
2656
+#define REG_A6XX_VSC_PRIM_STRM_PITCH				0x00000c32
21922657 
2193
-#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI			0x00000c35
2658
+#define REG_A6XX_VSC_PRIM_STRM_LIMIT				0x00000c33
21942659 
2195
-#define REG_A6XX_VSC_PIPE_DATA_PITCH				0x00000c36
2660
+#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO			0x00000c34
21962661 
2197
-static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2662
+#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI			0x00000c35
21982663 
2199
-static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2664
+#define REG_A6XX_VSC_DRAW_STRM_ADDRESS				0x00000c34
2665
+
2666
+#define REG_A6XX_VSC_DRAW_STRM_PITCH				0x00000c36
2667
+
2668
+#define REG_A6XX_VSC_DRAW_STRM_LIMIT				0x00000c37
2669
+
2670
+static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2671
+
2672
+static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2673
+
2674
+static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2675
+
2676
+static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2677
+
2678
+static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2679
+
2680
+static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
22002681 
22012682 #define REG_A6XX_UCHE_UNKNOWN_0E12				0x00000e12
22022683 
2203
-#define REG_A6XX_GRAS_UNKNOWN_8001				0x00008001
2684
+#define REG_A6XX_GRAS_CL_CNTL					0x00008000
2685
+#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE				0x00000001
2686
+#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE			0x00000002
2687
+#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE			0x00000004
2688
+#define A6XX_GRAS_CL_CNTL_UNK5					0x00000020
2689
+#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2690
+#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE			0x00000080
2691
+#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE			0x00000100
2692
+#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE		0x00000200
22042693 
2205
-#define REG_A6XX_GRAS_UNKNOWN_8004				0x00008004
2694
+#define REG_A6XX_GRAS_VS_CL_CNTL				0x00008001
2695
+#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2696
+#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2697
+static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2698
+{
2699
+	return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2700
+}
2701
+#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2702
+#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT			8
2703
+static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2704
+{
2705
+	return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2706
+}
2707
+
2708
+#define REG_A6XX_GRAS_DS_CL_CNTL				0x00008002
2709
+#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2710
+#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT			0
2711
+static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2712
+{
2713
+	return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2714
+}
2715
+#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2716
+#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT			8
2717
+static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2718
+{
2719
+	return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2720
+}
2721
+
2722
+#define REG_A6XX_GRAS_GS_CL_CNTL				0x00008003
2723
+#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2724
+#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT			0
2725
+static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2726
+{
2727
+	return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2728
+}
2729
+#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2730
+#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT			8
2731
+static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2732
+{
2733
+	return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2734
+}
2735
+
2736
+#define REG_A6XX_GRAS_MAX_LAYER_INDEX				0x00008004
22062737 
22072738 #define REG_A6XX_GRAS_CNTL					0x00008005
2208
-#define A6XX_GRAS_CNTL_VARYING					0x00000001
2209
-#define A6XX_GRAS_CNTL_XCOORD					0x00000040
2210
-#define A6XX_GRAS_CNTL_YCOORD					0x00000080
2211
-#define A6XX_GRAS_CNTL_ZCOORD					0x00000100
2212
-#define A6XX_GRAS_CNTL_WCOORD					0x00000200
2739
+#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2740
+#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2741
+#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2742
+#define A6XX_GRAS_CNTL_SIZE					0x00000008
2743
+#define A6XX_GRAS_CNTL_UNK4					0x00000010
2744
+#define A6XX_GRAS_CNTL_SIZE_PERSAMP				0x00000020
2745
+#define A6XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2746
+#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT			6
2747
+static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2748
+{
2749
+	return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2750
+}
22132751 
22142752 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x00008006
2215
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000003ff
2753
+#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000001ff
22162754 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
22172755 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
22182756 {
22192757 	return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
22202758 }
2221
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x000ffc00
2759
+#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x0007fc00
22222760 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT		10
22232761 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
22242762 {
22252763 	return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
22262764 }
22272765 
2228
-#define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0			0x00008010
2229
-#define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK			0xffffffff
2230
-#define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT			0
2231
-static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2766
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2767
+
2768
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2769
+#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
2770
+#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
2771
+static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
22322772 {
2233
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2773
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
22342774 }
22352775 
2236
-#define REG_A6XX_GRAS_CL_VPORT_XSCALE_0				0x00008011
2237
-#define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK			0xffffffff
2238
-#define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT			0
2239
-static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
2776
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2777
+#define A6XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
2778
+#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
2779
+static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
22402780 {
2241
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2781
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
22422782 }
22432783 
2244
-#define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0			0x00008012
2245
-#define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK			0xffffffff
2246
-#define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT			0
2247
-static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2784
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2785
+#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
2786
+#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
2787
+static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
22482788 {
2249
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2789
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
22502790 }
22512791 
2252
-#define REG_A6XX_GRAS_CL_VPORT_YSCALE_0				0x00008013
2253
-#define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK			0xffffffff
2254
-#define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT			0
2255
-static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
2792
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2793
+#define A6XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
2794
+#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
2795
+static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
22562796 {
2257
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2797
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
22582798 }
22592799 
2260
-#define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0			0x00008014
2261
-#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK			0xffffffff
2262
-#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT			0
2263
-static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2800
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2801
+#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
2802
+#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
2803
+static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
22642804 {
2265
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2805
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
22662806 }
22672807 
2268
-#define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0				0x00008015
2269
-#define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK			0xffffffff
2270
-#define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT			0
2271
-static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2808
+static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2809
+#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
2810
+#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
2811
+static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
22722812 {
2273
-	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2813
+	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2814
+}
2815
+
2816
+static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2817
+
2818
+static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2819
+#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK				0xffffffff
2820
+#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT				0
2821
+static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2822
+{
2823
+	return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2824
+}
2825
+
2826
+static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2827
+#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK				0xffffffff
2828
+#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT				0
2829
+static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2830
+{
2831
+	return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
22742832 }
22752833 
22762834 #define REG_A6XX_GRAS_SU_CNTL					0x00008090
....@@ -2284,7 +2842,19 @@
22842842 	return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
22852843 }
22862844 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2845
+#define A6XX_GRAS_SU_CNTL_UNK12__MASK				0x00001000
2846
+#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT				12
2847
+static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2848
+{
2849
+	return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2850
+}
22872851 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE				0x00002000
2852
+#define A6XX_GRAS_SU_CNTL_UNK15__MASK				0x007f8000
2853
+#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT				15
2854
+static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2855
+{
2856
+	return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2857
+}
22882858 
22892859 #define REG_A6XX_GRAS_SU_POINT_MINMAX				0x00008091
22902860 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
....@@ -2301,11 +2871,19 @@
23012871 }
23022872 
23032873 #define REG_A6XX_GRAS_SU_POINT_SIZE				0x00008092
2304
-#define A6XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
2874
+#define A6XX_GRAS_SU_POINT_SIZE__MASK				0x0000ffff
23052875 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT				0
23062876 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
23072877 {
23082878 	return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2879
+}
2880
+
2881
+#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
2882
+#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK		0x00000003
2883
+#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT		0
2884
+static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2885
+{
2886
+	return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
23092887 }
23102888 
23112889 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
....@@ -2339,10 +2917,64 @@
23392917 {
23402918 	return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
23412919 }
2920
+#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK		0x00000008
2921
+#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT		3
2922
+static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2923
+{
2924
+	return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2925
+}
23422926 
23432927 #define REG_A6XX_GRAS_UNKNOWN_8099				0x00008099
23442928 
2345
-#define REG_A6XX_GRAS_UNKNOWN_809B				0x0000809b
2929
+#define REG_A6XX_GRAS_UNKNOWN_809A				0x0000809a
2930
+
2931
+#define REG_A6XX_GRAS_VS_LAYER_CNTL				0x0000809b
2932
+#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER			0x00000001
2933
+#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW			0x00000002
2934
+
2935
+#define REG_A6XX_GRAS_GS_LAYER_CNTL				0x0000809c
2936
+#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER			0x00000001
2937
+#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW			0x00000002
2938
+
2939
+#define REG_A6XX_GRAS_DS_LAYER_CNTL				0x0000809d
2940
+#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER			0x00000001
2941
+#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW			0x00000002
2942
+
2943
+#define REG_A6XX_GRAS_UNKNOWN_80A0				0x000080a0
2944
+
2945
+#define REG_A6XX_GRAS_BIN_CONTROL				0x000080a1
2946
+#define A6XX_GRAS_BIN_CONTROL_BINW__MASK			0x0000003f
2947
+#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT			0
2948
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2949
+{
2950
+	return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2951
+}
2952
+#define A6XX_GRAS_BIN_CONTROL_BINH__MASK			0x00007f00
2953
+#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT			8
2954
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2955
+{
2956
+	return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2957
+}
2958
+#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS			0x00040000
2959
+#define A6XX_GRAS_BIN_CONTROL_UNK19__MASK			0x00080000
2960
+#define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT			19
2961
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
2962
+{
2963
+	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
2964
+}
2965
+#define A6XX_GRAS_BIN_CONTROL_UNK20__MASK			0x00100000
2966
+#define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT			20
2967
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
2968
+{
2969
+	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
2970
+}
2971
+#define A6XX_GRAS_BIN_CONTROL_USE_VIZ				0x00200000
2972
+#define A6XX_GRAS_BIN_CONTROL_UNK22__MASK			0x0fc00000
2973
+#define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT			22
2974
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
2975
+{
2976
+	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
2977
+}
23462978 
23472979 #define REG_A6XX_GRAS_RAS_MSAA_CNTL				0x000080a2
23482980 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
....@@ -2350,6 +2982,18 @@
23502982 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
23512983 {
23522984 	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2985
+}
2986
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
2987
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT			2
2988
+static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2989
+{
2990
+	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2991
+}
2992
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
2993
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT			3
2994
+static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2995
+{
2996
+	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
23532997 }
23542998 
23552999 #define REG_A6XX_GRAS_DEST_MSAA_CNTL				0x000080a3
....@@ -2361,83 +3005,180 @@
23613005 }
23623006 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
23633007 
2364
-#define REG_A6XX_GRAS_UNKNOWN_80A4				0x000080a4
3008
+#define REG_A6XX_GRAS_SAMPLE_CONFIG				0x000080a4
3009
+#define A6XX_GRAS_SAMPLE_CONFIG_UNK0				0x00000001
3010
+#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
23653011 
2366
-#define REG_A6XX_GRAS_UNKNOWN_80A5				0x000080a5
3012
+#define REG_A6XX_GRAS_SAMPLE_LOCATION_0				0x000080a5
3013
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
3014
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3015
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
3016
+{
3017
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3018
+}
3019
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3020
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
3021
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3022
+{
3023
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3024
+}
3025
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3026
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
3027
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3028
+{
3029
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3030
+}
3031
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3032
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
3033
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3034
+{
3035
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3036
+}
3037
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3038
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
3039
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3040
+{
3041
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3042
+}
3043
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3044
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
3045
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3046
+{
3047
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3048
+}
3049
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3050
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
3051
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3052
+{
3053
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3054
+}
3055
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3056
+#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
3057
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3058
+{
3059
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3060
+}
23673061 
2368
-#define REG_A6XX_GRAS_UNKNOWN_80A6				0x000080a6
3062
+#define REG_A6XX_GRAS_SAMPLE_LOCATION_1				0x000080a6
3063
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3064
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3065
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3066
+{
3067
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3068
+}
3069
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3070
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
3071
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3072
+{
3073
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3074
+}
3075
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3076
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
3077
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3078
+{
3079
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3080
+}
3081
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3082
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
3083
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3084
+{
3085
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3086
+}
3087
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3088
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
3089
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3090
+{
3091
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3092
+}
3093
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3094
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
3095
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3096
+{
3097
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3098
+}
3099
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3100
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
3101
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3102
+{
3103
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3104
+}
3105
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3106
+#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
3107
+static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3108
+{
3109
+	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3110
+}
23693111 
23703112 #define REG_A6XX_GRAS_UNKNOWN_80AF				0x000080af
23713113 
2372
-#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0			0x000080b0
2373
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
2374
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK		0x00007fff
2375
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT		0
2376
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
3114
+static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
3115
+
3116
+static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
3117
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x0000ffff
3118
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
3119
+static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
23773120 {
2378
-	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
3121
+	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
23793122 }
2380
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK		0x7fff0000
2381
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT		16
2382
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
3123
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0xffff0000
3124
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
3125
+static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
23833126 {
2384
-	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
3127
+	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
23853128 }
23863129 
2387
-#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0			0x000080b1
2388
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
2389
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK		0x00007fff
2390
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT		0
2391
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
3130
+static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
3131
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x0000ffff
3132
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
3133
+static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
23923134 {
2393
-	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
3135
+	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
23943136 }
2395
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK		0x7fff0000
2396
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT		16
2397
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
3137
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0xffff0000
3138
+#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
3139
+static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
23983140 {
2399
-	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
3141
+	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
24003142 }
24013143 
2402
-#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0			0x000080d0
2403
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
2404
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK		0x00007fff
2405
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT		0
2406
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
3144
+static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
3145
+
3146
+static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
3147
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK		0x0000ffff
3148
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT		0
3149
+static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
24073150 {
2408
-	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
3151
+	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
24093152 }
2410
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK		0x7fff0000
2411
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT		16
2412
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
3153
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK		0xffff0000
3154
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT		16
3155
+static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
24133156 {
2414
-	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
3157
+	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
24153158 }
24163159 
2417
-#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0			0x000080d1
2418
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
2419
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK		0x00007fff
2420
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT		0
2421
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
3160
+static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
3161
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK		0x0000ffff
3162
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT		0
3163
+static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
24223164 {
2423
-	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
3165
+	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
24243166 }
2425
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK		0x7fff0000
2426
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT		16
2427
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
3167
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK		0xffff0000
3168
+#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT		16
3169
+static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
24283170 {
2429
-	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
3171
+	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
24303172 }
24313173 
24323174 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL			0x000080f0
2433
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
2434
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
3175
+#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00003fff
24353176 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
24363177 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
24373178 {
24383179 	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
24393180 }
2440
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
3181
+#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x3fff0000
24413182 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
24423183 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
24433184 {
....@@ -2445,14 +3186,13 @@
24453186 }
24463187 
24473188 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR			0x000080f1
2448
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
2449
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
3189
+#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00003fff
24503190 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
24513191 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
24523192 {
24533193 	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
24543194 }
2455
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
3195
+#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x3fff0000
24563196 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
24573197 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
24583198 {
....@@ -2463,11 +3203,21 @@
24633203 #define A6XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
24643204 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
24653205 #define A6XX_GRAS_LRZ_CNTL_GREATER				0x00000004
3206
+#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE				0x00000008
3207
+#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE			0x00000010
3208
+#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK				0x000003e0
3209
+#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT				5
3210
+static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
3211
+{
3212
+	return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
3213
+}
3214
+
3215
+#define REG_A6XX_GRAS_UNKNOWN_8101				0x00008101
24663216 
24673217 #define REG_A6XX_GRAS_2D_BLIT_INFO				0x00008102
24683218 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK		0x000000ff
24693219 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT		0
2470
-static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3220
+static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
24713221 {
24723222 	return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
24733223 }
....@@ -2476,67 +3226,128 @@
24763226 
24773227 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI			0x00008104
24783228 
3229
+#define REG_A6XX_GRAS_LRZ_BUFFER_BASE				0x00008103
3230
+#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK				0xffffffff
3231
+#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT			0
3232
+static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
3233
+{
3234
+	return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
3235
+}
3236
+
24793237 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH				0x00008105
2480
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000007ff
3238
+#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000000ff
24813239 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT			0
24823240 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
24833241 {
24843242 	return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
24853243 }
2486
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x003ff800
2487
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT		11
3244
+#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffffc00
3245
+#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT		10
24883246 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
24893247 {
2490
-	return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3248
+	return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
24913249 }
24923250 
24933251 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO		0x00008106
24943252 
24953253 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI		0x00008107
24963254 
3255
+#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE		0x00008106
3256
+#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK		0xffffffff
3257
+#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT		0
3258
+static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
3259
+{
3260
+	return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
3261
+}
3262
+
3263
+#define REG_A6XX_GRAS_SAMPLE_CNTL				0x00008109
3264
+#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3265
+
3266
+#define REG_A6XX_GRAS_UNKNOWN_810A				0x0000810a
3267
+#define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK			0x000007ff
3268
+#define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT			0
3269
+static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
3270
+{
3271
+	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
3272
+}
3273
+#define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK			0x07ff0000
3274
+#define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT			16
3275
+static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
3276
+{
3277
+	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
3278
+}
3279
+#define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK			0xf0000000
3280
+#define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT			28
3281
+static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
3282
+{
3283
+	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
3284
+}
3285
+
3286
+#define REG_A6XX_GRAS_UNKNOWN_8110				0x00008110
3287
+
24973288 #define REG_A6XX_GRAS_2D_BLIT_CNTL				0x00008400
3289
+#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
3290
+#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT			0
3291
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3292
+{
3293
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
3294
+}
3295
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK			0x00000078
3296
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT			3
3297
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
3298
+{
3299
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
3300
+}
3301
+#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
3302
+#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK		0x0000ff00
3303
+#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT		8
3304
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
3305
+{
3306
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3307
+}
3308
+#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR				0x00010000
3309
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK			0x00060000
3310
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT			17
3311
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
3312
+{
3313
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
3314
+}
3315
+#define A6XX_GRAS_2D_BLIT_CNTL_D24S8				0x00080000
3316
+#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK			0x00f00000
3317
+#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT			20
3318
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
3319
+{
3320
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
3321
+}
3322
+#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK			0x1f000000
3323
+#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT			24
3324
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3325
+{
3326
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
3327
+}
3328
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK			0x20000000
3329
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT			29
3330
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
3331
+{
3332
+	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
3333
+}
24983334 
24993335 #define REG_A6XX_GRAS_2D_SRC_TL_X				0x00008401
2500
-#define A6XX_GRAS_2D_SRC_TL_X_X__MASK				0x00ffff00
2501
-#define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT				8
2502
-static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
2503
-{
2504
-	return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
2505
-}
25063336 
25073337 #define REG_A6XX_GRAS_2D_SRC_BR_X				0x00008402
2508
-#define A6XX_GRAS_2D_SRC_BR_X_X__MASK				0x00ffff00
2509
-#define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT				8
2510
-static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
2511
-{
2512
-	return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
2513
-}
25143338 
25153339 #define REG_A6XX_GRAS_2D_SRC_TL_Y				0x00008403
2516
-#define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK				0x00ffff00
2517
-#define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT				8
2518
-static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
2519
-{
2520
-	return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
2521
-}
25223340 
25233341 #define REG_A6XX_GRAS_2D_SRC_BR_Y				0x00008404
2524
-#define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK				0x00ffff00
2525
-#define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT				8
2526
-static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
2527
-{
2528
-	return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
2529
-}
25303342 
25313343 #define REG_A6XX_GRAS_2D_DST_TL					0x00008405
2532
-#define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE		0x80000000
2533
-#define A6XX_GRAS_2D_DST_TL_X__MASK				0x00007fff
3344
+#define A6XX_GRAS_2D_DST_TL_X__MASK				0x00003fff
25343345 #define A6XX_GRAS_2D_DST_TL_X__SHIFT				0
25353346 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
25363347 {
25373348 	return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
25383349 }
2539
-#define A6XX_GRAS_2D_DST_TL_Y__MASK				0x7fff0000
3350
+#define A6XX_GRAS_2D_DST_TL_Y__MASK				0x3fff0000
25403351 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT				16
25413352 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
25423353 {
....@@ -2544,51 +3355,138 @@
25443355 }
25453356 
25463357 #define REG_A6XX_GRAS_2D_DST_BR					0x00008406
2547
-#define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE		0x80000000
2548
-#define A6XX_GRAS_2D_DST_BR_X__MASK				0x00007fff
3358
+#define A6XX_GRAS_2D_DST_BR_X__MASK				0x00003fff
25493359 #define A6XX_GRAS_2D_DST_BR_X__SHIFT				0
25503360 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
25513361 {
25523362 	return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
25533363 }
2554
-#define A6XX_GRAS_2D_DST_BR_Y__MASK				0x7fff0000
3364
+#define A6XX_GRAS_2D_DST_BR_Y__MASK				0x3fff0000
25553365 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT				16
25563366 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
25573367 {
25583368 	return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
25593369 }
25603370 
2561
-#define REG_A6XX_GRAS_RESOLVE_CNTL_1				0x0000840a
2562
-#define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE		0x80000000
2563
-#define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK			0x00007fff
2564
-#define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT			0
2565
-static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
3371
+#define REG_A6XX_GRAS_2D_UNKNOWN_8407				0x00008407
3372
+
3373
+#define REG_A6XX_GRAS_2D_UNKNOWN_8408				0x00008408
3374
+
3375
+#define REG_A6XX_GRAS_2D_UNKNOWN_8409				0x00008409
3376
+
3377
+#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1				0x0000840a
3378
+#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK			0x00003fff
3379
+#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT			0
3380
+static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
25663381 {
2567
-	return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
3382
+	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
25683383 }
2569
-#define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK			0x7fff0000
2570
-#define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT			16
2571
-static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
3384
+#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK			0x3fff0000
3385
+#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT			16
3386
+static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
25723387 {
2573
-	return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
3388
+	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
25743389 }
25753390 
2576
-#define REG_A6XX_GRAS_RESOLVE_CNTL_2				0x0000840b
2577
-#define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE		0x80000000
2578
-#define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK			0x00007fff
2579
-#define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT			0
2580
-static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
3391
+#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2				0x0000840b
3392
+#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK			0x00003fff
3393
+#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT			0
3394
+static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
25813395 {
2582
-	return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
3396
+	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
25833397 }
2584
-#define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK			0x7fff0000
2585
-#define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT			16
2586
-static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
3398
+#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK			0x3fff0000
3399
+#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT			16
3400
+static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
25873401 {
2588
-	return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
3402
+	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
25893403 }
25903404 
25913405 #define REG_A6XX_GRAS_UNKNOWN_8600				0x00008600
3406
+
3407
+#define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601
3408
+
3409
+#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0				0x00008610
3410
+
3411
+#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1				0x00008611
3412
+
3413
+#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2				0x00008612
3414
+
3415
+#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3				0x00008613
3416
+
3417
+#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0				0x00008614
3418
+
3419
+#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1				0x00008615
3420
+
3421
+#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2				0x00008616
3422
+
3423
+#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3				0x00008617
3424
+
3425
+#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0				0x00008618
3426
+
3427
+#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1				0x00008619
3428
+
3429
+#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2				0x0000861a
3430
+
3431
+#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3				0x0000861b
3432
+
3433
+#define REG_A6XX_RB_BIN_CONTROL					0x00008800
3434
+#define A6XX_RB_BIN_CONTROL_BINW__MASK				0x0000003f
3435
+#define A6XX_RB_BIN_CONTROL_BINW__SHIFT				0
3436
+static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3437
+{
3438
+	return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3439
+}
3440
+#define A6XX_RB_BIN_CONTROL_BINH__MASK				0x00007f00
3441
+#define A6XX_RB_BIN_CONTROL_BINH__SHIFT				8
3442
+static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3443
+{
3444
+	return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3445
+}
3446
+#define A6XX_RB_BIN_CONTROL_BINNING_PASS			0x00040000
3447
+#define A6XX_RB_BIN_CONTROL_UNK19__MASK				0x00080000
3448
+#define A6XX_RB_BIN_CONTROL_UNK19__SHIFT			19
3449
+static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
3450
+{
3451
+	return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
3452
+}
3453
+#define A6XX_RB_BIN_CONTROL_UNK20__MASK				0x00100000
3454
+#define A6XX_RB_BIN_CONTROL_UNK20__SHIFT			20
3455
+static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
3456
+{
3457
+	return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
3458
+}
3459
+#define A6XX_RB_BIN_CONTROL_USE_VIZ				0x00200000
3460
+#define A6XX_RB_BIN_CONTROL_UNK22__MASK				0x07c00000
3461
+#define A6XX_RB_BIN_CONTROL_UNK22__SHIFT			22
3462
+static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
3463
+{
3464
+	return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
3465
+}
3466
+
3467
+#define REG_A6XX_RB_RENDER_CNTL					0x00008801
3468
+#define A6XX_RB_RENDER_CNTL_UNK3				0x00000008
3469
+#define A6XX_RB_RENDER_CNTL_UNK4				0x00000010
3470
+#define A6XX_RB_RENDER_CNTL_UNK5__MASK				0x00000060
3471
+#define A6XX_RB_RENDER_CNTL_UNK5__SHIFT				5
3472
+static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
3473
+{
3474
+	return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
3475
+}
3476
+#define A6XX_RB_RENDER_CNTL_BINNING				0x00000080
3477
+#define A6XX_RB_RENDER_CNTL_UNK8__MASK				0x00001f00
3478
+#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT				8
3479
+static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
3480
+{
3481
+	return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
3482
+}
3483
+#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
3484
+#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
3485
+#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT			16
3486
+static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3487
+{
3488
+	return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3489
+}
25923490 
25933491 #define REG_A6XX_RB_RAS_MSAA_CNTL				0x00008802
25943492 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
....@@ -2596,6 +3494,18 @@
25963494 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
25973495 {
25983496 	return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3497
+}
3498
+#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
3499
+#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT			2
3500
+static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
3501
+{
3502
+	return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
3503
+}
3504
+#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
3505
+#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT			3
3506
+static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
3507
+{
3508
+	return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
25993509 }
26003510 
26013511 #define REG_A6XX_RB_DEST_MSAA_CNTL				0x00008803
....@@ -2607,27 +3517,141 @@
26073517 }
26083518 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
26093519 
2610
-#define REG_A6XX_RB_UNKNOWN_8804				0x00008804
3520
+#define REG_A6XX_RB_SAMPLE_CONFIG				0x00008804
3521
+#define A6XX_RB_SAMPLE_CONFIG_UNK0				0x00000001
3522
+#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
26113523 
2612
-#define REG_A6XX_RB_UNKNOWN_8805				0x00008805
3524
+#define REG_A6XX_RB_SAMPLE_LOCATION_0				0x00008805
3525
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
3526
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3527
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
3528
+{
3529
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3530
+}
3531
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3532
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
3533
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3534
+{
3535
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3536
+}
3537
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3538
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
3539
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3540
+{
3541
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3542
+}
3543
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3544
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
3545
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3546
+{
3547
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3548
+}
3549
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3550
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
3551
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3552
+{
3553
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3554
+}
3555
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3556
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
3557
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3558
+{
3559
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3560
+}
3561
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3562
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
3563
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3564
+{
3565
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3566
+}
3567
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3568
+#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
3569
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3570
+{
3571
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3572
+}
26133573 
2614
-#define REG_A6XX_RB_UNKNOWN_8806				0x00008806
3574
+#define REG_A6XX_RB_SAMPLE_LOCATION_1				0x00008806
3575
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3576
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3577
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3578
+{
3579
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3580
+}
3581
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3582
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
3583
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3584
+{
3585
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3586
+}
3587
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3588
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
3589
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3590
+{
3591
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3592
+}
3593
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3594
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
3595
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3596
+{
3597
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3598
+}
3599
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3600
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
3601
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3602
+{
3603
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3604
+}
3605
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3606
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
3607
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3608
+{
3609
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3610
+}
3611
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3612
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
3613
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3614
+{
3615
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3616
+}
3617
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3618
+#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
3619
+static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3620
+{
3621
+	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3622
+}
26153623 
26163624 #define REG_A6XX_RB_RENDER_CONTROL0				0x00008809
2617
-#define A6XX_RB_RENDER_CONTROL0_VARYING				0x00000001
2618
-#define A6XX_RB_RENDER_CONTROL0_XCOORD				0x00000040
2619
-#define A6XX_RB_RENDER_CONTROL0_YCOORD				0x00000080
2620
-#define A6XX_RB_RENDER_CONTROL0_ZCOORD				0x00000100
2621
-#define A6XX_RB_RENDER_CONTROL0_WCOORD				0x00000200
3625
+#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3626
+#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3627
+#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3628
+#define A6XX_RB_RENDER_CONTROL0_SIZE				0x00000008
3629
+#define A6XX_RB_RENDER_CONTROL0_UNK4				0x00000010
3630
+#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP			0x00000020
3631
+#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3632
+#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT		6
3633
+static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3634
+{
3635
+	return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3636
+}
26223637 #define A6XX_RB_RENDER_CONTROL0_UNK10				0x00000400
26233638 
26243639 #define REG_A6XX_RB_RENDER_CONTROL1				0x0000880a
26253640 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
2626
-#define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000002
3641
+#define A6XX_RB_RENDER_CONTROL1_UNK1				0x00000002
3642
+#define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000004
26273643 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000008
3644
+#define A6XX_RB_RENDER_CONTROL1_UNK4				0x00000010
3645
+#define A6XX_RB_RENDER_CONTROL1_UNK5				0x00000020
3646
+#define A6XX_RB_RENDER_CONTROL1_SIZE				0x00000040
3647
+#define A6XX_RB_RENDER_CONTROL1_UNK7				0x00000080
3648
+#define A6XX_RB_RENDER_CONTROL1_UNK8				0x00000100
26283649 
26293650 #define REG_A6XX_RB_FS_OUTPUT_CNTL0				0x0000880b
3651
+#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
26303652 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z			0x00000002
3653
+#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK		0x00000004
3654
+#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF		0x00000008
26313655 
26323656 #define REG_A6XX_RB_FS_OUTPUT_CNTL1				0x0000880c
26333657 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
....@@ -2747,6 +3771,11 @@
27473771 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6				0x00000040
27483772 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7				0x00000080
27493773 
3774
+#define REG_A6XX_RB_SAMPLE_CNTL					0x00008810
3775
+#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3776
+
3777
+#define REG_A6XX_RB_UNKNOWN_8811				0x00008811
3778
+
27503779 #define REG_A6XX_RB_UNKNOWN_8818				0x00008818
27513780 
27523781 #define REG_A6XX_RB_UNKNOWN_8819				0x00008819
....@@ -2821,7 +3850,7 @@
28213850 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
28223851 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
28233852 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
2824
-static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3853
+static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
28253854 {
28263855 	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
28273856 }
....@@ -2831,16 +3860,21 @@
28313860 {
28323861 	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
28333862 }
3863
+#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK			0x00000400
3864
+#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT			10
3865
+static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3866
+{
3867
+	return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3868
+}
28343869 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
28353870 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT			13
28363871 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
28373872 {
28383873 	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
28393874 }
2840
-#define A6XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00008000
28413875 
28423876 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
2843
-#define A6XX_RB_MRT_PITCH__MASK					0xffffffff
3877
+#define A6XX_RB_MRT_PITCH__MASK					0x0000ffff
28443878 #define A6XX_RB_MRT_PITCH__SHIFT				0
28453879 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
28463880 {
....@@ -2848,7 +3882,7 @@
28483882 }
28493883 
28503884 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
2851
-#define A6XX_RB_MRT_ARRAY_PITCH__MASK				0xffffffff
3885
+#define A6XX_RB_MRT_ARRAY_PITCH__MASK				0x1fffffff
28523886 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT				0
28533887 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
28543888 {
....@@ -2859,7 +3893,21 @@
28593893 
28603894 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
28613895 
3896
+static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3897
+#define A6XX_RB_MRT_BASE__MASK					0xffffffff
3898
+#define A6XX_RB_MRT_BASE__SHIFT					0
3899
+static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3900
+{
3901
+	return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3902
+}
3903
+
28623904 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3905
+#define A6XX_RB_MRT_BASE_GMEM__MASK				0xfffff000
3906
+#define A6XX_RB_MRT_BASE_GMEM__SHIFT				12
3907
+static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3908
+{
3909
+	return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3910
+}
28633911 
28643912 #define REG_A6XX_RB_BLEND_RED_F32				0x00008860
28653913 #define A6XX_RB_BLEND_RED_F32__MASK				0xffffffff
....@@ -2916,11 +3964,22 @@
29163964 	return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
29173965 }
29183966 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3967
+#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
3968
+#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3969
+#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE				0x00000800
29193970 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
29203971 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT			16
29213972 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
29223973 {
29233974 	return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3975
+}
3976
+
3977
+#define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
3978
+#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK			0x00000003
3979
+#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT			0
3980
+static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3981
+{
3982
+	return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
29243983 }
29253984 
29263985 #define REG_A6XX_RB_DEPTH_CNTL					0x00008871
....@@ -2932,7 +3991,9 @@
29323991 {
29333992 	return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
29343993 }
3994
+#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE			0x00000020
29353995 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000040
3996
+#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE			0x00000080
29363997 
29373998 #define REG_A6XX_RB_DEPTH_BUFFER_INFO				0x00008872
29383999 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
....@@ -2941,9 +4002,15 @@
29414002 {
29424003 	return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
29434004 }
4005
+#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK			0x00000018
4006
+#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT			3
4007
+static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
4008
+{
4009
+	return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
4010
+}
29444011 
29454012 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH				0x00008873
2946
-#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0xffffffff
4013
+#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0x00003fff
29474014 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
29484015 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
29494016 {
....@@ -2951,7 +4018,7 @@
29514018 }
29524019 
29534020 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x00008874
2954
-#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0xffffffff
4021
+#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0x0fffffff
29554022 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
29564023 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
29574024 {
....@@ -2962,11 +4029,37 @@
29624029 
29634030 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI			0x00008876
29644031 
4032
+#define REG_A6XX_RB_DEPTH_BUFFER_BASE				0x00008875
4033
+#define A6XX_RB_DEPTH_BUFFER_BASE__MASK				0xffffffff
4034
+#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT			0
4035
+static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
4036
+{
4037
+	return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
4038
+}
4039
+
29654040 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM			0x00008877
4041
+#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK			0xfffff000
4042
+#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT			12
4043
+static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
4044
+{
4045
+	return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
4046
+}
29664047 
2967
-#define REG_A6XX_RB_UNKNOWN_8878				0x00008878
4048
+#define REG_A6XX_RB_Z_BOUNDS_MIN				0x00008878
4049
+#define A6XX_RB_Z_BOUNDS_MIN__MASK				0xffffffff
4050
+#define A6XX_RB_Z_BOUNDS_MIN__SHIFT				0
4051
+static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
4052
+{
4053
+	return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
4054
+}
29684055 
2969
-#define REG_A6XX_RB_UNKNOWN_8879				0x00008879
4056
+#define REG_A6XX_RB_Z_BOUNDS_MAX				0x00008879
4057
+#define A6XX_RB_Z_BOUNDS_MAX__MASK				0xffffffff
4058
+#define A6XX_RB_Z_BOUNDS_MAX__SHIFT				0
4059
+static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
4060
+{
4061
+	return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
4062
+}
29704063 
29714064 #define REG_A6XX_RB_STENCIL_CONTROL				0x00008880
29724065 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
....@@ -3023,9 +4116,10 @@
30234116 
30244117 #define REG_A6XX_RB_STENCIL_INFO				0x00008881
30254118 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
4119
+#define A6XX_RB_STENCIL_INFO_UNK1				0x00000002
30264120 
30274121 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH			0x00008882
3028
-#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0xffffffff
4122
+#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0x00000fff
30294123 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT			0
30304124 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
30314125 {
....@@ -3033,7 +4127,7 @@
30334127 }
30344128 
30354129 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH			0x00008883
3036
-#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0xffffffff
4130
+#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0x00ffffff
30374131 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT		0
30384132 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
30394133 {
....@@ -3044,7 +4138,21 @@
30444138 
30454139 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI			0x00008885
30464140 
4141
+#define REG_A6XX_RB_STENCIL_BUFFER_BASE				0x00008884
4142
+#define A6XX_RB_STENCIL_BUFFER_BASE__MASK			0xffffffff
4143
+#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT			0
4144
+static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
4145
+{
4146
+	return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
4147
+}
4148
+
30474149 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM			0x00008886
4150
+#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK			0xfffff000
4151
+#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT			12
4152
+static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
4153
+{
4154
+	return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
4155
+}
30484156 
30494157 #define REG_A6XX_RB_STENCILREF					0x00008887
30504158 #define A6XX_RB_STENCILREF_REF__MASK				0x000000ff
....@@ -3052,6 +4160,12 @@
30524160 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
30534161 {
30544162 	return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
4163
+}
4164
+#define A6XX_RB_STENCILREF_BFREF__MASK				0x0000ff00
4165
+#define A6XX_RB_STENCILREF_BFREF__SHIFT				8
4166
+static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
4167
+{
4168
+	return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
30554169 }
30564170 
30574171 #define REG_A6XX_RB_STENCILMASK					0x00008888
....@@ -3061,6 +4175,12 @@
30614175 {
30624176 	return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
30634177 }
4178
+#define A6XX_RB_STENCILMASK_BFMASK__MASK			0x0000ff00
4179
+#define A6XX_RB_STENCILMASK_BFMASK__SHIFT			8
4180
+static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
4181
+{
4182
+	return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
4183
+}
30644184 
30654185 #define REG_A6XX_RB_STENCILWRMASK				0x00008889
30664186 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK			0x000000ff
....@@ -3069,16 +4189,21 @@
30694189 {
30704190 	return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
30714191 }
4192
+#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK			0x0000ff00
4193
+#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT			8
4194
+static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
4195
+{
4196
+	return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
4197
+}
30724198 
30734199 #define REG_A6XX_RB_WINDOW_OFFSET				0x00008890
3074
-#define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
3075
-#define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00007fff
4200
+#define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00003fff
30764201 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT				0
30774202 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
30784203 {
30794204 	return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
30804205 }
3081
-#define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x7fff0000
4206
+#define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x3fff0000
30824207 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT				16
30834208 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
30844209 {
....@@ -3086,19 +4211,50 @@
30864211 }
30874212 
30884213 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL			0x00008891
4214
+#define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0			0x00000001
30894215 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
30904216 
4217
+#define REG_A6XX_RB_LRZ_CNTL					0x00008898
4218
+#define A6XX_RB_LRZ_CNTL_ENABLE					0x00000001
4219
+
4220
+#define REG_A6XX_RB_Z_CLAMP_MIN					0x000088c0
4221
+#define A6XX_RB_Z_CLAMP_MIN__MASK				0xffffffff
4222
+#define A6XX_RB_Z_CLAMP_MIN__SHIFT				0
4223
+static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
4224
+{
4225
+	return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
4226
+}
4227
+
4228
+#define REG_A6XX_RB_Z_CLAMP_MAX					0x000088c1
4229
+#define A6XX_RB_Z_CLAMP_MAX__MASK				0xffffffff
4230
+#define A6XX_RB_Z_CLAMP_MAX__SHIFT				0
4231
+static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
4232
+{
4233
+	return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
4234
+}
4235
+
30914236 #define REG_A6XX_RB_UNKNOWN_88D0				0x000088d0
4237
+#define A6XX_RB_UNKNOWN_88D0_UNK0__MASK				0x00001fff
4238
+#define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT			0
4239
+static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
4240
+{
4241
+	return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
4242
+}
4243
+#define A6XX_RB_UNKNOWN_88D0_UNK16__MASK			0x07ff0000
4244
+#define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT			16
4245
+static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
4246
+{
4247
+	return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
4248
+}
30924249 
30934250 #define REG_A6XX_RB_BLIT_SCISSOR_TL				0x000088d1
3094
-#define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE		0x80000000
3095
-#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00007fff
4251
+#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00003fff
30964252 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT			0
30974253 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
30984254 {
30994255 	return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
31004256 }
3101
-#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x7fff0000
4257
+#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x3fff0000
31024258 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT			16
31034259 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
31044260 {
....@@ -3106,21 +4262,62 @@
31064262 }
31074263 
31084264 #define REG_A6XX_RB_BLIT_SCISSOR_BR				0x000088d2
3109
-#define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE		0x80000000
3110
-#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00007fff
4265
+#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00003fff
31114266 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT			0
31124267 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
31134268 {
31144269 	return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
31154270 }
3116
-#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x7fff0000
4271
+#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x3fff0000
31174272 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT			16
31184273 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
31194274 {
31204275 	return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
31214276 }
31224277 
4278
+#define REG_A6XX_RB_BIN_CONTROL2				0x000088d3
4279
+#define A6XX_RB_BIN_CONTROL2_BINW__MASK				0x0000003f
4280
+#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT			0
4281
+static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
4282
+{
4283
+	return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
4284
+}
4285
+#define A6XX_RB_BIN_CONTROL2_BINH__MASK				0x00007f00
4286
+#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT			8
4287
+static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
4288
+{
4289
+	return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
4290
+}
4291
+
4292
+#define REG_A6XX_RB_WINDOW_OFFSET2				0x000088d4
4293
+#define A6XX_RB_WINDOW_OFFSET2_X__MASK				0x00003fff
4294
+#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT				0
4295
+static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
4296
+{
4297
+	return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
4298
+}
4299
+#define A6XX_RB_WINDOW_OFFSET2_Y__MASK				0x3fff0000
4300
+#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT				16
4301
+static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
4302
+{
4303
+	return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
4304
+}
4305
+
4306
+#define REG_A6XX_RB_MSAA_CNTL					0x000088d5
4307
+#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK				0x00000018
4308
+#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT			3
4309
+static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4310
+{
4311
+	return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
4312
+}
4313
+
31234314 #define REG_A6XX_RB_BLIT_BASE_GMEM				0x000088d6
4315
+#define A6XX_RB_BLIT_BASE_GMEM__MASK				0xfffff000
4316
+#define A6XX_RB_BLIT_BASE_GMEM__SHIFT				12
4317
+static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
4318
+{
4319
+	return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
4320
+}
31244321 
31254322 #define REG_A6XX_RB_BLIT_DST_INFO				0x000088d7
31264323 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK			0x00000003
....@@ -3130,11 +4327,11 @@
31304327 	return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
31314328 }
31324329 #define A6XX_RB_BLIT_DST_INFO_FLAGS				0x00000004
3133
-#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
3134
-#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT		7
3135
-static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
4330
+#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK			0x00000018
4331
+#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT			3
4332
+static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
31364333 {
3137
-	return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
4334
+	return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
31384335 }
31394336 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK			0x00000060
31404337 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT			5
....@@ -3142,13 +4339,28 @@
31424339 {
31434340 	return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
31444341 }
4342
+#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
4343
+#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT		7
4344
+static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4345
+{
4346
+	return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
4347
+}
4348
+#define A6XX_RB_BLIT_DST_INFO_UNK15				0x00008000
4349
+
4350
+#define REG_A6XX_RB_BLIT_DST					0x000088d8
4351
+#define A6XX_RB_BLIT_DST__MASK					0xffffffff
4352
+#define A6XX_RB_BLIT_DST__SHIFT					0
4353
+static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
4354
+{
4355
+	return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
4356
+}
31454357 
31464358 #define REG_A6XX_RB_BLIT_DST_LO					0x000088d8
31474359 
31484360 #define REG_A6XX_RB_BLIT_DST_HI					0x000088d9
31494361 
31504362 #define REG_A6XX_RB_BLIT_DST_PITCH				0x000088da
3151
-#define A6XX_RB_BLIT_DST_PITCH__MASK				0xffffffff
4363
+#define A6XX_RB_BLIT_DST_PITCH__MASK				0x0000ffff
31524364 #define A6XX_RB_BLIT_DST_PITCH__SHIFT				0
31534365 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
31544366 {
....@@ -3156,16 +4368,38 @@
31564368 }
31574369 
31584370 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH			0x000088db
3159
-#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0xffffffff
4371
+#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0x1fffffff
31604372 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
31614373 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
31624374 {
31634375 	return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
31644376 }
31654377 
4378
+#define REG_A6XX_RB_BLIT_FLAG_DST				0x000088dc
4379
+#define A6XX_RB_BLIT_FLAG_DST__MASK				0xffffffff
4380
+#define A6XX_RB_BLIT_FLAG_DST__SHIFT				0
4381
+static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
4382
+{
4383
+	return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
4384
+}
4385
+
31664386 #define REG_A6XX_RB_BLIT_FLAG_DST_LO				0x000088dc
31674387 
31684388 #define REG_A6XX_RB_BLIT_FLAG_DST_HI				0x000088dd
4389
+
4390
+#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH				0x000088de
4391
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK			0x000007ff
4392
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT		0
4393
+static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
4394
+{
4395
+	return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
4396
+}
4397
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK		0x0ffff800
4398
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT		11
4399
+static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
4400
+{
4401
+	return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
4402
+}
31694403 
31704404 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0			0x000088df
31714405 
....@@ -3177,23 +4411,85 @@
31774411 
31784412 #define REG_A6XX_RB_BLIT_INFO					0x000088e3
31794413 #define A6XX_RB_BLIT_INFO_UNK0					0x00000001
3180
-#define A6XX_RB_BLIT_INFO_FAST_CLEAR				0x00000002
4414
+#define A6XX_RB_BLIT_INFO_GMEM					0x00000002
31814415 #define A6XX_RB_BLIT_INFO_INTEGER				0x00000004
3182
-#define A6XX_RB_BLIT_INFO_UNK3					0x00000008
3183
-#define A6XX_RB_BLIT_INFO_MASK__MASK				0x000000f0
3184
-#define A6XX_RB_BLIT_INFO_MASK__SHIFT				4
3185
-static inline uint32_t A6XX_RB_BLIT_INFO_MASK(uint32_t val)
4416
+#define A6XX_RB_BLIT_INFO_DEPTH					0x00000008
4417
+#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK			0x000000f0
4418
+#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT			4
4419
+static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
31864420 {
3187
-	return ((val) << A6XX_RB_BLIT_INFO_MASK__SHIFT) & A6XX_RB_BLIT_INFO_MASK__MASK;
4421
+	return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
4422
+}
4423
+#define A6XX_RB_BLIT_INFO_UNK8__MASK				0x00000300
4424
+#define A6XX_RB_BLIT_INFO_UNK8__SHIFT				8
4425
+static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
4426
+{
4427
+	return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
4428
+}
4429
+#define A6XX_RB_BLIT_INFO_UNK12__MASK				0x0000f000
4430
+#define A6XX_RB_BLIT_INFO_UNK12__SHIFT				12
4431
+static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
4432
+{
4433
+	return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
31884434 }
31894435 
31904436 #define REG_A6XX_RB_UNKNOWN_88F0				0x000088f0
4437
+
4438
+#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE			0x000088f1
4439
+#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK			0xffffffff
4440
+#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT			0
4441
+static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
4442
+{
4443
+	return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
4444
+}
4445
+
4446
+#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH			0x000088f3
4447
+#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
4448
+#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4449
+static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4450
+{
4451
+	return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
4452
+}
4453
+#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x00fff800
4454
+#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
4455
+static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4456
+{
4457
+	return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4458
+}
4459
+
4460
+#define REG_A6XX_RB_UNKNOWN_88F4				0x000088f4
31914461 
31924462 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO			0x00008900
31934463 
31944464 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI			0x00008901
31954465 
4466
+#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE			0x00008900
4467
+#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK			0xffffffff
4468
+#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT			0
4469
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
4470
+{
4471
+	return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
4472
+}
4473
+
31964474 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x00008902
4475
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK		0x0000007f
4476
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4477
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4478
+{
4479
+	return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
4480
+}
4481
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK		0x00000700
4482
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT		8
4483
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
4484
+{
4485
+	return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
4486
+}
4487
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK	0x0ffff800
4488
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
4489
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4490
+{
4491
+	return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4492
+}
31974493 
31984494 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
31994495 
....@@ -3201,36 +4497,93 @@
32014497 
32024498 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
32034499 
4500
+static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4501
+#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK			0xffffffff
4502
+#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT			0
4503
+static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
4504
+{
4505
+	return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
4506
+}
4507
+
32044508 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
32054509 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
32064510 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
32074511 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
32084512 {
3209
-	return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
4513
+	return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
32104514 }
3211
-#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x003ff800
4515
+#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffff800
32124516 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
32134517 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
32144518 {
3215
-	return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4519
+	return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
32164520 }
32174521 
32184522 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO			0x00008927
32194523 
32204524 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI			0x00008928
32214525 
4526
+#define REG_A6XX_RB_SAMPLE_COUNT_ADDR				0x00008927
4527
+#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK				0xffffffff
4528
+#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT			0
4529
+static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
4530
+{
4531
+	return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
4532
+}
4533
+
32224534 #define REG_A6XX_RB_2D_BLIT_CNTL				0x00008c00
4535
+#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
4536
+#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT			0
4537
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
4538
+{
4539
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
4540
+}
4541
+#define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK				0x00000078
4542
+#define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT			3
4543
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)
4544
+{
4545
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK;
4546
+}
4547
+#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
32234548 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK			0x0000ff00
32244549 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT		8
3225
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
4550
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
32264551 {
32274552 	return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
32284553 }
4554
+#define A6XX_RB_2D_BLIT_CNTL_SCISSOR				0x00010000
4555
+#define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK			0x00060000
4556
+#define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT			17
4557
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
4558
+{
4559
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
4560
+}
4561
+#define A6XX_RB_2D_BLIT_CNTL_D24S8				0x00080000
4562
+#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK				0x00f00000
4563
+#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT			20
4564
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
4565
+{
4566
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
4567
+}
4568
+#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK				0x1f000000
4569
+#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT			24
4570
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
4571
+{
4572
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
4573
+}
4574
+#define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK			0x20000000
4575
+#define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT			29
4576
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)
4577
+{
4578
+	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK;
4579
+}
4580
+
4581
+#define REG_A6XX_RB_2D_UNKNOWN_8C01				0x00008c01
32294582 
32304583 #define REG_A6XX_RB_2D_DST_INFO					0x00008c17
32314584 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
32324585 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
3233
-static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
4586
+static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
32344587 {
32354588 	return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
32364589 }
....@@ -3247,22 +4600,97 @@
32474600 	return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
32484601 }
32494602 #define A6XX_RB_2D_DST_INFO_FLAGS				0x00001000
4603
+#define A6XX_RB_2D_DST_INFO_SRGB				0x00002000
4604
+#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK			0x0000c000
4605
+#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT			14
4606
+static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4607
+{
4608
+	return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4609
+}
4610
+#define A6XX_RB_2D_DST_INFO_FILTER				0x00010000
4611
+#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE			0x00040000
4612
+#define A6XX_RB_2D_DST_INFO_UNK20				0x00100000
4613
+#define A6XX_RB_2D_DST_INFO_UNK22				0x00400000
32504614 
32514615 #define REG_A6XX_RB_2D_DST_LO					0x00008c18
32524616 
32534617 #define REG_A6XX_RB_2D_DST_HI					0x00008c19
32544618 
3255
-#define REG_A6XX_RB_2D_DST_SIZE					0x00008c1a
3256
-#define A6XX_RB_2D_DST_SIZE_PITCH__MASK				0x0000ffff
3257
-#define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT			0
3258
-static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
4619
+#define REG_A6XX_RB_2D_DST					0x00008c18
4620
+#define A6XX_RB_2D_DST__MASK					0xffffffff
4621
+#define A6XX_RB_2D_DST__SHIFT					0
4622
+static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
32594623 {
3260
-	return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
4624
+	return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4625
+}
4626
+
4627
+#define REG_A6XX_RB_2D_DST_PITCH				0x00008c1a
4628
+#define A6XX_RB_2D_DST_PITCH__MASK				0x0000ffff
4629
+#define A6XX_RB_2D_DST_PITCH__SHIFT				0
4630
+static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
4631
+{
4632
+	return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
4633
+}
4634
+
4635
+#define REG_A6XX_RB_2D_DST_PLANE1				0x00008c1b
4636
+#define A6XX_RB_2D_DST_PLANE1__MASK				0xffffffff
4637
+#define A6XX_RB_2D_DST_PLANE1__SHIFT				0
4638
+static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
4639
+{
4640
+	return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
4641
+}
4642
+
4643
+#define REG_A6XX_RB_2D_DST_PLANE_PITCH				0x00008c1d
4644
+#define A6XX_RB_2D_DST_PLANE_PITCH__MASK			0x0000ffff
4645
+#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT			0
4646
+static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
4647
+{
4648
+	return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
4649
+}
4650
+
4651
+#define REG_A6XX_RB_2D_DST_PLANE2				0x00008c1e
4652
+#define A6XX_RB_2D_DST_PLANE2__MASK				0xffffffff
4653
+#define A6XX_RB_2D_DST_PLANE2__SHIFT				0
4654
+static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4655
+{
4656
+	return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
32614657 }
32624658 
32634659 #define REG_A6XX_RB_2D_DST_FLAGS_LO				0x00008c20
32644660 
32654661 #define REG_A6XX_RB_2D_DST_FLAGS_HI				0x00008c21
4662
+
4663
+#define REG_A6XX_RB_2D_DST_FLAGS				0x00008c20
4664
+#define A6XX_RB_2D_DST_FLAGS__MASK				0xffffffff
4665
+#define A6XX_RB_2D_DST_FLAGS__SHIFT				0
4666
+static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4667
+{
4668
+	return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4669
+}
4670
+
4671
+#define REG_A6XX_RB_2D_DST_FLAGS_PITCH				0x00008c22
4672
+#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK			0x000000ff
4673
+#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
4674
+static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
4675
+{
4676
+	return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
4677
+}
4678
+
4679
+#define REG_A6XX_RB_2D_DST_FLAGS_PLANE				0x00008c23
4680
+#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK			0xffffffff
4681
+#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT			0
4682
+static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
4683
+{
4684
+	return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
4685
+}
4686
+
4687
+#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH			0x00008c25
4688
+#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK			0x000000ff
4689
+#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT			0
4690
+static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
4691
+{
4692
+	return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
4693
+}
32664694 
32674695 #define REG_A6XX_RB_2D_SRC_SOLID_C0				0x00008c2c
32684696 
....@@ -3274,13 +4702,207 @@
32744702 
32754703 #define REG_A6XX_RB_UNKNOWN_8E01				0x00008e01
32764704 
4705
+#define REG_A6XX_RB_UNKNOWN_8E04				0x00008e04
4706
+
4707
+#define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05
4708
+
32774709 #define REG_A6XX_RB_CCU_CNTL					0x00008e07
4710
+#define A6XX_RB_CCU_CNTL_OFFSET__MASK				0xff800000
4711
+#define A6XX_RB_CCU_CNTL_OFFSET__SHIFT				23
4712
+static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
4713
+{
4714
+	return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
4715
+}
4716
+#define A6XX_RB_CCU_CNTL_GMEM					0x00400000
4717
+#define A6XX_RB_CCU_CNTL_UNK2					0x00000004
32784718 
3279
-#define REG_A6XX_VPC_UNKNOWN_9101				0x00009101
4719
+#define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
4720
+#define A6XX_RB_NC_MODE_CNTL_MODE				0x00000001
4721
+#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
4722
+#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT			1
4723
+static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4724
+{
4725
+	return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4726
+}
4727
+#define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH			0x00000008
4728
+#define A6XX_RB_NC_MODE_CNTL_AMSBC				0x00000010
4729
+#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000400
4730
+#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT			10
4731
+static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4732
+{
4733
+	return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4734
+}
4735
+#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR			0x00000800
4736
+#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK			0x00003000
4737
+#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT			12
4738
+static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4739
+{
4740
+	return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4741
+}
32804742 
3281
-#define REG_A6XX_VPC_GS_SIV_CNTL				0x00009104
4743
+#define REG_A6XX_RB_PERFCTR_RB_SEL_0				0x00008e10
32824744 
3283
-#define REG_A6XX_VPC_UNKNOWN_9108				0x00009108
4745
+#define REG_A6XX_RB_PERFCTR_RB_SEL_1				0x00008e11
4746
+
4747
+#define REG_A6XX_RB_PERFCTR_RB_SEL_2				0x00008e12
4748
+
4749
+#define REG_A6XX_RB_PERFCTR_RB_SEL_3				0x00008e13
4750
+
4751
+#define REG_A6XX_RB_PERFCTR_RB_SEL_4				0x00008e14
4752
+
4753
+#define REG_A6XX_RB_PERFCTR_RB_SEL_5				0x00008e15
4754
+
4755
+#define REG_A6XX_RB_PERFCTR_RB_SEL_6				0x00008e16
4756
+
4757
+#define REG_A6XX_RB_PERFCTR_RB_SEL_7				0x00008e17
4758
+
4759
+#define REG_A6XX_RB_PERFCTR_CCU_SEL_0				0x00008e18
4760
+
4761
+#define REG_A6XX_RB_PERFCTR_CCU_SEL_1				0x00008e19
4762
+
4763
+#define REG_A6XX_RB_PERFCTR_CCU_SEL_2				0x00008e1a
4764
+
4765
+#define REG_A6XX_RB_PERFCTR_CCU_SEL_3				0x00008e1b
4766
+
4767
+#define REG_A6XX_RB_PERFCTR_CCU_SEL_4				0x00008e1c
4768
+
4769
+#define REG_A6XX_RB_UNKNOWN_8E28				0x00008e28
4770
+
4771
+#define REG_A6XX_RB_PERFCTR_CMP_SEL_0				0x00008e2c
4772
+
4773
+#define REG_A6XX_RB_PERFCTR_CMP_SEL_1				0x00008e2d
4774
+
4775
+#define REG_A6XX_RB_PERFCTR_CMP_SEL_2				0x00008e2e
4776
+
4777
+#define REG_A6XX_RB_PERFCTR_CMP_SEL_3				0x00008e2f
4778
+
4779
+#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST			0x00008e3b
4780
+
4781
+#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d
4782
+
4783
+#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50
4784
+
4785
+#define REG_A6XX_RB_UNKNOWN_8E51				0x00008e51
4786
+#define A6XX_RB_UNKNOWN_8E51__MASK				0xffffffff
4787
+#define A6XX_RB_UNKNOWN_8E51__SHIFT				0
4788
+static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4789
+{
4790
+	return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4791
+}
4792
+
4793
+#define REG_A6XX_VPC_UNKNOWN_9100				0x00009100
4794
+
4795
+#define REG_A6XX_VPC_VS_CLIP_CNTL				0x00009101
4796
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4797
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4798
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4799
+{
4800
+	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4801
+}
4802
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4803
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
4804
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4805
+{
4806
+	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4807
+}
4808
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4809
+#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
4810
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4811
+{
4812
+	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4813
+}
4814
+
4815
+#define REG_A6XX_VPC_GS_CLIP_CNTL				0x00009102
4816
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4817
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4818
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4819
+{
4820
+	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4821
+}
4822
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4823
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
4824
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4825
+{
4826
+	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4827
+}
4828
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4829
+#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
4830
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4831
+{
4832
+	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4833
+}
4834
+
4835
+#define REG_A6XX_VPC_DS_CLIP_CNTL				0x00009103
4836
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4837
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4838
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4839
+{
4840
+	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4841
+}
4842
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4843
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
4844
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4845
+{
4846
+	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4847
+}
4848
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4849
+#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
4850
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4851
+{
4852
+	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4853
+}
4854
+
4855
+#define REG_A6XX_VPC_VS_LAYER_CNTL				0x00009104
4856
+#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4857
+#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT			0
4858
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4859
+{
4860
+	return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4861
+}
4862
+#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4863
+#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT			8
4864
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4865
+{
4866
+	return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4867
+}
4868
+
4869
+#define REG_A6XX_VPC_GS_LAYER_CNTL				0x00009105
4870
+#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4871
+#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT			0
4872
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4873
+{
4874
+	return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4875
+}
4876
+#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4877
+#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT			8
4878
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4879
+{
4880
+	return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4881
+}
4882
+
4883
+#define REG_A6XX_VPC_DS_LAYER_CNTL				0x00009106
4884
+#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4885
+#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT			0
4886
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4887
+{
4888
+	return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4889
+}
4890
+#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4891
+#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT			8
4892
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4893
+{
4894
+	return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4895
+}
4896
+
4897
+#define REG_A6XX_VPC_UNKNOWN_9107				0x00009107
4898
+
4899
+#define REG_A6XX_VPC_POLYGON_MODE				0x00009108
4900
+#define A6XX_VPC_POLYGON_MODE_MODE__MASK			0x00000003
4901
+#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT			0
4902
+static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4903
+{
4904
+	return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4905
+}
32844906 
32854907 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
32864908 
....@@ -3299,6 +4921,12 @@
32994921 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
33004922 
33014923 #define REG_A6XX_VPC_SO_CNTL					0x00009216
4924
+#define A6XX_VPC_SO_CNTL_UNK0__MASK				0x000000ff
4925
+#define A6XX_VPC_SO_CNTL_UNK0__SHIFT				0
4926
+static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
4927
+{
4928
+	return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
4929
+}
33024930 #define A6XX_VPC_SO_CNTL_ENABLE					0x00010000
33034931 
33044932 #define REG_A6XX_VPC_SO_PROG					0x00009217
....@@ -3329,44 +4957,143 @@
33294957 }
33304958 #define A6XX_VPC_SO_PROG_B_EN					0x00800000
33314959 
4960
+#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO			0x00009218
4961
+
4962
+#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI			0x00009219
4963
+
4964
+#define REG_A6XX_VPC_SO_STREAM_COUNTS				0x00009218
4965
+#define A6XX_VPC_SO_STREAM_COUNTS__MASK				0xffffffff
4966
+#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT			0
4967
+static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4968
+{
4969
+	return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4970
+}
4971
+
33324972 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4973
+
4974
+static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4975
+#define A6XX_VPC_SO_BUFFER_BASE__MASK				0xffffffff
4976
+#define A6XX_VPC_SO_BUFFER_BASE__SHIFT				0
4977
+static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4978
+{
4979
+	return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4980
+}
33334981 
33344982 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
33354983 
33364984 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
33374985 
33384986 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4987
+#define A6XX_VPC_SO_BUFFER_SIZE__MASK				0xfffffffc
4988
+#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT				2
4989
+static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4990
+{
4991
+	return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4992
+}
33394993 
33404994 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
33414995 
33424996 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4997
+#define A6XX_VPC_SO_BUFFER_OFFSET__MASK				0xfffffffc
4998
+#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT			2
4999
+static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
5000
+{
5001
+	return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
5002
+}
5003
+
5004
+static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5005
+#define A6XX_VPC_SO_FLUSH_BASE__MASK				0xffffffff
5006
+#define A6XX_VPC_SO_FLUSH_BASE__SHIFT				0
5007
+static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
5008
+{
5009
+	return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
5010
+}
33435011 
33445012 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
33455013 
33465014 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
33475015 
3348
-#define REG_A6XX_VPC_UNKNOWN_9236				0x00009236
5016
+#define REG_A6XX_VPC_POINT_COORD_INVERT				0x00009236
5017
+#define A6XX_VPC_POINT_COORD_INVERT_INVERT			0x00000001
33495018 
33505019 #define REG_A6XX_VPC_UNKNOWN_9300				0x00009300
33515020 
3352
-#define REG_A6XX_VPC_PACK					0x00009301
3353
-#define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK			0x000000ff
3354
-#define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT			0
3355
-static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
5021
+#define REG_A6XX_VPC_VS_PACK					0x00009301
5022
+#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5023
+#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT			0
5024
+static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
33565025 {
3357
-	return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
5026
+	return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
33585027 }
3359
-#define A6XX_VPC_PACK_NUMNONPOSVAR__MASK			0x0000ff00
3360
-#define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT			8
3361
-static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
5028
+#define A6XX_VPC_VS_PACK_POSITIONLOC__MASK			0x0000ff00
5029
+#define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT			8
5030
+static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
33625031 {
3363
-	return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
5032
+	return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
33645033 }
3365
-#define A6XX_VPC_PACK_PSIZELOC__MASK				0x00ff0000
3366
-#define A6XX_VPC_PACK_PSIZELOC__SHIFT				16
3367
-static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
5034
+#define A6XX_VPC_VS_PACK_PSIZELOC__MASK				0x00ff0000
5035
+#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT			16
5036
+static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
33685037 {
3369
-	return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
5038
+	return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
5039
+}
5040
+#define A6XX_VPC_VS_PACK_UNK24__MASK				0x0f000000
5041
+#define A6XX_VPC_VS_PACK_UNK24__SHIFT				24
5042
+static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
5043
+{
5044
+	return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
5045
+}
5046
+
5047
+#define REG_A6XX_VPC_GS_PACK					0x00009302
5048
+#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5049
+#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT			0
5050
+static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
5051
+{
5052
+	return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
5053
+}
5054
+#define A6XX_VPC_GS_PACK_POSITIONLOC__MASK			0x0000ff00
5055
+#define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT			8
5056
+static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
5057
+{
5058
+	return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
5059
+}
5060
+#define A6XX_VPC_GS_PACK_PSIZELOC__MASK				0x00ff0000
5061
+#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT			16
5062
+static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
5063
+{
5064
+	return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
5065
+}
5066
+#define A6XX_VPC_GS_PACK_UNK24__MASK				0x0f000000
5067
+#define A6XX_VPC_GS_PACK_UNK24__SHIFT				24
5068
+static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
5069
+{
5070
+	return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
5071
+}
5072
+
5073
+#define REG_A6XX_VPC_DS_PACK					0x00009303
5074
+#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5075
+#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT			0
5076
+static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
5077
+{
5078
+	return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
5079
+}
5080
+#define A6XX_VPC_DS_PACK_POSITIONLOC__MASK			0x0000ff00
5081
+#define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT			8
5082
+static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
5083
+{
5084
+	return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
5085
+}
5086
+#define A6XX_VPC_DS_PACK_PSIZELOC__MASK				0x00ff0000
5087
+#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT			16
5088
+static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
5089
+{
5090
+	return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
5091
+}
5092
+#define A6XX_VPC_DS_PACK_UNK24__MASK				0x0f000000
5093
+#define A6XX_VPC_DS_PACK_UNK24__SHIFT				24
5094
+static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
5095
+{
5096
+	return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
33705097 }
33715098 
33725099 #define REG_A6XX_VPC_CNTL_0					0x00009304
....@@ -3376,7 +5103,19 @@
33765103 {
33775104 	return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
33785105 }
5106
+#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK				0x0000ff00
5107
+#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT			8
5108
+static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
5109
+{
5110
+	return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
5111
+}
33795112 #define A6XX_VPC_CNTL_0_VARYING					0x00010000
5113
+#define A6XX_VPC_CNTL_0_UNKLOC__MASK				0xff000000
5114
+#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT				24
5115
+static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
5116
+{
5117
+	return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
5118
+}
33805119 
33815120 #define REG_A6XX_VPC_SO_BUF_CNTL				0x00009305
33825121 #define A6XX_VPC_SO_BUF_CNTL_BUF0				0x00000001
....@@ -3384,12 +5123,65 @@
33845123 #define A6XX_VPC_SO_BUF_CNTL_BUF2				0x00000040
33855124 #define A6XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
33865125 #define A6XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
5126
+#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK			0x000f0000
5127
+#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT			16
5128
+static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
5129
+{
5130
+	return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
5131
+}
5132
+
5133
+#define REG_A6XX_VPC_SO_DISABLE					0x00009306
5134
+#define A6XX_VPC_SO_DISABLE_DISABLE				0x00000001
33875135 
33885136 #define REG_A6XX_VPC_UNKNOWN_9600				0x00009600
33895137 
5138
+#define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601
5139
+
33905140 #define REG_A6XX_VPC_UNKNOWN_9602				0x00009602
33915141 
5142
+#define REG_A6XX_VPC_UNKNOWN_9603				0x00009603
5143
+
5144
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0				0x00009604
5145
+
5146
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1				0x00009605
5147
+
5148
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2				0x00009606
5149
+
5150
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3				0x00009607
5151
+
5152
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4				0x00009608
5153
+
5154
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5				0x00009609
5155
+
5156
+#define REG_A6XX_PC_TESS_NUM_VERTEX				0x00009800
5157
+
33925158 #define REG_A6XX_PC_UNKNOWN_9801				0x00009801
5159
+#define A6XX_PC_UNKNOWN_9801_UNK0__MASK				0x000007ff
5160
+#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT			0
5161
+static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
5162
+{
5163
+	return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
5164
+}
5165
+#define A6XX_PC_UNKNOWN_9801_UNK13__MASK			0x00002000
5166
+#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT			13
5167
+static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
5168
+{
5169
+	return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
5170
+}
5171
+
5172
+#define REG_A6XX_PC_TESS_CNTL					0x00009802
5173
+#define A6XX_PC_TESS_CNTL_SPACING__MASK				0x00000003
5174
+#define A6XX_PC_TESS_CNTL_SPACING__SHIFT			0
5175
+static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
5176
+{
5177
+	return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
5178
+}
5179
+#define A6XX_PC_TESS_CNTL_OUTPUT__MASK				0x0000000c
5180
+#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT				2
5181
+static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
5182
+{
5183
+	return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
5184
+}
33935185 
33945186 #define REG_A6XX_PC_RESTART_INDEX				0x00009803
33955187 
....@@ -3397,36 +5189,244 @@
33975189 
33985190 #define REG_A6XX_PC_UNKNOWN_9805				0x00009805
33995191 
3400
-#define REG_A6XX_PC_UNKNOWN_9981				0x00009981
5192
+#define REG_A6XX_PC_PRIMID_PASSTHRU				0x00009806
5193
+
5194
+#define REG_A6XX_PC_DRAW_CMD					0x00009840
5195
+#define A6XX_PC_DRAW_CMD_STATE_ID__MASK				0x000000ff
5196
+#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT			0
5197
+static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
5198
+{
5199
+	return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
5200
+}
5201
+
5202
+#define REG_A6XX_PC_DISPATCH_CMD				0x00009841
5203
+#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
5204
+#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT			0
5205
+static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
5206
+{
5207
+	return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
5208
+}
5209
+
5210
+#define REG_A6XX_PC_EVENT_CMD					0x00009842
5211
+#define A6XX_PC_EVENT_CMD_STATE_ID__MASK			0x00ff0000
5212
+#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT			16
5213
+static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
5214
+{
5215
+	return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
5216
+}
5217
+#define A6XX_PC_EVENT_CMD_EVENT__MASK				0x0000007f
5218
+#define A6XX_PC_EVENT_CMD_EVENT__SHIFT				0
5219
+static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
5220
+{
5221
+	return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
5222
+}
5223
+
5224
+#define REG_A6XX_PC_POLYGON_MODE				0x00009981
5225
+#define A6XX_PC_POLYGON_MODE_MODE__MASK				0x00000003
5226
+#define A6XX_PC_POLYGON_MODE_MODE__SHIFT			0
5227
+static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
5228
+{
5229
+	return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
5230
+}
5231
+
5232
+#define REG_A6XX_PC_UNKNOWN_9980				0x00009980
34015233 
34025234 #define REG_A6XX_PC_PRIMITIVE_CNTL_0				0x00009b00
34035235 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART		0x00000001
34045236 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST		0x00000002
5237
+#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN	0x00000004
5238
+#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3				0x00000008
34055239 
3406
-#define REG_A6XX_PC_PRIMITIVE_CNTL_1				0x00009b01
3407
-#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK		0x0000007f
3408
-#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT		0
3409
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
5240
+#define REG_A6XX_PC_VS_OUT_CNTL					0x00009b01
5241
+#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5242
+#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5243
+static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
34105244 {
3411
-	return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
5245
+	return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5246
+}
5247
+#define A6XX_PC_VS_OUT_CNTL_PSIZE				0x00000100
5248
+#define A6XX_PC_VS_OUT_CNTL_LAYER				0x00000200
5249
+#define A6XX_PC_VS_OUT_CNTL_VIEW				0x00000400
5250
+#define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5251
+#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5252
+#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT			16
5253
+static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
5254
+{
5255
+	return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
34125256 }
34135257 
3414
-#define REG_A6XX_PC_UNKNOWN_9B06				0x00009b06
5258
+#define REG_A6XX_PC_GS_OUT_CNTL					0x00009b02
5259
+#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5260
+#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5261
+static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5262
+{
5263
+	return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5264
+}
5265
+#define A6XX_PC_GS_OUT_CNTL_PSIZE				0x00000100
5266
+#define A6XX_PC_GS_OUT_CNTL_LAYER				0x00000200
5267
+#define A6XX_PC_GS_OUT_CNTL_VIEW				0x00000400
5268
+#define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5269
+#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5270
+#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT			16
5271
+static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
5272
+{
5273
+	return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
5274
+}
5275
+
5276
+#define REG_A6XX_PC_PRIMITIVE_CNTL_3				0x00009b03
5277
+
5278
+#define REG_A6XX_PC_DS_OUT_CNTL					0x00009b04
5279
+#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5280
+#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5281
+static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5282
+{
5283
+	return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5284
+}
5285
+#define A6XX_PC_DS_OUT_CNTL_PSIZE				0x00000100
5286
+#define A6XX_PC_DS_OUT_CNTL_LAYER				0x00000200
5287
+#define A6XX_PC_DS_OUT_CNTL_VIEW				0x00000400
5288
+#define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5289
+#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5290
+#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT			16
5291
+static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
5292
+{
5293
+	return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
5294
+}
5295
+
5296
+#define REG_A6XX_PC_PRIMITIVE_CNTL_5				0x00009b05
5297
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK		0x000000ff
5298
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT		0
5299
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
5300
+{
5301
+	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
5302
+}
5303
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK		0x00007c00
5304
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT		10
5305
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
5306
+{
5307
+	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
5308
+}
5309
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK		0x00030000
5310
+#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT		16
5311
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
5312
+{
5313
+	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
5314
+}
5315
+#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK			0x00040000
5316
+#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT			18
5317
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
5318
+{
5319
+	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
5320
+}
5321
+
5322
+#define REG_A6XX_PC_PRIMITIVE_CNTL_6				0x00009b06
5323
+#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK		0x000007ff
5324
+#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT		0
5325
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
5326
+{
5327
+	return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
5328
+}
34155329 
34165330 #define REG_A6XX_PC_UNKNOWN_9B07				0x00009b07
5331
+
5332
+#define REG_A6XX_PC_UNKNOWN_9B08				0x00009b08
5333
+
5334
+#define REG_A6XX_PC_2D_EVENT_CMD				0x00009c00
5335
+#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK			0x0000007f
5336
+#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT			0
5337
+static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
5338
+{
5339
+	return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
5340
+}
5341
+#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
5342
+#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT			8
5343
+static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
5344
+{
5345
+	return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
5346
+}
5347
+
5348
+#define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00
5349
+
5350
+#define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01
34175351 
34185352 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO				0x00009e08
34195353 
34205354 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI				0x00009e09
34215355 
5356
+#define REG_A6XX_PC_TESSFACTOR_ADDR				0x00009e08
5357
+#define A6XX_PC_TESSFACTOR_ADDR__MASK				0xffffffff
5358
+#define A6XX_PC_TESSFACTOR_ADDR__SHIFT				0
5359
+static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
5360
+{
5361
+	return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
5362
+}
5363
+
5364
+#define REG_A6XX_PC_VSTREAM_CONTROL				0x00009e11
5365
+#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK			0x0000ffff
5366
+#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT			0
5367
+static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
5368
+{
5369
+	return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
5370
+}
5371
+#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK			0x003f0000
5372
+#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT			16
5373
+static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
5374
+{
5375
+	return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
5376
+}
5377
+#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK			0x07c00000
5378
+#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT			22
5379
+static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
5380
+{
5381
+	return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
5382
+}
5383
+
5384
+#define REG_A6XX_PC_BIN_PRIM_STRM				0x00009e12
5385
+#define A6XX_PC_BIN_PRIM_STRM__MASK				0xffffffff
5386
+#define A6XX_PC_BIN_PRIM_STRM__SHIFT				0
5387
+static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
5388
+{
5389
+	return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
5390
+}
5391
+
5392
+#define REG_A6XX_PC_BIN_DRAW_STRM				0x00009e14
5393
+#define A6XX_PC_BIN_DRAW_STRM__MASK				0xffffffff
5394
+#define A6XX_PC_BIN_DRAW_STRM__SHIFT				0
5395
+static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
5396
+{
5397
+	return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
5398
+}
5399
+
5400
+#define REG_A6XX_PC_PERFCTR_PC_SEL_0				0x00009e34
5401
+
5402
+#define REG_A6XX_PC_PERFCTR_PC_SEL_1				0x00009e35
5403
+
5404
+#define REG_A6XX_PC_PERFCTR_PC_SEL_2				0x00009e36
5405
+
5406
+#define REG_A6XX_PC_PERFCTR_PC_SEL_3				0x00009e37
5407
+
5408
+#define REG_A6XX_PC_PERFCTR_PC_SEL_4				0x00009e38
5409
+
5410
+#define REG_A6XX_PC_PERFCTR_PC_SEL_5				0x00009e39
5411
+
5412
+#define REG_A6XX_PC_PERFCTR_PC_SEL_6				0x00009e3a
5413
+
5414
+#define REG_A6XX_PC_PERFCTR_PC_SEL_7				0x00009e3b
5415
+
34225416 #define REG_A6XX_PC_UNKNOWN_9E72				0x00009e72
34235417 
34245418 #define REG_A6XX_VFD_CONTROL_0					0x0000a000
3425
-#define A6XX_VFD_CONTROL_0_VTXCNT__MASK				0x0000003f
3426
-#define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT			0
3427
-static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
5419
+#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK			0x0000003f
5420
+#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT			0
5421
+static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
34285422 {
3429
-	return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
5423
+	return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
5424
+}
5425
+#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK			0x00003f00
5426
+#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT			8
5427
+static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
5428
+{
5429
+	return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
34305430 }
34315431 
34325432 #define REG_A6XX_VFD_CONTROL_1					0x0000a001
....@@ -3450,19 +5450,25 @@
34505450 }
34515451 
34525452 #define REG_A6XX_VFD_CONTROL_2					0x0000a002
3453
-#define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK			0x000000ff
3454
-#define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT			0
3455
-static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
5453
+#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK		0x000000ff
5454
+#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT		0
5455
+static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
34565456 {
3457
-	return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
5457
+	return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
5458
+}
5459
+#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK		0x0000ff00
5460
+#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT		8
5461
+static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
5462
+{
5463
+	return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
34585464 }
34595465 
34605466 #define REG_A6XX_VFD_CONTROL_3					0x0000a003
3461
-#define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK			0x0000ff00
3462
-#define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT			8
3463
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
5467
+#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK		0x0000ff00
5468
+#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT		8
5469
+static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
34645470 {
3465
-	return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
5471
+	return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
34665472 }
34675473 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
34685474 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT			16
....@@ -3480,19 +5486,32 @@
34805486 #define REG_A6XX_VFD_CONTROL_4					0x0000a004
34815487 
34825488 #define REG_A6XX_VFD_CONTROL_5					0x0000a005
5489
+#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK			0x000000ff
5490
+#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT		0
5491
+static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5492
+{
5493
+	return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5494
+}
34835495 
34845496 #define REG_A6XX_VFD_CONTROL_6					0x0000a006
5497
+#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU			0x00000001
34855498 
34865499 #define REG_A6XX_VFD_MODE_CNTL					0x0000a007
34875500 #define A6XX_VFD_MODE_CNTL_BINNING_PASS				0x00000001
34885501 
34895502 #define REG_A6XX_VFD_UNKNOWN_A008				0x0000a008
34905503 
5504
+#define REG_A6XX_VFD_ADD_OFFSET					0x0000a009
5505
+#define A6XX_VFD_ADD_OFFSET_VERTEX				0x00000001
5506
+#define A6XX_VFD_ADD_OFFSET_INSTANCE				0x00000002
5507
+
34915508 #define REG_A6XX_VFD_INDEX_OFFSET				0x0000a00e
34925509 
34935510 #define REG_A6XX_VFD_INSTANCE_START_OFFSET			0x0000a00f
34945511 
34955512 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5513
+
5514
+static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
34965515 
34975516 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
34985517 
....@@ -3511,10 +5530,16 @@
35115530 {
35125531 	return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
35135532 }
5533
+#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK			0x0001ffe0
5534
+#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT			5
5535
+static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
5536
+{
5537
+	return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
5538
+}
35145539 #define A6XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
35155540 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
35165541 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT			20
3517
-static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
5542
+static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
35185543 {
35195544 	return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
35205545 }
....@@ -3547,12 +5572,44 @@
35475572 
35485573 #define REG_A6XX_SP_UNKNOWN_A0F8				0x0000a0f8
35495574 
3550
-#define REG_A6XX_SP_PRIMITIVE_CNTL				0x0000a802
3551
-#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK			0x0000001f
3552
-#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT			0
3553
-static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
5575
+#define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
5576
+#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5577
+#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
5578
+static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
35545579 {
3555
-	return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
5580
+	return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5581
+}
5582
+#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5583
+#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
5584
+static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5585
+{
5586
+	return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5587
+}
5588
+#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5589
+#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT			14
5590
+static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5591
+{
5592
+	return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5593
+}
5594
+#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5595
+#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
5596
+static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5597
+{
5598
+	return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
5599
+}
5600
+#define A6XX_SP_VS_CTRL_REG0_VARYING				0x00400000
5601
+#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE				0x00800000
5602
+#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x04000000
5603
+#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x80000000
5604
+
5605
+#define REG_A6XX_SP_VS_BRANCH_COND				0x0000a801
5606
+
5607
+#define REG_A6XX_SP_VS_PRIMITIVE_CNTL				0x0000a802
5608
+#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5609
+#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT			0
5610
+static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5611
+{
5612
+	return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
35565613 }
35575614 
35585615 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
....@@ -3611,34 +5668,7 @@
36115668 	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
36125669 }
36135670 
3614
-#define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
3615
-#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
3616
-#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
3617
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3618
-{
3619
-	return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3620
-}
3621
-#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
3622
-#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
3623
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3624
-{
3625
-	return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3626
-}
3627
-#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
3628
-#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT			14
3629
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3630
-{
3631
-	return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
3632
-}
3633
-#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
3634
-#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
3635
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3636
-{
3637
-	return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
3638
-}
3639
-#define A6XX_SP_VS_CTRL_REG0_VARYING				0x00400000
3640
-#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x04000000
3641
-#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x80000000
5671
+#define REG_A6XX_SP_UNKNOWN_A81B				0x0000a81b
36425672 
36435673 #define REG_A6XX_SP_VS_OBJ_START_LO				0x0000a81c
36445674 
....@@ -3647,6 +5677,10 @@
36475677 #define REG_A6XX_SP_VS_TEX_COUNT				0x0000a822
36485678 
36495679 #define REG_A6XX_SP_VS_CONFIG					0x0000a823
5680
+#define A6XX_SP_VS_CONFIG_BINDLESS_TEX				0x00000001
5681
+#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP				0x00000002
5682
+#define A6XX_SP_VS_CONFIG_BINDLESS_IBO				0x00000004
5683
+#define A6XX_SP_VS_CONFIG_BINDLESS_UBO				0x00000008
36505684 #define A6XX_SP_VS_CONFIG_ENABLED				0x00000100
36515685 #define A6XX_SP_VS_CONFIG_NTEX__MASK				0x0001fe00
36525686 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT				9
....@@ -3654,11 +5688,17 @@
36545688 {
36555689 	return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
36565690 }
3657
-#define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x01fe0000
5691
+#define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x003e0000
36585692 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT				17
36595693 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
36605694 {
36615695 	return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5696
+}
5697
+#define A6XX_SP_VS_CONFIG_NIBO__MASK				0x3fc00000
5698
+#define A6XX_SP_VS_CONFIG_NIBO__SHIFT				22
5699
+static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5700
+{
5701
+	return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
36625702 }
36635703 
36645704 #define REG_A6XX_SP_VS_INSTRLEN					0x0000a824
....@@ -3689,10 +5729,13 @@
36895729 	return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
36905730 }
36915731 #define A6XX_SP_HS_CTRL_REG0_VARYING				0x00400000
5732
+#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE				0x00800000
36925733 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE			0x04000000
36935734 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS				0x80000000
36945735 
36955736 #define REG_A6XX_SP_HS_UNKNOWN_A831				0x0000a831
5737
+
5738
+#define REG_A6XX_SP_HS_UNKNOWN_A833				0x0000a833
36965739 
36975740 #define REG_A6XX_SP_HS_OBJ_START_LO				0x0000a834
36985741 
....@@ -3701,6 +5744,10 @@
37015744 #define REG_A6XX_SP_HS_TEX_COUNT				0x0000a83a
37025745 
37035746 #define REG_A6XX_SP_HS_CONFIG					0x0000a83b
5747
+#define A6XX_SP_HS_CONFIG_BINDLESS_TEX				0x00000001
5748
+#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP				0x00000002
5749
+#define A6XX_SP_HS_CONFIG_BINDLESS_IBO				0x00000004
5750
+#define A6XX_SP_HS_CONFIG_BINDLESS_UBO				0x00000008
37045751 #define A6XX_SP_HS_CONFIG_ENABLED				0x00000100
37055752 #define A6XX_SP_HS_CONFIG_NTEX__MASK				0x0001fe00
37065753 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT				9
....@@ -3708,11 +5755,17 @@
37085755 {
37095756 	return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
37105757 }
3711
-#define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x01fe0000
5758
+#define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x003e0000
37125759 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT				17
37135760 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
37145761 {
37155762 	return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5763
+}
5764
+#define A6XX_SP_HS_CONFIG_NIBO__MASK				0x3fc00000
5765
+#define A6XX_SP_HS_CONFIG_NIBO__SHIFT				22
5766
+static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5767
+{
5768
+	return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
37165769 }
37175770 
37185771 #define REG_A6XX_SP_HS_INSTRLEN					0x0000a83c
....@@ -3743,8 +5796,75 @@
37435796 	return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
37445797 }
37455798 #define A6XX_SP_DS_CTRL_REG0_VARYING				0x00400000
5799
+#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE				0x00800000
37465800 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE			0x04000000
37475801 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS				0x80000000
5802
+
5803
+#define REG_A6XX_SP_DS_PRIMITIVE_CNTL				0x0000a842
5804
+#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5805
+#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT			0
5806
+static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5807
+{
5808
+	return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5809
+}
5810
+
5811
+static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5812
+
5813
+static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5814
+#define A6XX_SP_DS_OUT_REG_A_REGID__MASK			0x000000ff
5815
+#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
5816
+static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5817
+{
5818
+	return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5819
+}
5820
+#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5821
+#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT			8
5822
+static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5823
+{
5824
+	return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5825
+}
5826
+#define A6XX_SP_DS_OUT_REG_B_REGID__MASK			0x00ff0000
5827
+#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT			16
5828
+static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5829
+{
5830
+	return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5831
+}
5832
+#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5833
+#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT			24
5834
+static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5835
+{
5836
+	return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5837
+}
5838
+
5839
+static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5840
+
5841
+static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5842
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5843
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
5844
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5845
+{
5846
+	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5847
+}
5848
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5849
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT			8
5850
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5851
+{
5852
+	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5853
+}
5854
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5855
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT			16
5856
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5857
+{
5858
+	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5859
+}
5860
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5861
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT			24
5862
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5863
+{
5864
+	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5865
+}
5866
+
5867
+#define REG_A6XX_SP_DS_UNKNOWN_A85B				0x0000a85b
37485868 
37495869 #define REG_A6XX_SP_DS_OBJ_START_LO				0x0000a85c
37505870 
....@@ -3753,6 +5873,10 @@
37535873 #define REG_A6XX_SP_DS_TEX_COUNT				0x0000a862
37545874 
37555875 #define REG_A6XX_SP_DS_CONFIG					0x0000a863
5876
+#define A6XX_SP_DS_CONFIG_BINDLESS_TEX				0x00000001
5877
+#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP				0x00000002
5878
+#define A6XX_SP_DS_CONFIG_BINDLESS_IBO				0x00000004
5879
+#define A6XX_SP_DS_CONFIG_BINDLESS_UBO				0x00000008
37565880 #define A6XX_SP_DS_CONFIG_ENABLED				0x00000100
37575881 #define A6XX_SP_DS_CONFIG_NTEX__MASK				0x0001fe00
37585882 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT				9
....@@ -3760,11 +5884,17 @@
37605884 {
37615885 	return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
37625886 }
3763
-#define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x01fe0000
5887
+#define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x003e0000
37645888 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT				17
37655889 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
37665890 {
37675891 	return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5892
+}
5893
+#define A6XX_SP_DS_CONFIG_NIBO__MASK				0x3fc00000
5894
+#define A6XX_SP_DS_CONFIG_NIBO__SHIFT				22
5895
+static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5896
+{
5897
+	return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
37685898 }
37695899 
37705900 #define REG_A6XX_SP_DS_INSTRLEN					0x0000a864
....@@ -3795,10 +5925,83 @@
37955925 	return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
37965926 }
37975927 #define A6XX_SP_GS_CTRL_REG0_VARYING				0x00400000
5928
+#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE				0x00800000
37985929 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE			0x04000000
37995930 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS				0x80000000
38005931 
3801
-#define REG_A6XX_SP_GS_UNKNOWN_A871				0x0000a871
5932
+#define REG_A6XX_SP_GS_PRIM_SIZE				0x0000a871
5933
+
5934
+#define REG_A6XX_SP_GS_BRANCH_COND				0x0000a872
5935
+
5936
+#define REG_A6XX_SP_GS_PRIMITIVE_CNTL				0x0000a873
5937
+#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5938
+#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT			0
5939
+static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5940
+{
5941
+	return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5942
+}
5943
+#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5944
+#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT		6
5945
+static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5946
+{
5947
+	return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5948
+}
5949
+
5950
+static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5951
+
5952
+static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5953
+#define A6XX_SP_GS_OUT_REG_A_REGID__MASK			0x000000ff
5954
+#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
5955
+static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5956
+{
5957
+	return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5958
+}
5959
+#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5960
+#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT			8
5961
+static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5962
+{
5963
+	return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5964
+}
5965
+#define A6XX_SP_GS_OUT_REG_B_REGID__MASK			0x00ff0000
5966
+#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT			16
5967
+static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5968
+{
5969
+	return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5970
+}
5971
+#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5972
+#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT			24
5973
+static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5974
+{
5975
+	return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5976
+}
5977
+
5978
+static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5979
+
5980
+static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5981
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5982
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
5983
+static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5984
+{
5985
+	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5986
+}
5987
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5988
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT			8
5989
+static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5990
+{
5991
+	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5992
+}
5993
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5994
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT			16
5995
+static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5996
+{
5997
+	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5998
+}
5999
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
6000
+#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT			24
6001
+static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
6002
+{
6003
+	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
6004
+}
38026005 
38036006 #define REG_A6XX_SP_GS_OBJ_START_LO				0x0000a88d
38046007 
....@@ -3807,6 +6010,10 @@
38076010 #define REG_A6XX_SP_GS_TEX_COUNT				0x0000a893
38086011 
38096012 #define REG_A6XX_SP_GS_CONFIG					0x0000a894
6013
+#define A6XX_SP_GS_CONFIG_BINDLESS_TEX				0x00000001
6014
+#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP				0x00000002
6015
+#define A6XX_SP_GS_CONFIG_BINDLESS_IBO				0x00000004
6016
+#define A6XX_SP_GS_CONFIG_BINDLESS_UBO				0x00000008
38106017 #define A6XX_SP_GS_CONFIG_ENABLED				0x00000100
38116018 #define A6XX_SP_GS_CONFIG_NTEX__MASK				0x0001fe00
38126019 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT				9
....@@ -3814,11 +6021,17 @@
38146021 {
38156022 	return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
38166023 }
3817
-#define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x01fe0000
6024
+#define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x003e0000
38186025 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT				17
38196026 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
38206027 {
38216028 	return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
6029
+}
6030
+#define A6XX_SP_GS_CONFIG_NIBO__MASK				0x3fc00000
6031
+#define A6XX_SP_GS_CONFIG_NIBO__SHIFT				22
6032
+static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
6033
+{
6034
+	return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
38226035 }
38236036 
38246037 #define REG_A6XX_SP_GS_INSTRLEN					0x0000a895
....@@ -3881,8 +6094,13 @@
38816094 	return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
38826095 }
38836096 #define A6XX_SP_FS_CTRL_REG0_VARYING				0x00400000
6097
+#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE				0x00800000
38846098 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x04000000
38856099 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS				0x80000000
6100
+
6101
+#define REG_A6XX_SP_FS_BRANCH_COND				0x0000a981
6102
+
6103
+#define REG_A6XX_SP_UNKNOWN_A982				0x0000a982
38866104 
38876105 #define REG_A6XX_SP_FS_OBJ_START_LO				0x0000a983
38886106 
....@@ -3891,6 +6109,8 @@
38916109 #define REG_A6XX_SP_BLEND_CNTL					0x0000a989
38926110 #define A6XX_SP_BLEND_CNTL_ENABLED				0x00000001
38936111 #define A6XX_SP_BLEND_CNTL_UNK8					0x00000100
6112
+#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
6113
+#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
38946114 
38956115 #define REG_A6XX_SP_SRGB_CNTL					0x0000a98a
38966116 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0				0x00000001
....@@ -3953,11 +6173,24 @@
39536173 }
39546174 
39556175 #define REG_A6XX_SP_FS_OUTPUT_CNTL0				0x0000a98c
6176
+#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
39566177 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK		0x0000ff00
39576178 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT		8
39586179 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
39596180 {
39606181 	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
6182
+}
6183
+#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK		0x00ff0000
6184
+#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT		16
6185
+static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
6186
+{
6187
+	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
6188
+}
6189
+#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK		0xff000000
6190
+#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT		24
6191
+static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
6192
+{
6193
+	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
39616194 }
39626195 
39636196 #define REG_A6XX_SP_FS_OUTPUT_CNTL1				0x0000a98d
....@@ -3973,17 +6206,100 @@
39736206 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
39746207 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
39756208 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
3976
-static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
6209
+static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
39776210 {
39786211 	return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
39796212 }
39806213 #define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
39816214 #define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
3982
-#define A6XX_SP_FS_MRT_REG_COLOR_SRGB				0x00000400
6215
+
6216
+#define REG_A6XX_SP_FS_PREFETCH_CNTL				0x0000a99e
6217
+#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK			0x00000007
6218
+#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT			0
6219
+static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6220
+{
6221
+	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6222
+}
6223
+#define A6XX_SP_FS_PREFETCH_CNTL_UNK3				0x00000008
6224
+#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK			0x00000ff0
6225
+#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT			4
6226
+static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
6227
+{
6228
+	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6229
+}
6230
+
6231
+static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6232
+
6233
+static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6234
+#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK			0x0000007f
6235
+#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT			0
6236
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6237
+{
6238
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
6239
+}
6240
+#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK			0x00000780
6241
+#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT			7
6242
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6243
+{
6244
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
6245
+}
6246
+#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK			0x0000f800
6247
+#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT			11
6248
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
6249
+{
6250
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
6251
+}
6252
+#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK			0x003f0000
6253
+#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT			16
6254
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
6255
+{
6256
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
6257
+}
6258
+#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK			0x03c00000
6259
+#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT			22
6260
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
6261
+{
6262
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
6263
+}
6264
+#define A6XX_SP_FS_PREFETCH_CMD_HALF				0x04000000
6265
+#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK			0xf8000000
6266
+#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT			27
6267
+static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
6268
+{
6269
+	return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6270
+}
6271
+
6272
+static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6273
+
6274
+static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6275
+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK		0x000000ff
6276
+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT		0
6277
+static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6278
+{
6279
+	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6280
+}
6281
+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK		0x00ff0000
6282
+#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT		16
6283
+static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6284
+{
6285
+	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6286
+}
39836287 
39846288 #define REG_A6XX_SP_FS_TEX_COUNT				0x0000a9a7
39856289 
39866290 #define REG_A6XX_SP_UNKNOWN_A9A8				0x0000a9a8
6291
+
6292
+#define REG_A6XX_SP_CS_UNKNOWN_A9B1				0x0000a9b1
6293
+#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK		0x00000001
6294
+#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT		0
6295
+static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
6296
+{
6297
+	return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
6298
+}
6299
+
6300
+#define REG_A6XX_SP_CS_UNKNOWN_A9B3				0x0000a9b3
6301
+
6302
+#define REG_A6XX_SP_CS_TEX_COUNT				0x0000a9ba
39876303 
39886304 #define REG_A6XX_SP_FS_TEX_SAMP_LO				0x0000a9e0
39896305 
....@@ -4000,6 +6316,10 @@
40006316 #define REG_A6XX_SP_CS_TEX_CONST_LO				0x0000a9e6
40016317 
40026318 #define REG_A6XX_SP_CS_TEX_CONST_HI				0x0000a9e7
6319
+
6320
+static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6321
+
6322
+static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
40036323 
40046324 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
40056325 
....@@ -4038,6 +6358,7 @@
40386358 	return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
40396359 }
40406360 #define A6XX_SP_CS_CTRL_REG0_VARYING				0x00400000
6361
+#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE				0x00800000
40416362 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x04000000
40426363 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS				0x80000000
40436364 
....@@ -4045,11 +6366,46 @@
40456366 
40466367 #define REG_A6XX_SP_CS_OBJ_START_HI				0x0000a9b5
40476368 
6369
+#define REG_A6XX_SP_CS_CONFIG					0x0000a9bb
6370
+#define A6XX_SP_CS_CONFIG_BINDLESS_TEX				0x00000001
6371
+#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP				0x00000002
6372
+#define A6XX_SP_CS_CONFIG_BINDLESS_IBO				0x00000004
6373
+#define A6XX_SP_CS_CONFIG_BINDLESS_UBO				0x00000008
6374
+#define A6XX_SP_CS_CONFIG_ENABLED				0x00000100
6375
+#define A6XX_SP_CS_CONFIG_NTEX__MASK				0x0001fe00
6376
+#define A6XX_SP_CS_CONFIG_NTEX__SHIFT				9
6377
+static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6378
+{
6379
+	return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6380
+}
6381
+#define A6XX_SP_CS_CONFIG_NSAMP__MASK				0x003e0000
6382
+#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT				17
6383
+static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6384
+{
6385
+	return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6386
+}
6387
+#define A6XX_SP_CS_CONFIG_NIBO__MASK				0x3fc00000
6388
+#define A6XX_SP_CS_CONFIG_NIBO__SHIFT				22
6389
+static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6390
+{
6391
+	return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6392
+}
6393
+
40486394 #define REG_A6XX_SP_CS_INSTRLEN					0x0000a9bc
6395
+
6396
+#define REG_A6XX_SP_CS_IBO_LO					0x0000a9f2
6397
+
6398
+#define REG_A6XX_SP_CS_IBO_HI					0x0000a9f3
6399
+
6400
+#define REG_A6XX_SP_CS_IBO_COUNT				0x0000aa00
40496401 
40506402 #define REG_A6XX_SP_UNKNOWN_AB00				0x0000ab00
40516403 
40526404 #define REG_A6XX_SP_FS_CONFIG					0x0000ab04
6405
+#define A6XX_SP_FS_CONFIG_BINDLESS_TEX				0x00000001
6406
+#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP				0x00000002
6407
+#define A6XX_SP_FS_CONFIG_BINDLESS_IBO				0x00000004
6408
+#define A6XX_SP_FS_CONFIG_BINDLESS_UBO				0x00000008
40536409 #define A6XX_SP_FS_CONFIG_ENABLED				0x00000100
40546410 #define A6XX_SP_FS_CONFIG_NTEX__MASK				0x0001fe00
40556411 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT				9
....@@ -4057,22 +6413,62 @@
40576413 {
40586414 	return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
40596415 }
4060
-#define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x01fe0000
6416
+#define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x003e0000
40616417 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT				17
40626418 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
40636419 {
40646420 	return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
40656421 }
6422
+#define A6XX_SP_FS_CONFIG_NIBO__MASK				0x3fc00000
6423
+#define A6XX_SP_FS_CONFIG_NIBO__SHIFT				22
6424
+static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6425
+{
6426
+	return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6427
+}
40666428 
40676429 #define REG_A6XX_SP_FS_INSTRLEN					0x0000ab05
40686430 
6431
+static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6432
+
6433
+static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6434
+
6435
+#define REG_A6XX_SP_IBO_LO					0x0000ab1a
6436
+
6437
+#define REG_A6XX_SP_IBO_HI					0x0000ab1b
6438
+
6439
+#define REG_A6XX_SP_IBO_COUNT					0x0000ab20
6440
+
6441
+#define REG_A6XX_SP_2D_DST_FORMAT				0x0000acc0
6442
+#define A6XX_SP_2D_DST_FORMAT_NORM				0x00000001
6443
+#define A6XX_SP_2D_DST_FORMAT_SINT				0x00000002
6444
+#define A6XX_SP_2D_DST_FORMAT_UINT				0x00000004
6445
+#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK		0x000007f8
6446
+#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT		3
6447
+static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6448
+{
6449
+	return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6450
+}
6451
+#define A6XX_SP_2D_DST_FORMAT_SRGB				0x00000800
6452
+#define A6XX_SP_2D_DST_FORMAT_MASK__MASK			0x0000f000
6453
+#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT			12
6454
+static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6455
+{
6456
+	return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6457
+}
6458
+
40696459 #define REG_A6XX_SP_UNKNOWN_AE00				0x0000ae00
6460
+
6461
+#define REG_A6XX_SP_UNKNOWN_AE03				0x0000ae03
40706462 
40716463 #define REG_A6XX_SP_UNKNOWN_AE04				0x0000ae04
40726464 
40736465 #define REG_A6XX_SP_UNKNOWN_AE0F				0x0000ae0f
40746466 
6467
+#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR		0x0000b180
6468
+
40756469 #define REG_A6XX_SP_UNKNOWN_B182				0x0000b182
6470
+
6471
+#define REG_A6XX_SP_UNKNOWN_B183				0x0000b183
40766472 
40776473 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL				0x0000b300
40786474 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
....@@ -4091,16 +6487,122 @@
40916487 }
40926488 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
40936489 
6490
+#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR			0x0000b302
6491
+
40946492 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO		0x0000b302
40956493 
40966494 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI		0x0000b303
40976495 
4098
-#define REG_A6XX_SP_TP_UNKNOWN_B304				0x0000b304
6496
+#define REG_A6XX_SP_TP_SAMPLE_CONFIG				0x0000b304
6497
+#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0				0x00000001
6498
+#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE		0x00000002
6499
+
6500
+#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0			0x0000b305
6501
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
6502
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
6503
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6504
+{
6505
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6506
+}
6507
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
6508
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
6509
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6510
+{
6511
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6512
+}
6513
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
6514
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
6515
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6516
+{
6517
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6518
+}
6519
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
6520
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
6521
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6522
+{
6523
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6524
+}
6525
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
6526
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
6527
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6528
+{
6529
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6530
+}
6531
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
6532
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
6533
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6534
+{
6535
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6536
+}
6537
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
6538
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
6539
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6540
+{
6541
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6542
+}
6543
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
6544
+#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
6545
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6546
+{
6547
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6548
+}
6549
+
6550
+#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1			0x0000b306
6551
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
6552
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
6553
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6554
+{
6555
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6556
+}
6557
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
6558
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
6559
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6560
+{
6561
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6562
+}
6563
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
6564
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
6565
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6566
+{
6567
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6568
+}
6569
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
6570
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
6571
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6572
+{
6573
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6574
+}
6575
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
6576
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
6577
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6578
+{
6579
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6580
+}
6581
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
6582
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
6583
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6584
+{
6585
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6586
+}
6587
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
6588
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
6589
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6590
+{
6591
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6592
+}
6593
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
6594
+#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
6595
+static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6596
+{
6597
+	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6598
+}
6599
+
6600
+#define REG_A6XX_SP_TP_UNKNOWN_B309				0x0000b309
40996601 
41006602 #define REG_A6XX_SP_PS_2D_SRC_INFO				0x0000b4c0
41016603 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
41026604 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
4103
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
6605
+static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
41046606 {
41056607 	return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
41066608 }
....@@ -4117,14 +6619,65 @@
41176619 	return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
41186620 }
41196621 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS				0x00001000
6622
+#define A6XX_SP_PS_2D_SRC_INFO_SRGB				0x00002000
6623
+#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK			0x0000c000
6624
+#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT			14
6625
+static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6626
+{
6627
+	return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6628
+}
6629
+#define A6XX_SP_PS_2D_SRC_INFO_FILTER				0x00010000
6630
+#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE			0x00040000
6631
+#define A6XX_SP_PS_2D_SRC_INFO_UNK20				0x00100000
6632
+#define A6XX_SP_PS_2D_SRC_INFO_UNK22				0x00400000
6633
+
6634
+#define REG_A6XX_SP_PS_2D_SRC_SIZE				0x0000b4c1
6635
+#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK			0x00007fff
6636
+#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT			0
6637
+static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6638
+{
6639
+	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6640
+}
6641
+#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK			0x3fff8000
6642
+#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT			15
6643
+static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6644
+{
6645
+	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6646
+}
41206647 
41216648 #define REG_A6XX_SP_PS_2D_SRC_LO				0x0000b4c2
41226649 
41236650 #define REG_A6XX_SP_PS_2D_SRC_HI				0x0000b4c3
41246651 
6652
+#define REG_A6XX_SP_PS_2D_SRC					0x0000b4c2
6653
+
6654
+#define REG_A6XX_SP_PS_2D_SRC_PITCH				0x0000b4c4
6655
+#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK			0x01fffe00
6656
+#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT			9
6657
+static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6658
+{
6659
+	return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6660
+}
6661
+
41256662 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO				0x0000b4ca
41266663 
41276664 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI				0x0000b4cb
6665
+
6666
+#define REG_A6XX_SP_PS_2D_SRC_FLAGS				0x0000b4ca
6667
+
6668
+#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH			0x0000b4cc
6669
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK		0x000007ff
6670
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT		0
6671
+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
6672
+{
6673
+	return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
6674
+}
6675
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK		0x003ff800
6676
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT	11
6677
+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
6678
+{
6679
+	return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
6680
+}
41286681 
41296682 #define REG_A6XX_SP_UNKNOWN_B600				0x0000b600
41306683 
....@@ -4137,6 +6690,7 @@
41376690 {
41386691 	return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
41396692 }
6693
+#define A6XX_HLSQ_VS_CNTL_ENABLED				0x00000100
41406694 
41416695 #define REG_A6XX_HLSQ_HS_CNTL					0x0000b801
41426696 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK			0x000000ff
....@@ -4145,6 +6699,7 @@
41456699 {
41466700 	return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
41476701 }
6702
+#define A6XX_HLSQ_HS_CNTL_ENABLED				0x00000100
41486703 
41496704 #define REG_A6XX_HLSQ_DS_CNTL					0x0000b802
41506705 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK			0x000000ff
....@@ -4153,6 +6708,7 @@
41536708 {
41546709 	return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
41556710 }
6711
+#define A6XX_HLSQ_DS_CNTL_ENABLED				0x00000100
41566712 
41576713 #define REG_A6XX_HLSQ_GS_CNTL					0x0000b803
41586714 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK			0x000000ff
....@@ -4161,6 +6717,15 @@
41616717 {
41626718 	return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
41636719 }
6720
+#define A6XX_HLSQ_GS_CNTL_ENABLED				0x00000100
6721
+
6722
+#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD			0x0000b820
6723
+
6724
+#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR		0x0000b821
6725
+
6726
+#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA			0x0000b823
6727
+
6728
+#define REG_A6XX_HLSQ_UNKNOWN_B980				0x0000b980
41646729 
41656730 #define REG_A6XX_HLSQ_CONTROL_1_REG				0x0000b982
41666731 
....@@ -4183,16 +6748,52 @@
41836748 {
41846749 	return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
41856750 }
6751
+#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
6752
+#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT			24
6753
+static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
6754
+{
6755
+	return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
6756
+}
41866757 
41876758 #define REG_A6XX_HLSQ_CONTROL_3_REG				0x0000b984
4188
-#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK		0x000000ff
4189
-#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT		0
4190
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
6759
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
6760
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
6761
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
41916762 {
4192
-	return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
6763
+	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
6764
+}
6765
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
6766
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT		8
6767
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
6768
+{
6769
+	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
6770
+}
6771
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
6772
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT	16
6773
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
6774
+{
6775
+	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
6776
+}
6777
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
6778
+#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT	24
6779
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
6780
+{
6781
+	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
41936782 }
41946783 
41956784 #define REG_A6XX_HLSQ_CONTROL_4_REG				0x0000b985
6785
+#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
6786
+#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
6787
+static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
6788
+{
6789
+	return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
6790
+}
6791
+#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
6792
+#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT		8
6793
+static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
6794
+{
6795
+	return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
6796
+}
41966797 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
41976798 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT		16
41986799 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
....@@ -4207,6 +6808,15 @@
42076808 }
42086809 
42096810 #define REG_A6XX_HLSQ_CONTROL_5_REG				0x0000b986
6811
+
6812
+#define REG_A6XX_HLSQ_CS_CNTL					0x0000b987
6813
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK			0x000000ff
6814
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT			0
6815
+static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6816
+{
6817
+	return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6818
+}
6819
+#define A6XX_HLSQ_CS_CNTL_ENABLED				0x00000100
42106820 
42116821 #define REG_A6XX_HLSQ_CS_NDRANGE_0				0x0000b990
42126822 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
....@@ -4308,13 +6918,77 @@
43086918 	return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
43096919 }
43106920 
6921
+#define REG_A6XX_HLSQ_CS_UNKNOWN_B998				0x0000b998
6922
+
43116923 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X				0x0000b999
43126924 
43136925 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000b99a
43146926 
43156927 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000b99b
43166928 
4317
-#define REG_A6XX_HLSQ_UPDATE_CNTL				0x0000bb08
6929
+#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD			0x0000b9a0
6930
+
6931
+#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR		0x0000b9a1
6932
+
6933
+#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA			0x0000b9a3
6934
+
6935
+static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6936
+
6937
+static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6938
+
6939
+#define REG_A6XX_HLSQ_DRAW_CMD					0x0000bb00
6940
+#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK			0x000000ff
6941
+#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT			0
6942
+static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
6943
+{
6944
+	return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
6945
+}
6946
+
6947
+#define REG_A6XX_HLSQ_DISPATCH_CMD				0x0000bb01
6948
+#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
6949
+#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT			0
6950
+static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
6951
+{
6952
+	return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
6953
+}
6954
+
6955
+#define REG_A6XX_HLSQ_EVENT_CMD					0x0000bb02
6956
+#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK			0x00ff0000
6957
+#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT			16
6958
+static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
6959
+{
6960
+	return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
6961
+}
6962
+#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK				0x0000007f
6963
+#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT			0
6964
+static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
6965
+{
6966
+	return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
6967
+}
6968
+
6969
+#define REG_A6XX_HLSQ_INVALIDATE_CMD				0x0000bb08
6970
+#define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE			0x00000001
6971
+#define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE			0x00000002
6972
+#define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE			0x00000004
6973
+#define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE			0x00000008
6974
+#define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE			0x00000010
6975
+#define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE			0x00000020
6976
+#define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO				0x00000040
6977
+#define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO			0x00000080
6978
+#define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST		0x00080000
6979
+#define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST		0x00000100
6980
+#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK		0x00003e00
6981
+#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT		9
6982
+static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
6983
+{
6984
+	return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
6985
+}
6986
+#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK		0x0007c000
6987
+#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT		14
6988
+static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
6989
+{
6990
+	return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
6991
+}
43186992 
43196993 #define REG_A6XX_HLSQ_FS_CNTL					0x0000bb10
43206994 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK			0x000000ff
....@@ -4323,14 +6997,66 @@
43236997 {
43246998 	return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
43256999 }
7000
+#define A6XX_HLSQ_FS_CNTL_ENABLED				0x00000100
43267001 
4327
-#define REG_A6XX_HLSQ_UNKNOWN_BB11				0x0000bb11
7002
+#define REG_A6XX_HLSQ_SHARED_CONSTS				0x0000bb11
7003
+#define A6XX_HLSQ_SHARED_CONSTS_ENABLE				0x00000001
7004
+
7005
+static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7006
+
7007
+static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7008
+
7009
+#define REG_A6XX_HLSQ_2D_EVENT_CMD				0x0000bd80
7010
+#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
7011
+#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT			8
7012
+static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
7013
+{
7014
+	return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
7015
+}
7016
+#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK			0x0000007f
7017
+#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT			0
7018
+static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
7019
+{
7020
+	return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
7021
+}
43287022 
43297023 #define REG_A6XX_HLSQ_UNKNOWN_BE00				0x0000be00
43307024 
43317025 #define REG_A6XX_HLSQ_UNKNOWN_BE01				0x0000be01
43327026 
43337027 #define REG_A6XX_HLSQ_UNKNOWN_BE04				0x0000be04
7028
+
7029
+#define REG_A6XX_CP_EVENT_START					0x0000d600
7030
+#define A6XX_CP_EVENT_START_STATE_ID__MASK			0x000000ff
7031
+#define A6XX_CP_EVENT_START_STATE_ID__SHIFT			0
7032
+static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7033
+{
7034
+	return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7035
+}
7036
+
7037
+#define REG_A6XX_CP_EVENT_END					0x0000d601
7038
+#define A6XX_CP_EVENT_END_STATE_ID__MASK			0x000000ff
7039
+#define A6XX_CP_EVENT_END_STATE_ID__SHIFT			0
7040
+static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
7041
+{
7042
+	return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
7043
+}
7044
+
7045
+#define REG_A6XX_CP_2D_EVENT_START				0x0000d700
7046
+#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK			0x000000ff
7047
+#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT			0
7048
+static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
7049
+{
7050
+	return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
7051
+}
7052
+
7053
+#define REG_A6XX_CP_2D_EVENT_END				0x0000d701
7054
+#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK			0x000000ff
7055
+#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT			0
7056
+static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
7057
+{
7058
+	return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
7059
+}
43347060 
43357061 #define REG_A6XX_TEX_SAMP_0					0x00000000
43367062 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
....@@ -4378,6 +7104,7 @@
43787104 }
43797105 
43807106 #define REG_A6XX_TEX_SAMP_1					0x00000001
7107
+#define A6XX_TEX_SAMP_1_UNK0					0x00000001
43817108 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
43827109 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT			1
43837110 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
....@@ -4401,11 +7128,18 @@
44017128 }
44027129 
44037130 #define REG_A6XX_TEX_SAMP_2					0x00000002
4404
-#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xfffffff0
4405
-#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			4
7131
+#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK			0x00000003
7132
+#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT			0
7133
+static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7134
+{
7135
+	return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7136
+}
7137
+#define A6XX_TEX_SAMP_2_CHROMA_LINEAR				0x00000020
7138
+#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
7139
+#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			7
44067140 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
44077141 {
4408
-	return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
7142
+	return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
44097143 }
44107144 
44117145 #define REG_A6XX_TEX_SAMP_3					0x00000003
....@@ -4448,9 +7182,17 @@
44487182 {
44497183 	return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
44507184 }
7185
+#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X			0x00010000
7186
+#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y			0x00040000
7187
+#define A6XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
7188
+#define A6XX_TEX_CONST_0_SAMPLES__SHIFT				20
7189
+static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7190
+{
7191
+	return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7192
+}
44517193 #define A6XX_TEX_CONST_0_FMT__MASK				0x3fc00000
44527194 #define A6XX_TEX_CONST_0_FMT__SHIFT				22
4453
-static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
7195
+static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
44547196 {
44557197 	return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
44567198 }
....@@ -4476,11 +7218,12 @@
44767218 }
44777219 
44787220 #define REG_A6XX_TEX_CONST_2					0x00000002
4479
-#define A6XX_TEX_CONST_2_FETCHSIZE__MASK			0x0000000f
4480
-#define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT			0
4481
-static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
7221
+#define A6XX_TEX_CONST_2_UNK4					0x00000010
7222
+#define A6XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
7223
+#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
7224
+static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
44827225 {
4483
-	return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
7226
+	return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
44847227 }
44857228 #define A6XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
44867229 #define A6XX_TEX_CONST_2_PITCH__SHIFT				7
....@@ -4494,6 +7237,7 @@
44947237 {
44957238 	return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
44967239 }
7240
+#define A6XX_TEX_CONST_2_UNK31					0x80000000
44977241 
44987242 #define REG_A6XX_TEX_CONST_3					0x00000003
44997243 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
....@@ -4502,6 +7246,13 @@
45027246 {
45037247 	return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
45047248 }
7249
+#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
7250
+#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT			23
7251
+static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7252
+{
7253
+	return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7254
+}
7255
+#define A6XX_TEX_CONST_3_TILE_ALL				0x08000000
45057256 #define A6XX_TEX_CONST_3_FLAG					0x10000000
45067257 
45077258 #define REG_A6XX_TEX_CONST_4					0x00000004
....@@ -4527,6 +7278,12 @@
45277278 }
45287279 
45297280 #define REG_A6XX_TEX_CONST_6					0x00000006
7281
+#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK			0xffffff00
7282
+#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT			8
7283
+static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7284
+{
7285
+	return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7286
+}
45307287 
45317288 #define REG_A6XX_TEX_CONST_7					0x00000007
45327289 #define A6XX_TEX_CONST_7_FLAG_LO__MASK				0xffffffe0
....@@ -4537,16 +7294,40 @@
45377294 }
45387295 
45397296 #define REG_A6XX_TEX_CONST_8					0x00000008
4540
-#define A6XX_TEX_CONST_8_BASE_HI__MASK				0x0001ffff
4541
-#define A6XX_TEX_CONST_8_BASE_HI__SHIFT				0
4542
-static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val)
7297
+#define A6XX_TEX_CONST_8_FLAG_HI__MASK				0x0001ffff
7298
+#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT				0
7299
+static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
45437300 {
4544
-	return ((val) << A6XX_TEX_CONST_8_BASE_HI__SHIFT) & A6XX_TEX_CONST_8_BASE_HI__MASK;
7301
+	return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
45457302 }
45467303 
45477304 #define REG_A6XX_TEX_CONST_9					0x00000009
7305
+#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7306
+#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7307
+static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7308
+{
7309
+	return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7310
+}
45487311 
45497312 #define REG_A6XX_TEX_CONST_10					0x0000000a
7313
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK		0x0000007f
7314
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT		0
7315
+static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7316
+{
7317
+	return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7318
+}
7319
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK		0x00000f00
7320
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT		8
7321
+static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7322
+{
7323
+	return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7324
+}
7325
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK		0x0000f000
7326
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT		12
7327
+static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7328
+{
7329
+	return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7330
+}
45507331 
45517332 #define REG_A6XX_TEX_CONST_11					0x0000000b
45527333 
....@@ -4558,5 +7339,351 @@
45587339 
45597340 #define REG_A6XX_TEX_CONST_15					0x0000000f
45607341 
7342
+#define REG_A6XX_IBO_0						0x00000000
7343
+#define A6XX_IBO_0_TILE_MODE__MASK				0x00000003
7344
+#define A6XX_IBO_0_TILE_MODE__SHIFT				0
7345
+static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
7346
+{
7347
+	return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
7348
+}
7349
+#define A6XX_IBO_0_FMT__MASK					0x3fc00000
7350
+#define A6XX_IBO_0_FMT__SHIFT					22
7351
+static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
7352
+{
7353
+	return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
7354
+}
7355
+
7356
+#define REG_A6XX_IBO_1						0x00000001
7357
+#define A6XX_IBO_1_WIDTH__MASK					0x00007fff
7358
+#define A6XX_IBO_1_WIDTH__SHIFT					0
7359
+static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
7360
+{
7361
+	return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
7362
+}
7363
+#define A6XX_IBO_1_HEIGHT__MASK					0x3fff8000
7364
+#define A6XX_IBO_1_HEIGHT__SHIFT				15
7365
+static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
7366
+{
7367
+	return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
7368
+}
7369
+
7370
+#define REG_A6XX_IBO_2						0x00000002
7371
+#define A6XX_IBO_2_UNK4						0x00000010
7372
+#define A6XX_IBO_2_PITCH__MASK					0x1fffff80
7373
+#define A6XX_IBO_2_PITCH__SHIFT					7
7374
+static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
7375
+{
7376
+	return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
7377
+}
7378
+#define A6XX_IBO_2_TYPE__MASK					0x60000000
7379
+#define A6XX_IBO_2_TYPE__SHIFT					29
7380
+static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
7381
+{
7382
+	return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
7383
+}
7384
+#define A6XX_IBO_2_UNK31					0x80000000
7385
+
7386
+#define REG_A6XX_IBO_3						0x00000003
7387
+#define A6XX_IBO_3_ARRAY_PITCH__MASK				0x00003fff
7388
+#define A6XX_IBO_3_ARRAY_PITCH__SHIFT				0
7389
+static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
7390
+{
7391
+	return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
7392
+}
7393
+#define A6XX_IBO_3_UNK27					0x08000000
7394
+#define A6XX_IBO_3_FLAG						0x10000000
7395
+
7396
+#define REG_A6XX_IBO_4						0x00000004
7397
+#define A6XX_IBO_4_BASE_LO__MASK				0xffffffff
7398
+#define A6XX_IBO_4_BASE_LO__SHIFT				0
7399
+static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
7400
+{
7401
+	return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
7402
+}
7403
+
7404
+#define REG_A6XX_IBO_5						0x00000005
7405
+#define A6XX_IBO_5_BASE_HI__MASK				0x0001ffff
7406
+#define A6XX_IBO_5_BASE_HI__SHIFT				0
7407
+static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
7408
+{
7409
+	return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
7410
+}
7411
+#define A6XX_IBO_5_DEPTH__MASK					0x3ffe0000
7412
+#define A6XX_IBO_5_DEPTH__SHIFT					17
7413
+static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
7414
+{
7415
+	return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
7416
+}
7417
+
7418
+#define REG_A6XX_IBO_6						0x00000006
7419
+
7420
+#define REG_A6XX_IBO_7						0x00000007
7421
+
7422
+#define REG_A6XX_IBO_8						0x00000008
7423
+
7424
+#define REG_A6XX_IBO_9						0x00000009
7425
+#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7426
+#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7427
+static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7428
+{
7429
+	return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7430
+}
7431
+
7432
+#define REG_A6XX_IBO_10						0x0000000a
7433
+#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK			0x0000007f
7434
+#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT			0
7435
+static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
7436
+{
7437
+	return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
7438
+}
7439
+
7440
+#define REG_A6XX_UBO_0						0x00000000
7441
+#define A6XX_UBO_0_BASE_LO__MASK				0xffffffff
7442
+#define A6XX_UBO_0_BASE_LO__SHIFT				0
7443
+static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
7444
+{
7445
+	return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
7446
+}
7447
+
7448
+#define REG_A6XX_UBO_1						0x00000001
7449
+#define A6XX_UBO_1_BASE_HI__MASK				0x0001ffff
7450
+#define A6XX_UBO_1_BASE_HI__SHIFT				0
7451
+static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
7452
+{
7453
+	return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
7454
+}
7455
+#define A6XX_UBO_1_SIZE__MASK					0xfffe0000
7456
+#define A6XX_UBO_1_SIZE__SHIFT					17
7457
+static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
7458
+{
7459
+	return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
7460
+}
7461
+
7462
+#define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00001140
7463
+
7464
+#define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00001148
7465
+
7466
+#define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00001540
7467
+
7468
+#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00001541
7469
+
7470
+#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00001542
7471
+
7472
+#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00001543
7473
+
7474
+#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00001544
7475
+
7476
+#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00001545
7477
+
7478
+#define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00001572
7479
+
7480
+#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00001573
7481
+
7482
+#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00001574
7483
+
7484
+#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00001575
7485
+
7486
+#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00001576
7487
+
7488
+#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00001577
7489
+
7490
+#define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000015a4
7491
+
7492
+#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000015a5
7493
+
7494
+#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000015a6
7495
+
7496
+#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000015a7
7497
+
7498
+#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000015a8
7499
+
7500
+#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000015a9
7501
+
7502
+#define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000015d6
7503
+
7504
+#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000015d7
7505
+
7506
+#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000015d8
7507
+
7508
+#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000015d9
7509
+
7510
+#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000015da
7511
+
7512
+#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000015db
7513
+
7514
+#define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x00000000
7515
+
7516
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00000000
7517
+#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK		0x000000ff
7518
+#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT		0
7519
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
7520
+{
7521
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
7522
+}
7523
+#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK	0x0000ff00
7524
+#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT	8
7525
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
7526
+{
7527
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
7528
+}
7529
+
7530
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00000001
7531
+
7532
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00000002
7533
+
7534
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00000003
7535
+
7536
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00000004
7537
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
7538
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
7539
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
7540
+{
7541
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
7542
+}
7543
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
7544
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT		12
7545
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
7546
+{
7547
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
7548
+}
7549
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
7550
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT		28
7551
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
7552
+{
7553
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
7554
+}
7555
+
7556
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00000005
7557
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
7558
+#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT		24
7559
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
7560
+{
7561
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
7562
+}
7563
+
7564
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00000008
7565
+
7566
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00000009
7567
+
7568
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0000000a
7569
+
7570
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0000000b
7571
+
7572
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0000000c
7573
+
7574
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0000000d
7575
+
7576
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0000000e
7577
+
7578
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0000000f
7579
+
7580
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000010
7581
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
7582
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
7583
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
7584
+{
7585
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
7586
+}
7587
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
7588
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT		4
7589
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
7590
+{
7591
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
7592
+}
7593
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
7594
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT		8
7595
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
7596
+{
7597
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
7598
+}
7599
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
7600
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT		12
7601
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
7602
+{
7603
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
7604
+}
7605
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
7606
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT		16
7607
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
7608
+{
7609
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
7610
+}
7611
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
7612
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT		20
7613
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
7614
+{
7615
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
7616
+}
7617
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
7618
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT		24
7619
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
7620
+{
7621
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
7622
+}
7623
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
7624
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT		28
7625
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
7626
+{
7627
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
7628
+}
7629
+
7630
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000011
7631
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
7632
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
7633
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
7634
+{
7635
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
7636
+}
7637
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
7638
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT		4
7639
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
7640
+{
7641
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
7642
+}
7643
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
7644
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT		8
7645
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
7646
+{
7647
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
7648
+}
7649
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
7650
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT		12
7651
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
7652
+{
7653
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
7654
+}
7655
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
7656
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT		16
7657
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
7658
+{
7659
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
7660
+}
7661
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
7662
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT		20
7663
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
7664
+{
7665
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
7666
+}
7667
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
7668
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT		24
7669
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
7670
+{
7671
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
7672
+}
7673
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
7674
+#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT		28
7675
+static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
7676
+{
7677
+	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
7678
+}
7679
+
7680
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000002f
7681
+
7682
+#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000030
7683
+
7684
+#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0			0x00000001
7685
+
7686
+#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1			0x00000002
7687
+
45617688 
45627689 #endif /* A6XX_XML */