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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/msm/adreno/a4xx.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -91,6 +93,7 @@
9193 	RB4_R32G32B32A32_FLOAT = 60,
9294 	RB4_R32G32B32A32_UINT = 61,
9395 	RB4_R32G32B32A32_SINT = 62,
96
+	RB4_NONE = 255,
9497 };
9598 
9699 enum a4xx_tile_mode {
....@@ -161,6 +164,7 @@
161164 	VFMT4_2_10_10_10_UNORM = 61,
162165 	VFMT4_2_10_10_10_SINT = 62,
163166 	VFMT4_2_10_10_10_SNORM = 63,
167
+	VFMT4_NONE = 255,
164168 };
165169 
166170 enum a4xx_tex_fmt {
....@@ -248,14 +252,7 @@
248252 	TFMT4_ASTC_10x10 = 122,
249253 	TFMT4_ASTC_12x10 = 123,
250254 	TFMT4_ASTC_12x12 = 124,
251
-};
252
-
253
-enum a4xx_tex_fetchsize {
254
-	TFETCH4_1_BYTE = 0,
255
-	TFETCH4_2_BYTE = 1,
256
-	TFETCH4_4_BYTE = 2,
257
-	TFETCH4_8_BYTE = 3,
258
-	TFETCH4_16_BYTE = 4,
255
+	TFMT4_NONE = 255,
259256 };
260257 
261258 enum a4xx_depth_format {
....@@ -949,10 +946,12 @@
949946 }
950947 
951948 #define REG_A4XX_RB_RENDER_CONTROL2				0x000020a3
952
-#define A4XX_RB_RENDER_CONTROL2_XCOORD				0x00000001
953
-#define A4XX_RB_RENDER_CONTROL2_YCOORD				0x00000002
954
-#define A4XX_RB_RENDER_CONTROL2_ZCOORD				0x00000004
955
-#define A4XX_RB_RENDER_CONTROL2_WCOORD				0x00000008
949
+#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK		0x0000000f
950
+#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT		0
951
+static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
952
+{
953
+	return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
954
+}
956955 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK			0x00000010
957956 #define A4XX_RB_RENDER_CONTROL2_FACENESS			0x00000020
958957 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID			0x00000040
....@@ -963,7 +962,10 @@
963962 	return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
964963 }
965964 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR			0x00000800
966
-#define A4XX_RB_RENDER_CONTROL2_VARYING				0x00001000
965
+#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL			0x00001000
966
+#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID		0x00002000
967
+#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE			0x00004000
968
+#define A4XX_RB_RENDER_CONTROL2_SIZE				0x00008000
967969 
968970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
969971 
....@@ -1877,10 +1879,6 @@
18771879 
18781880 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI				0x00000115
18791881 
1880
-#define REG_A4XX_RBBM_PERFCTR_TP_0_LO				0x00000114
1881
-
1882
-#define REG_A4XX_RBBM_PERFCTR_TP_0_HI				0x00000115
1883
-
18841882 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO				0x00000116
18851883 
18861884 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI				0x00000117
....@@ -2061,8 +2059,6 @@
20612059 
20622060 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1			0x0000009a
20632061 
2064
-#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO				0x00000168
2065
-
20662062 #define REG_A4XX_RBBM_PERFCTR_CTL				0x00000170
20672063 
20682064 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0				0x00000171
....@@ -2210,8 +2206,18 @@
22102206 {
22112207 	return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
22122208 }
2213
-#define A4XX_CP_PROTECT_REG_TRAP_WRITE				0x20000000
2214
-#define A4XX_CP_PROTECT_REG_TRAP_READ				0x40000000
2209
+#define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK			0x20000000
2210
+#define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT			29
2211
+static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
2212
+{
2213
+	return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
2214
+}
2215
+#define A4XX_CP_PROTECT_REG_TRAP_READ__MASK			0x40000000
2216
+#define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT			30
2217
+static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
2218
+{
2219
+	return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK;
2220
+}
22152221 
22162222 #define REG_A4XX_CP_PROTECT_CTRL				0x00000250
22172223 
....@@ -3151,8 +3157,9 @@
31513157 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
31523158 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000
31533159 
3154
-#define REG_A4XX_GRAS_CLEAR_CNTL				0x00002003
3155
-#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR			0x00000001
3160
+#define REG_A4XX_GRAS_CNTL					0x00002003
3161
+#define A4XX_GRAS_CNTL_IJ_PERSP					0x00000001
3162
+#define A4XX_GRAS_CNTL_IJ_LINEAR				0x00000002
31563163 
31573164 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ				0x00002004
31583165 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK			0x000003ff
....@@ -3524,14 +3531,44 @@
35243531 }
35253532 
35263533 #define REG_A4XX_HLSQ_CONTROL_3_REG				0x000023c3
3527
-#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK			0x000000ff
3528
-#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT			0
3529
-static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
3534
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
3535
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
3536
+static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
35303537 {
3531
-	return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
3538
+	return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
3539
+}
3540
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
3541
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT		8
3542
+static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
3543
+{
3544
+	return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
3545
+}
3546
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
3547
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT	16
3548
+static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
3549
+{
3550
+	return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
3551
+}
3552
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
3553
+#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT	24
3554
+static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
3555
+{
3556
+	return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
35323557 }
35333558 
35343559 #define REG_A4XX_HLSQ_CONTROL_4_REG				0x000023c4
3560
+#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
3561
+#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
3562
+static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
3563
+{
3564
+	return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
3565
+}
3566
+#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
3567
+#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT		8
3568
+static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
3569
+{
3570
+	return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
3571
+}
35353572 
35363573 #define REG_A4XX_HLSQ_VS_CONTROL_REG				0x000023c5
35373574 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
....@@ -4115,11 +4152,11 @@
41154152 }
41164153 
41174154 #define REG_A4XX_TEX_CONST_2					0x00000002
4118
-#define A4XX_TEX_CONST_2_FETCHSIZE__MASK			0x0000000f
4119
-#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT			0
4120
-static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
4155
+#define A4XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
4156
+#define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
4157
+static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
41214158 {
4122
-	return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
4159
+	return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
41234160 }
41244161 #define A4XX_TEX_CONST_2_PITCH__MASK				0x3ffffe00
41254162 #define A4XX_TEX_CONST_2_PITCH__SHIFT				9