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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/meson/meson_venc.c
....@@ -1,30 +1,18 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2016 BayLibre, SAS
34  * Author: Neil Armstrong <narmstrong@baylibre.com>
45  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License as
8
- * published by the Free Software Foundation; either version 2 of the
9
- * License, or (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful, but
12
- * WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
- * General Public License for more details.
15
- *
16
- * You should have received a copy of the GNU General Public License
17
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
186  */
197 
20
-#include <linux/kernel.h>
21
-#include <linux/module.h>
22
-#include <drm/drmP.h>
8
+#include <linux/export.h>
9
+
10
+#include <drm/drm_modes.h>
11
+
2312 #include "meson_drv.h"
13
+#include "meson_registers.h"
2414 #include "meson_venc.h"
2515 #include "meson_vpp.h"
26
-#include "meson_vclk.h"
27
-#include "meson_registers.h"
2816 
2917 /**
3018  * DOC: Video Encoder
....@@ -73,7 +61,9 @@
7361 /* HHI Registers */
7462 #define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */
7563 #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
64
+#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbb offset in data sheet */
7665 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
66
+#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */
7767 #define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
7868 
7969 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
....@@ -202,7 +192,7 @@
202192 		.hso_end = 129,
203193 		.vso_even = 3,
204194 		.vso_odd = 260,
205
-		.macv_max_amp = 0x810b,
195
+		.macv_max_amp = 0xb,
206196 		.video_prog_mode = 0xf0,
207197 		.video_mode = 0x8,
208198 		.sch_adjust = 0x20,
....@@ -222,7 +212,7 @@
222212 		.hso_end = 129,
223213 		.vso_even = 3,
224214 		.vso_odd = 260,
225
-		.macv_max_amp = 8107,
215
+		.macv_max_amp = 0x7,
226216 		.video_prog_mode = 0xff,
227217 		.video_mode = 0x13,
228218 		.sch_adjust = 0x28,
....@@ -698,6 +688,132 @@
698688 	},
699689 };
700690 
691
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
692
+	.encp = {
693
+		.dvi_settings = 0x1,
694
+		.video_mode = 0x4040,
695
+		.video_mode_adv = 0x8,
696
+		/* video_sync_mode */
697
+		/* video_yc_dly */
698
+		/* video_rgb_ctrl */
699
+		.video_filt_ctrl = 0x1000,
700
+		.video_filt_ctrl_present = true,
701
+		/* video_ofld_voav_ofst */
702
+		.yfp1_htime = 140,
703
+		.yfp2_htime = 140+3840,
704
+		.max_pxcnt = 3840+1660-1,
705
+		.hspuls_begin = 2156+1920,
706
+		.hspuls_end = 44,
707
+		.hspuls_switch = 44,
708
+		.vspuls_begin = 140,
709
+		.vspuls_end = 2059+1920,
710
+		.vspuls_bline = 0,
711
+		.vspuls_eline = 4,
712
+		.havon_begin = 148,
713
+		.havon_end = 3987,
714
+		.vavon_bline = 89,
715
+		.vavon_eline = 2248,
716
+		/* eqpuls_begin */
717
+		/* eqpuls_end */
718
+		/* eqpuls_bline */
719
+		/* eqpuls_eline */
720
+		.hso_begin = 44,
721
+		.hso_end = 2156+1920,
722
+		.vso_begin = 2100+1920,
723
+		.vso_end = 2164+1920,
724
+		.vso_bline = 51,
725
+		.vso_eline = 53,
726
+		.vso_eline_present = true,
727
+		/* sy_val */
728
+		/* sy2_val */
729
+		.max_lncnt = 2249,
730
+	},
731
+};
732
+
733
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
734
+	.encp = {
735
+		.dvi_settings = 0x1,
736
+		.video_mode = 0x4040,
737
+		.video_mode_adv = 0x8,
738
+		/* video_sync_mode */
739
+		/* video_yc_dly */
740
+		/* video_rgb_ctrl */
741
+		.video_filt_ctrl = 0x1000,
742
+		.video_filt_ctrl_present = true,
743
+		/* video_ofld_voav_ofst */
744
+		.yfp1_htime = 140,
745
+		.yfp2_htime = 140+3840,
746
+		.max_pxcnt = 3840+1440-1,
747
+		.hspuls_begin = 2156+1920,
748
+		.hspuls_end = 44,
749
+		.hspuls_switch = 44,
750
+		.vspuls_begin = 140,
751
+		.vspuls_end = 2059+1920,
752
+		.vspuls_bline = 0,
753
+		.vspuls_eline = 4,
754
+		.havon_begin = 148,
755
+		.havon_end = 3987,
756
+		.vavon_bline = 89,
757
+		.vavon_eline = 2248,
758
+		/* eqpuls_begin */
759
+		/* eqpuls_end */
760
+		/* eqpuls_bline */
761
+		/* eqpuls_eline */
762
+		.hso_begin = 44,
763
+		.hso_end = 2156+1920,
764
+		.vso_begin = 2100+1920,
765
+		.vso_end = 2164+1920,
766
+		.vso_bline = 51,
767
+		.vso_eline = 53,
768
+		.vso_eline_present = true,
769
+		/* sy_val */
770
+		/* sy2_val */
771
+		.max_lncnt = 2249,
772
+	},
773
+};
774
+
775
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
776
+	.encp = {
777
+		.dvi_settings = 0x1,
778
+		.video_mode = 0x4040,
779
+		.video_mode_adv = 0x8,
780
+		/* video_sync_mode */
781
+		/* video_yc_dly */
782
+		/* video_rgb_ctrl */
783
+		.video_filt_ctrl = 0x1000,
784
+		.video_filt_ctrl_present = true,
785
+		/* video_ofld_voav_ofst */
786
+		.yfp1_htime = 140,
787
+		.yfp2_htime = 140+3840,
788
+		.max_pxcnt = 3840+560-1,
789
+		.hspuls_begin = 2156+1920,
790
+		.hspuls_end = 44,
791
+		.hspuls_switch = 44,
792
+		.vspuls_begin = 140,
793
+		.vspuls_end = 2059+1920,
794
+		.vspuls_bline = 0,
795
+		.vspuls_eline = 4,
796
+		.havon_begin = 148,
797
+		.havon_end = 3987,
798
+		.vavon_bline = 89,
799
+		.vavon_eline = 2248,
800
+		/* eqpuls_begin */
801
+		/* eqpuls_end */
802
+		/* eqpuls_bline */
803
+		/* eqpuls_eline */
804
+		.hso_begin = 44,
805
+		.hso_end = 2156+1920,
806
+		.vso_begin = 2100+1920,
807
+		.vso_end = 2164+1920,
808
+		.vso_bline = 51,
809
+		.vso_eline = 53,
810
+		.vso_eline_present = true,
811
+		/* sy_val */
812
+		/* sy2_val */
813
+		.max_lncnt = 2249,
814
+	},
815
+};
816
+
701817 struct meson_hdmi_venc_vic_mode {
702818 	unsigned int vic;
703819 	union meson_hdmi_venc_mode *mode;
....@@ -719,6 +835,11 @@
719835 	{ 34, &meson_hdmi_encp_mode_1080p30 },
720836 	{ 31, &meson_hdmi_encp_mode_1080p50 },
721837 	{ 16, &meson_hdmi_encp_mode_1080p60 },
838
+	{ 93, &meson_hdmi_encp_mode_2160p24 },
839
+	{ 94, &meson_hdmi_encp_mode_2160p25 },
840
+	{ 95, &meson_hdmi_encp_mode_2160p30 },
841
+	{ 96, &meson_hdmi_encp_mode_2160p25 },
842
+	{ 97, &meson_hdmi_encp_mode_2160p30 },
722843 	{ 0, NULL}, /* sentinel */
723844 };
724845 
....@@ -825,7 +946,9 @@
825946 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
826947 
827948 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
828
-			      struct drm_display_mode *mode)
949
+			      unsigned int ycrcb_map,
950
+			      bool yuv420_mode,
951
+			      const struct drm_display_mode *mode)
829952 {
830953 	union meson_hdmi_venc_mode *vmode = NULL;
831954 	union meson_hdmi_venc_mode vmode_dmt;
....@@ -855,6 +978,14 @@
855978 	unsigned int eof_lines;
856979 	unsigned int sof_lines;
857980 	unsigned int vsync_lines;
981
+	u32 reg;
982
+
983
+	/* Use VENCI for 480i and 576i and double HDMI pixels */
984
+	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
985
+		hdmi_repeat = true;
986
+		use_enci = true;
987
+		venc_hdmi_latency = 1;
988
+	}
858989 
859990 	if (meson_venc_hdmi_supported_vic(vic)) {
860991 		vmode = meson_venc_hdmi_get_vic_vmode(vic);
....@@ -867,13 +998,7 @@
867998 	} else {
868999 		meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
8691000 		vmode = &vmode_dmt;
870
-	}
871
-
872
-	/* Use VENCI for 480i and 576i and double HDMI pixels */
873
-	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
874
-		hdmi_repeat = true;
875
-		use_enci = true;
876
-		venc_hdmi_latency = 1;
1001
+		use_enci = false;
8771002 	}
8781003 
8791004 	/* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
....@@ -926,8 +1051,11 @@
9261051 		unsigned int lines_f1;
9271052 
9281053 		/* CVBS Filter settings */
929
-		writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
930
-		writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1054
+		writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
1055
+			       priv->io_base + _REG(ENCI_CFILT_CTRL));
1056
+		writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
1057
+			       ENCI_CFILT_CMPT_CB_DLY(1),
1058
+			       priv->io_base + _REG(ENCI_CFILT_CTRL2));
9311059 
9321060 		/* Digital Video Select : Interlace, clk27 clk, external */
9331061 		writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
....@@ -949,8 +1077,9 @@
9491077 				priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
9501078 
9511079 		/* Macrovision max amplitude change */
952
-		writel_relaxed(vmode->enci.macv_max_amp,
953
-				priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1080
+		writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
1081
+			       ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp),
1082
+			       priv->io_base + _REG(ENCI_MACV_MAX_AMP));
9541083 
9551084 		/* Video mode */
9561085 		writel_relaxed(vmode->enci.video_prog_mode,
....@@ -958,7 +1087,8 @@
9581087 		writel_relaxed(vmode->enci.video_mode,
9591088 				priv->io_base + _REG(ENCI_VIDEO_MODE));
9601089 
961
-		/* Advanced Video Mode :
1090
+		/*
1091
+		 * Advanced Video Mode :
9621092 		 * Demux shifting 0x2
9631093 		 * Blank line end at line17/22
9641094 		 * High bandwidth Luma Filter
....@@ -966,7 +1096,10 @@
9661096 		 * Bypass luma low pass filter
9671097 		 * No macrovision on CSYNC
9681098 		 */
969
-		writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1099
+		writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
1100
+			       ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
1101
+			       ENCI_VIDEO_MODE_ADV_YBW_HIGH,
1102
+			       priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
9701103 
9711104 		writel(vmode->enci.sch_adjust,
9721105 				priv->io_base + _REG(ENCI_VIDEO_SCH));
....@@ -982,8 +1115,17 @@
9821115 		/* UNreset Interlaced TV Encoder */
9831116 		writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
9841117 
985
-		/* Enable Vfifo2vd, Y_Cb_Y_Cr select */
986
-		writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1118
+		/*
1119
+		 * Enable Vfifo2vd and set Y_Cb_Y_Cr:
1120
+		 * Corresponding value:
1121
+		 * Y  => 00 or 10
1122
+		 * Cb => 01
1123
+		 * Cr => 11
1124
+		 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
1125
+		 */
1126
+		writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
1127
+			       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
1128
+			       priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
9871129 
9881130 		/* Timings */
9891131 		writel_relaxed(vmode->enci.pixel_start,
....@@ -1005,7 +1147,8 @@
10051147 		meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
10061148 
10071149 		/* Interlace video enable */
1008
-		writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1150
+		writel_relaxed(ENCI_VIDEO_EN_ENABLE,
1151
+			       priv->io_base + _REG(ENCI_VIDEO_EN));
10091152 
10101153 		lines_f0 = mode->vtotal >> 1;
10111154 		lines_f1 = lines_f0 + 1;
....@@ -1252,7 +1395,8 @@
12521395 		writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
12531396 
12541397 		/* Set DE signal’s polarity is active high */
1255
-		writel_bits_relaxed(BIT(14), BIT(14),
1398
+		writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH,
1399
+				    ENCP_VIDEO_MODE_DE_V_HIGH,
12561400 				    priv->io_base + _REG(ENCP_VIDEO_MODE));
12571401 
12581402 		/* Program DE timing */
....@@ -1371,13 +1515,39 @@
13711515 		meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
13721516 	}
13731517 
1374
-	writel_relaxed((use_enci ? 1 : 2) |
1375
-		       (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1376
-		       (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1377
-		       4 << 5 |
1378
-		       (venc_repeat ? 1 << 8 : 0) |
1379
-		       (hdmi_repeat ? 1 << 12 : 0),
1380
-		       priv->io_base + _REG(VPU_HDMI_SETTING));
1518
+	/* Set VPU HDMI setting */
1519
+	/* Select ENCP or ENCI data to HDMI */
1520
+	if (use_enci)
1521
+		reg = VPU_HDMI_ENCI_DATA_TO_HDMI;
1522
+	else
1523
+		reg = VPU_HDMI_ENCP_DATA_TO_HDMI;
1524
+
1525
+	/* Invert polarity of HSYNC from VENC */
1526
+	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1527
+		reg |= VPU_HDMI_INV_HSYNC;
1528
+
1529
+	/* Invert polarity of VSYNC from VENC */
1530
+	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1531
+		reg |= VPU_HDMI_INV_VSYNC;
1532
+
1533
+	/* Output data format */
1534
+	reg |= ycrcb_map;
1535
+
1536
+	/*
1537
+	 * Write rate to the async FIFO between VENC and HDMI.
1538
+	 * One write every 2 wr_clk.
1539
+	 */
1540
+	if (venc_repeat || yuv420_mode)
1541
+		reg |= VPU_HDMI_WR_RATE(2);
1542
+
1543
+	/*
1544
+	 * Read rate to the async FIFO between VENC and HDMI.
1545
+	 * One read every 2 wr_clk.
1546
+	 */
1547
+	if (hdmi_repeat)
1548
+		reg |= VPU_HDMI_RD_RATE(2);
1549
+
1550
+	writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
13811551 
13821552 	priv->venc.hdmi_repeat = hdmi_repeat;
13831553 	priv->venc.venc_repeat = venc_repeat;
....@@ -1390,12 +1560,17 @@
13901560 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
13911561 			       struct meson_cvbs_enci_mode *mode)
13921562 {
1563
+	u32 reg;
1564
+
13931565 	if (mode->mode_tag == priv->venc.current_mode)
13941566 		return;
13951567 
13961568 	/* CVBS Filter settings */
1397
-	writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1398
-	writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1569
+	writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
1570
+		       priv->io_base + _REG(ENCI_CFILT_CTRL));
1571
+	writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
1572
+		       ENCI_CFILT_CMPT_CB_DLY(1),
1573
+		       priv->io_base + _REG(ENCI_CFILT_CTRL2));
13991574 
14001575 	/* Digital Video Select : Interlace, clk27 clk, external */
14011576 	writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
....@@ -1417,8 +1592,9 @@
14171592 			priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
14181593 
14191594 	/* Macrovision max amplitude change */
1420
-	writel_relaxed(0x8100 + mode->macv_max_amp,
1421
-			priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1595
+	writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
1596
+		       ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp),
1597
+		       priv->io_base + _REG(ENCI_MACV_MAX_AMP));
14221598 
14231599 	/* Video mode */
14241600 	writel_relaxed(mode->video_prog_mode,
....@@ -1426,7 +1602,8 @@
14261602 	writel_relaxed(mode->video_mode,
14271603 			priv->io_base + _REG(ENCI_VIDEO_MODE));
14281604 
1429
-	/* Advanced Video Mode :
1605
+	/*
1606
+	 * Advanced Video Mode :
14301607 	 * Demux shifting 0x2
14311608 	 * Blank line end at line17/22
14321609 	 * High bandwidth Luma Filter
....@@ -1434,7 +1611,10 @@
14341611 	 * Bypass luma low pass filter
14351612 	 * No macrovision on CSYNC
14361613 	 */
1437
-	writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1614
+	writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
1615
+		       ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
1616
+		       ENCI_VIDEO_MODE_ADV_YBW_HIGH,
1617
+		       priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
14381618 
14391619 	writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
14401620 
....@@ -1466,16 +1646,50 @@
14661646 	/* UNreset Interlaced TV Encoder */
14671647 	writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
14681648 
1469
-	/* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1470
-	writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1649
+	/*
1650
+	 * Enable Vfifo2vd and set Y_Cb_Y_Cr:
1651
+	 * Corresponding value:
1652
+	 * Y  => 00 or 10
1653
+	 * Cb => 01
1654
+	 * Cr => 11
1655
+	 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
1656
+	 */
1657
+	writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
1658
+		       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
1659
+		       priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
14711660 
14721661 	/* Power UP Dacs */
14731662 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
14741663 
14751664 	/* Video Upsampling */
1476
-	writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1477
-	writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1478
-	writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1665
+	/*
1666
+	 * CTRL0, CTRL1 and CTRL2:
1667
+	 * Filter0: input data sample every 2 cloks
1668
+	 * Filter1: filtering and upsample enable
1669
+	 */
1670
+	reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN |
1671
+		VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN;
1672
+
1673
+	/*
1674
+	 * Upsample CTRL0:
1675
+	 * Interlace High Bandwidth Luma
1676
+	 */
1677
+	writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
1678
+		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1679
+
1680
+	/*
1681
+	 * Upsample CTRL1:
1682
+	 * Interlace Pb
1683
+	 */
1684
+	writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
1685
+		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1686
+
1687
+	/*
1688
+	 * Upsample CTRL2:
1689
+	 * Interlace R
1690
+	 */
1691
+	writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
1692
+		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
14791693 
14801694 	/* Select Interlace Y DACs */
14811695 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
....@@ -1489,14 +1703,16 @@
14891703 	meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
14901704 
14911705 	/* Enable ENCI FIFO */
1492
-	writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1706
+	writel_relaxed(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
1707
+		       priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
14931708 
14941709 	/* Select ENCI DACs 0, 1, 4, and 5 */
14951710 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
14961711 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
14971712 
14981713 	/* Interlace video enable */
1499
-	writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1714
+	writel_relaxed(ENCI_VIDEO_EN_ENABLE,
1715
+		       priv->io_base + _REG(ENCI_VIDEO_EN));
15001716 
15011717 	/* Configure Video Saturation / Contrast / Brightness / Hue */
15021718 	writel_relaxed(mode->video_saturation,
....@@ -1509,7 +1725,8 @@
15091725 			priv->io_base + _REG(ENCI_VIDEO_HUE));
15101726 
15111727 	/* Enable DAC0 Filter */
1512
-	writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1728
+	writel_relaxed(VENC_VDAC_DAC0_FILT_CTRL0_EN,
1729
+		       priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
15131730 	writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
15141731 
15151732 	/* 0 in Macrovision register 0 */
....@@ -1530,7 +1747,8 @@
15301747 
15311748 void meson_venc_enable_vsync(struct meson_drm *priv)
15321749 {
1533
-	writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
1750
+	writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
1751
+		       priv->io_base + _REG(VENC_INTCTRL));
15341752 	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
15351753 }
15361754 
....@@ -1543,8 +1761,13 @@
15431761 void meson_venc_init(struct meson_drm *priv)
15441762 {
15451763 	/* Disable CVBS VDAC */
1546
-	regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1547
-	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1764
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
1765
+		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
1766
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);
1767
+	} else {
1768
+		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1769
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1770
+	}
15481771 
15491772 	/* Power Down Dacs */
15501773 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
....@@ -1553,7 +1776,8 @@
15531776 	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
15541777 
15551778 	/* Disable HDMI */
1556
-	writel_bits_relaxed(0x3, 0,
1779
+	writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
1780
+			    VPU_HDMI_ENCP_DATA_TO_HDMI, 0,
15571781 			    priv->io_base + _REG(VPU_HDMI_SETTING));
15581782 
15591783 	/* Disable all encoders */