forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/i915/i915_suspend.c
....@@ -24,24 +24,35 @@
2424 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2525 */
2626
27
-#include <drm/drmP.h>
28
-#include <drm/i915_drm.h>
29
-#include "intel_drv.h"
27
+#include "display/intel_fbc.h"
28
+#include "display/intel_gmbus.h"
29
+#include "display/intel_vga.h"
30
+
31
+#include "i915_drv.h"
3032 #include "i915_reg.h"
33
+#include "i915_suspend.h"
3134
3235 static void i915_save_display(struct drm_i915_private *dev_priv)
3336 {
37
+ struct pci_dev *pdev = dev_priv->drm.pdev;
38
+
3439 /* Display arbitration control */
3540 if (INTEL_GEN(dev_priv) <= 4)
3641 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
3742
38
- /* save FBC interval */
39
- if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
40
- dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
43
+ if (IS_GEN(dev_priv, 4))
44
+ pci_read_config_word(pdev, GCDGMBUS,
45
+ &dev_priv->regfile.saveGCDGMBUS);
4146 }
4247
4348 static void i915_restore_display(struct drm_i915_private *dev_priv)
4449 {
50
+ struct pci_dev *pdev = dev_priv->drm.pdev;
51
+
52
+ if (IS_GEN(dev_priv, 4))
53
+ pci_write_config_word(pdev, GCDGMBUS,
54
+ dev_priv->regfile.saveGCDGMBUS);
55
+
4556 /* Display arbitration */
4657 if (INTEL_GEN(dev_priv) <= 4)
4758 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
....@@ -49,45 +60,29 @@
4960 /* only restore FBC info on the platform that supports FBC*/
5061 intel_fbc_global_disable(dev_priv);
5162
52
- /* restore FBC interval */
53
- if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
54
- I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
63
+ intel_vga_redisable(dev_priv);
5564
56
- i915_redisable_vga(dev_priv);
65
+ intel_gmbus_reset(dev_priv);
5766 }
5867
5968 int i915_save_state(struct drm_i915_private *dev_priv)
6069 {
61
- struct pci_dev *pdev = dev_priv->drm.pdev;
6270 int i;
63
-
64
- mutex_lock(&dev_priv->drm.struct_mutex);
6571
6672 i915_save_display(dev_priv);
6773
68
- if (IS_GEN4(dev_priv))
69
- pci_read_config_word(pdev, GCDGMBUS,
70
- &dev_priv->regfile.saveGCDGMBUS);
71
-
72
- /* Cache mode state */
73
- if (INTEL_GEN(dev_priv) < 7)
74
- dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
75
-
76
- /* Memory Arbitration state */
77
- dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
78
-
7974 /* Scratch space */
80
- if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
75
+ if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
8176 for (i = 0; i < 7; i++) {
8277 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
8378 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
8479 }
8580 for (i = 0; i < 3; i++)
8681 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
87
- } else if (IS_GEN2(dev_priv)) {
82
+ } else if (IS_GEN(dev_priv, 2)) {
8883 for (i = 0; i < 7; i++)
8984 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
90
- } else if (HAS_GMCH_DISPLAY(dev_priv)) {
85
+ } else if (HAS_GMCH(dev_priv)) {
9186 for (i = 0; i < 16; i++) {
9287 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
9388 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
....@@ -95,44 +90,28 @@
9590 for (i = 0; i < 3; i++)
9691 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
9792 }
98
-
99
- mutex_unlock(&dev_priv->drm.struct_mutex);
10093
10194 return 0;
10295 }
10396
10497 int i915_restore_state(struct drm_i915_private *dev_priv)
10598 {
106
- struct pci_dev *pdev = dev_priv->drm.pdev;
10799 int i;
108100
109
- mutex_lock(&dev_priv->drm.struct_mutex);
110
-
111
- if (IS_GEN4(dev_priv))
112
- pci_write_config_word(pdev, GCDGMBUS,
113
- dev_priv->regfile.saveGCDGMBUS);
114101 i915_restore_display(dev_priv);
115102
116
- /* Cache mode state */
117
- if (INTEL_GEN(dev_priv) < 7)
118
- I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
119
- 0xffff0000);
120
-
121
- /* Memory arbitration state */
122
- I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
123
-
124103 /* Scratch space */
125
- if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
104
+ if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
126105 for (i = 0; i < 7; i++) {
127106 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
128107 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
129108 }
130109 for (i = 0; i < 3; i++)
131110 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
132
- } else if (IS_GEN2(dev_priv)) {
111
+ } else if (IS_GEN(dev_priv, 2)) {
133112 for (i = 0; i < 7; i++)
134113 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
135
- } else if (HAS_GMCH_DISPLAY(dev_priv)) {
114
+ } else if (HAS_GMCH(dev_priv)) {
136115 for (i = 0; i < 16; i++) {
137116 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
138117 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
....@@ -140,10 +119,6 @@
140119 for (i = 0; i < 3; i++)
141120 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
142121 }
143
-
144
- mutex_unlock(&dev_priv->drm.struct_mutex);
145
-
146
- intel_i2c_reset(dev_priv);
147122
148123 return 0;
149124 }