modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
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@@ -1,18 +1,14 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (c) 2016 Linaro Limited.
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  * Copyright (c) 2014-2016 Hisilicon Limited.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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  */
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 #ifndef __DW_DSI_REG_H__
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 #define __DW_DSI_REG_H__
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 #define MASK(x)				(BIT(x) - 1)
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-
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+#define DEFAULT_MAX_TX_ESC_CLK	(10 * 1000000UL)	//for hikey960
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 /*
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  * regs
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  */
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@@ -56,6 +52,50 @@
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 #define VID_VACTIVE_LINES       0x60  /* Vertical resolution */
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 #define VID_PKT_SIZE            0x3C  /* Video packet size */
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 #define VID_MODE_CFG            0x38  /* Video mode configuration */
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+/***************************for hikey960***********************************/
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+#define GEN_HDR			0x6c
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+#define GEN_HDATA(data)		(((data) & 0xffff) << 8)
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+#define GEN_HDATA_MASK		(0xffff << 8)
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+#define GEN_HTYPE(type)		(((type) & 0xff) << 0)
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+#define GEN_HTYPE_MASK		0xff
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+#define GEN_PLD_DATA		0x70
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+#define CMD_PKT_STATUS		0x74
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+#define GEN_CMD_EMPTY		BIT(0)
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+#define GEN_CMD_FULL		BIT(1)
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+#define GEN_PLD_W_EMPTY		BIT(2)
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+#define GEN_PLD_W_FULL		BIT(3)
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+#define GEN_PLD_R_EMPTY		BIT(4)
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+#define GEN_PLD_R_FULL		BIT(5)
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+#define GEN_RD_CMD_BUSY		BIT(6)
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+#define CMD_MODE_CFG		0x68
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+#define MAX_RD_PKT_SIZE_LP	BIT(24)
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+#define DCS_LW_TX_LP		BIT(19)
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+#define DCS_SR_0P_TX_LP		BIT(18)
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+#define DCS_SW_1P_TX_LP		BIT(17)
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+#define DCS_SW_0P_TX_LP		BIT(16)
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+#define GEN_LW_TX_LP		BIT(14)
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+#define GEN_SR_2P_TX_LP		BIT(13)
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+#define GEN_SR_1P_TX_LP		BIT(12)
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+#define GEN_SR_0P_TX_LP		BIT(11)
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+#define GEN_SW_2P_TX_LP		BIT(10)
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+#define GEN_SW_1P_TX_LP		BIT(9)
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+#define GEN_SW_0P_TX_LP		BIT(8)
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+#define EN_ACK_RQST		BIT(1)
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+#define EN_TEAR_FX		BIT(0)
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+#define CMD_PKT_STATUS_TIMEOUT_US	20000
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+#define CMD_MODE_ALL_LP		(MAX_RD_PKT_SIZE_LP | \
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+				 DCS_LW_TX_LP | \
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+				 DCS_SR_0P_TX_LP | \
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+				 DCS_SW_1P_TX_LP | \
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+				 DCS_SW_0P_TX_LP | \
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+				 GEN_LW_TX_LP | \
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+				 GEN_SR_2P_TX_LP | \
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+				 GEN_SR_1P_TX_LP | \
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+				 GEN_SR_0P_TX_LP | \
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+				 GEN_SW_2P_TX_LP | \
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+				 GEN_SW_1P_TX_LP | \
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+				 GEN_SW_0P_TX_LP)
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+/***************************for hikey960***********************************/
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 #define PHY_TMR_CFG             0x9C  /* Data lanes timing configuration */
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 #define BTA_TO_CNT              0x8C  /* Response timeout definition */
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 #define PHY_TMR_LPCLK_CFG       0x98  /* clock lane timing configuration */