forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /* Hisilicon Hibmc SoC drm driver
23 *
34 * Based on the bochs drm driver.
....@@ -8,12 +9,6 @@
89 * Rongrong Zou <zourongrong@huawei.com>
910 * Rongrong Zou <zourongrong@gmail.com>
1011 * Jianhua Li <lijianhua@huawei.com>
11
- *
12
- * This program is free software; you can redistribute it and/or modify
13
- * it under the terms of the GNU General Public License as published by
14
- * the Free Software Foundation; either version 2 of the License, or
15
- * (at your option) any later version.
16
- *
1712 */
1813
1914 #ifndef HIBMC_DRM_HW_H
....@@ -73,6 +68,12 @@
7368
7469 #define HIBMC_CRT_DISP_CTL 0x80200
7570
71
+#define HIBMC_CRT_DISP_CTL_DPMS(x) ((x) << 30)
72
+#define HIBMC_CRT_DISP_CTL_DPMS_MASK 0xc0000000
73
+
74
+#define HIBMC_CRT_DPMS_ON 0
75
+#define HIBMC_CRT_DPMS_OFF 3
76
+
7677 #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25)
7778 #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000
7879
....@@ -89,6 +90,9 @@
8990
9091 #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8)
9192 #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100
93
+
94
+#define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3)
95
+#define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x08
9296
9397 #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2)
9498 #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4
....@@ -175,6 +179,7 @@
175179 #define CRT_PLL1_HS_74MHZ 0x23941dc2
176180 #define CRT_PLL1_HS_80MHZ 0x23941001
177181 #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2
182
+#define CRT_PLL1_HS_106MHZ 0x237C1641
178183 #define CRT_PLL1_HS_108MHZ 0x23b41b01
179184 #define CRT_PLL1_HS_162MHZ 0x23480681
180185 #define CRT_PLL1_HS_148MHZ 0x23541dc2
....@@ -187,10 +192,13 @@
187192 #define CRT_PLL2_HS_78MHZ 0x50E147AE
188193 #define CRT_PLL2_HS_74MHZ 0x602B6AE7
189194 #define CRT_PLL2_HS_80MHZ 0x70000000
195
+#define CRT_PLL2_HS_106MHZ 0x0075c28f
190196 #define CRT_PLL2_HS_108MHZ 0x80000000
191197 #define CRT_PLL2_HS_162MHZ 0xA0000000
192198 #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD
193199 #define CRT_PLL2_HS_193MHZ 0xC0872B02
194200
201
+#define HIBMC_CRT_PALETTE 0x80C00
202
+
195203 #define HIBMC_FIELD(field, value) (field(value) & field##_MASK)
196204 #endif