.. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* Hisilicon Hibmc SoC drm driver |
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2 | 3 | * |
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3 | 4 | * Based on the bochs drm driver. |
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.. | .. |
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8 | 9 | * Rongrong Zou <zourongrong@huawei.com> |
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9 | 10 | * Rongrong Zou <zourongrong@gmail.com> |
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10 | 11 | * Jianhua Li <lijianhua@huawei.com> |
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11 | | - * |
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12 | | - * This program is free software; you can redistribute it and/or modify |
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13 | | - * it under the terms of the GNU General Public License as published by |
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14 | | - * the Free Software Foundation; either version 2 of the License, or |
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15 | | - * (at your option) any later version. |
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16 | | - * |
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17 | 12 | */ |
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18 | 13 | |
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19 | 14 | #ifndef HIBMC_DRM_HW_H |
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.. | .. |
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73 | 68 | |
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74 | 69 | #define HIBMC_CRT_DISP_CTL 0x80200 |
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75 | 70 | |
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| 71 | +#define HIBMC_CRT_DISP_CTL_DPMS(x) ((x) << 30) |
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| 72 | +#define HIBMC_CRT_DISP_CTL_DPMS_MASK 0xc0000000 |
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| 73 | + |
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| 74 | +#define HIBMC_CRT_DPMS_ON 0 |
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| 75 | +#define HIBMC_CRT_DPMS_OFF 3 |
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| 76 | + |
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76 | 77 | #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25) |
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77 | 78 | #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000 |
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78 | 79 | |
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.. | .. |
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89 | 90 | |
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90 | 91 | #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8) |
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91 | 92 | #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100 |
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| 93 | + |
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| 94 | +#define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3) |
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| 95 | +#define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x08 |
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92 | 96 | |
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93 | 97 | #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2) |
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94 | 98 | #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4 |
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.. | .. |
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175 | 179 | #define CRT_PLL1_HS_74MHZ 0x23941dc2 |
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176 | 180 | #define CRT_PLL1_HS_80MHZ 0x23941001 |
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177 | 181 | #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2 |
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| 182 | +#define CRT_PLL1_HS_106MHZ 0x237C1641 |
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178 | 183 | #define CRT_PLL1_HS_108MHZ 0x23b41b01 |
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179 | 184 | #define CRT_PLL1_HS_162MHZ 0x23480681 |
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180 | 185 | #define CRT_PLL1_HS_148MHZ 0x23541dc2 |
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.. | .. |
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187 | 192 | #define CRT_PLL2_HS_78MHZ 0x50E147AE |
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188 | 193 | #define CRT_PLL2_HS_74MHZ 0x602B6AE7 |
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189 | 194 | #define CRT_PLL2_HS_80MHZ 0x70000000 |
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| 195 | +#define CRT_PLL2_HS_106MHZ 0x0075c28f |
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190 | 196 | #define CRT_PLL2_HS_108MHZ 0x80000000 |
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191 | 197 | #define CRT_PLL2_HS_162MHZ 0xA0000000 |
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192 | 198 | #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD |
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193 | 199 | #define CRT_PLL2_HS_193MHZ 0xC0872B02 |
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194 | 200 | |
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| 201 | +#define HIBMC_CRT_PALETTE 0x80C00 |
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| 202 | + |
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195 | 203 | #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) |
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196 | 204 | #endif |
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