modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
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@@ -1,22 +1,20 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright 2015 Freescale Semiconductor, Inc.
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  *
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  * Freescale DCU drm device driver
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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 #include <linux/clk.h>
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 #include <linux/regmap.h>
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-#include <drm/drmP.h>
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+#include <video/videomode.h>
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+
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 #include <drm/drm_atomic.h>
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 #include <drm/drm_atomic_helper.h>
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 #include <drm/drm_crtc.h>
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-#include <drm/drm_crtc_helper.h>
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+#include <drm/drm_probe_helper.h>
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+#include <drm/drm_vblank.h>
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 #include "fsl_dcu_drm_crtc.h"
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 #include "fsl_dcu_drm_drv.h"
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@@ -85,40 +83,34 @@
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 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
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 	struct drm_connector *con = &fsl_dev->connector.base;
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 	struct drm_display_mode *mode = &crtc->state->mode;
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-	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
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+	unsigned int pol = 0;
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+	struct videomode vm;
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-	index = drm_crtc_index(crtc);
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 	clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
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-	/* Configure timings: */
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-	hbp = mode->htotal - mode->hsync_end;
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-	hfp = mode->hsync_start - mode->hdisplay;
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-	hsw = mode->hsync_end - mode->hsync_start;
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-	vbp = mode->vtotal - mode->vsync_end;
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-	vfp = mode->vsync_start - mode->vdisplay;
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-	vsw = mode->vsync_end - mode->vsync_start;
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+	drm_display_mode_to_videomode(mode, &vm);
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 	/* INV_PXCK as default (most display sample data on rising edge) */
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-	if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE))
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+	if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE))
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 		pol |= DCU_SYN_POL_INV_PXCK;
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-	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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+	if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
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 		pol |= DCU_SYN_POL_INV_HS_LOW;
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-	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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+	if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
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 		pol |= DCU_SYN_POL_INV_VS_LOW;
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 	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
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-		     DCU_HSYN_PARA_BP(hbp) |
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-		     DCU_HSYN_PARA_PW(hsw) |
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-		     DCU_HSYN_PARA_FP(hfp));
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+		     DCU_HSYN_PARA_BP(vm.hback_porch) |
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+		     DCU_HSYN_PARA_PW(vm.hsync_len) |
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+		     DCU_HSYN_PARA_FP(vm.hfront_porch));
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 	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
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-		     DCU_VSYN_PARA_BP(vbp) |
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-		     DCU_VSYN_PARA_PW(vsw) |
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-		     DCU_VSYN_PARA_FP(vfp));
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+		     DCU_VSYN_PARA_BP(vm.vback_porch) |
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+		     DCU_VSYN_PARA_PW(vm.vsync_len) |
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+		     DCU_VSYN_PARA_FP(vm.vfront_porch));
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 	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
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-		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
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-		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
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+		     DCU_DISP_SIZE_DELTA_Y(vm.vactive) |
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+		     DCU_DISP_SIZE_DELTA_X(vm.hactive));
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 	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
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 	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
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 		     DCU_BGND_G(0) | DCU_BGND_B(0));