forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/exynos/exynos_mixer.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2011 Samsung Electronics Co.Ltd
34  * Authors:
....@@ -6,42 +7,34 @@
67  *	Joonyoung Shim <jy0922.shim@samsung.com>
78  *
89  * Based on drivers/media/video/s5p-tv/mixer_reg.c
9
- *
10
- * This program is free software; you can redistribute  it and/or modify it
11
- * under  the terms of  the GNU General  Public License as published by the
12
- * Free Software Foundation;  either version 2 of the  License, or (at your
13
- * option) any later version.
14
- *
1510  */
1611 
17
-#include <drm/drmP.h>
18
-
19
-#include "regs-mixer.h"
20
-#include "regs-vp.h"
21
-
22
-#include <linux/kernel.h>
23
-#include <linux/ktime.h>
24
-#include <linux/spinlock.h>
25
-#include <linux/wait.h>
12
+#include <linux/clk.h>
13
+#include <linux/component.h>
14
+#include <linux/delay.h>
2615 #include <linux/i2c.h>
27
-#include <linux/platform_device.h>
2816 #include <linux/interrupt.h>
2917 #include <linux/irq.h>
30
-#include <linux/delay.h>
31
-#include <linux/pm_runtime.h>
32
-#include <linux/clk.h>
33
-#include <linux/regulator/consumer.h>
18
+#include <linux/kernel.h>
19
+#include <linux/ktime.h>
3420 #include <linux/of.h>
3521 #include <linux/of_device.h>
36
-#include <linux/component.h>
22
+#include <linux/platform_device.h>
23
+#include <linux/pm_runtime.h>
24
+#include <linux/regulator/consumer.h>
25
+#include <linux/spinlock.h>
26
+#include <linux/wait.h>
3727 
28
+#include <drm/drm_fourcc.h>
29
+#include <drm/drm_vblank.h>
3830 #include <drm/exynos_drm.h>
3931 
40
-#include "exynos_drm_drv.h"
4132 #include "exynos_drm_crtc.h"
33
+#include "exynos_drm_drv.h"
4234 #include "exynos_drm_fb.h"
4335 #include "exynos_drm_plane.h"
44
-#include "exynos_drm_iommu.h"
36
+#include "regs-mixer.h"
37
+#include "regs-vp.h"
4538 
4639 #define MIXER_WIN_NR		3
4740 #define VP_DEFAULT_WIN		2
....@@ -101,6 +94,7 @@
10194 	struct platform_device *pdev;
10295 	struct device		*dev;
10396 	struct drm_device	*drm_dev;
97
+	void			*dma_priv;
10498 	struct exynos_drm_crtc	*crtc;
10599 	struct exynos_drm_plane	planes[MIXER_WIN_NR];
106100 	unsigned long		flags;
....@@ -132,14 +126,18 @@
132126 		.pixel_formats = mixer_formats,
133127 		.num_pixel_formats = ARRAY_SIZE(mixer_formats),
134128 		.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
135
-				EXYNOS_DRM_PLANE_CAP_ZPOS,
129
+				EXYNOS_DRM_PLANE_CAP_ZPOS |
130
+				EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
131
+				EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
136132 	}, {
137133 		.zpos = 1,
138134 		.type = DRM_PLANE_TYPE_CURSOR,
139135 		.pixel_formats = mixer_formats,
140136 		.num_pixel_formats = ARRAY_SIZE(mixer_formats),
141137 		.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
142
-				EXYNOS_DRM_PLANE_CAP_ZPOS,
138
+				EXYNOS_DRM_PLANE_CAP_ZPOS |
139
+				EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
140
+				EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
143141 	}, {
144142 		.zpos = 2,
145143 		.type = DRM_PLANE_TYPE_OVERLAY,
....@@ -147,7 +145,8 @@
147145 		.num_pixel_formats = ARRAY_SIZE(vp_formats),
148146 		.capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
149147 				EXYNOS_DRM_PLANE_CAP_ZPOS |
150
-				EXYNOS_DRM_PLANE_CAP_TILE,
148
+				EXYNOS_DRM_PLANE_CAP_TILE |
149
+				EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
151150 	},
152151 };
153152 
....@@ -224,8 +223,8 @@
224223 {
225224 #define DUMPREG(reg_id) \
226225 do { \
227
-	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
228
-		(u32)readl(ctx->mixer_regs + reg_id)); \
226
+	DRM_DEV_DEBUG_KMS(ctx->dev, #reg_id " = %08x\n", \
227
+			 (u32)readl(ctx->mixer_regs + reg_id)); \
229228 } while (0)
230229 
231230 	DUMPREG(MXR_STATUS);
....@@ -256,8 +255,8 @@
256255 {
257256 #define DUMPREG(reg_id) \
258257 do { \
259
-	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
260
-		(u32) readl(ctx->vp_regs + reg_id)); \
258
+	DRM_DEV_DEBUG_KMS(ctx->dev, #reg_id " = %08x\n", \
259
+			 (u32) readl(ctx->vp_regs + reg_id)); \
261260 } while (0)
262261 
263262 	DUMPREG(VP_ENABLE);
....@@ -310,31 +309,42 @@
310309 }
311310 
312311 static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
313
-				bool alpha)
312
+				unsigned int pixel_alpha, unsigned int alpha)
314313 {
314
+	u32 win_alpha = alpha >> 8;
315315 	u32 val;
316316 
317317 	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
318
-	if (alpha) {
319
-		/* blending based on pixel alpha */
318
+	switch (pixel_alpha) {
319
+	case DRM_MODE_BLEND_PIXEL_NONE:
320
+		break;
321
+	case DRM_MODE_BLEND_COVERAGE:
322
+		val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
323
+		break;
324
+	case DRM_MODE_BLEND_PREMULTI:
325
+	default:
320326 		val |= MXR_GRP_CFG_BLEND_PRE_MUL;
321327 		val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
328
+		break;
329
+	}
330
+
331
+	if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
332
+		val |= MXR_GRP_CFG_WIN_BLEND_EN;
333
+		val |= win_alpha;
322334 	}
323335 	mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
324336 			    val, MXR_GRP_CFG_MISC_MASK);
325337 }
326338 
327
-static void mixer_cfg_vp_blend(struct mixer_context *ctx)
339
+static void mixer_cfg_vp_blend(struct mixer_context *ctx, unsigned int alpha)
328340 {
329
-	u32 val;
341
+	u32 win_alpha = alpha >> 8;
342
+	u32 val = 0;
330343 
331
-	/*
332
-	 * No blending at the moment since the NV12/NV21 pixelformats don't
333
-	 * have an alpha channel. However the mixer supports a global alpha
334
-	 * value for a layer. Once this functionality is exposed, we can
335
-	 * support blending of the video layer through this.
336
-	 */
337
-	val = 0;
344
+	if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
345
+		val |= MXR_VID_CFG_BLEND_EN;
346
+		val |= win_alpha;
347
+	}
338348 	mixer_reg_write(ctx, MXR_VIDEO_CFG, val);
339349 }
340350 
....@@ -413,19 +423,16 @@
413423 	mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK);
414424 }
415425 
416
-static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
426
+static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, struct drm_display_mode *mode)
417427 {
428
+	enum hdmi_quantization_range range = drm_default_rgb_quant_range(mode);
418429 	u32 val;
419430 
420
-	switch (height) {
421
-	case 480:
422
-	case 576:
423
-		val = MXR_CFG_RGB601_0_255;
424
-		break;
425
-	case 720:
426
-	case 1080:
427
-	default:
428
-		val = MXR_CFG_RGB709_16_235;
431
+	if (mode->vdisplay < 720) {
432
+		val = MXR_CFG_RGB601;
433
+	} else {
434
+		val = MXR_CFG_RGB709;
435
+
429436 		/* Configure the BT.709 CSC matrix for full range RGB. */
430437 		mixer_reg_write(ctx, MXR_CM_COEFF_Y,
431438 			MXR_CSC_CT( 0.184,  0.614,  0.063) |
....@@ -434,8 +441,12 @@
434441 			MXR_CSC_CT(-0.102, -0.338,  0.440));
435442 		mixer_reg_write(ctx, MXR_CM_COEFF_CR,
436443 			MXR_CSC_CT( 0.440, -0.399, -0.040));
437
-		break;
438444 	}
445
+
446
+	if (range == HDMI_QUANTIZATION_RANGE_FULL)
447
+		val |= MXR_CFG_QUANT_RANGE_FULL;
448
+	else
449
+		val |= MXR_CFG_QUANT_RANGE_LIMITED;
439450 
440451 	mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
441452 }
....@@ -493,7 +504,7 @@
493504 	struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode;
494505 
495506 	mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay);
496
-	mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
507
+	mixer_cfg_rgb_fmt(ctx, mode);
497508 	mixer_run(ctx);
498509 }
499510 
....@@ -576,7 +587,7 @@
576587 	vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]);
577588 
578589 	mixer_cfg_layer(ctx, plane->index, priority, true);
579
-	mixer_cfg_vp_blend(ctx);
590
+	mixer_cfg_vp_blend(ctx, state->base.alpha);
580591 
581592 	spin_unlock_irqrestore(&ctx->reg_slock, flags);
582593 
....@@ -595,9 +606,15 @@
595606 	unsigned int win = plane->index;
596607 	unsigned int x_ratio = 0, y_ratio = 0;
597608 	unsigned int dst_x_offset, dst_y_offset;
609
+	unsigned int pixel_alpha;
598610 	dma_addr_t dma_addr;
599611 	unsigned int fmt;
600612 	u32 val;
613
+
614
+	if (fb->format->has_alpha)
615
+		pixel_alpha = state->base.pixel_blend_mode;
616
+	else
617
+		pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
601618 
602619 	switch (fb->format->format) {
603620 	case DRM_FORMAT_XRGB4444:
....@@ -658,7 +675,7 @@
658675 	mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr);
659676 
660677 	mixer_cfg_layer(ctx, win, priority, true);
661
-	mixer_cfg_gfx_blend(ctx, win, fb->format->has_alpha);
678
+	mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha);
662679 
663680 	spin_unlock_irqrestore(&ctx->reg_slock, flags);
664681 
....@@ -863,7 +880,8 @@
863880 	/* acquire resources: regs, irqs, clocks */
864881 	ret = mixer_resources_init(mixer_ctx);
865882 	if (ret) {
866
-		DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
883
+		DRM_DEV_ERROR(mixer_ctx->dev,
884
+			      "mixer_resources_init failed ret=%d\n", ret);
867885 		return ret;
868886 	}
869887 
....@@ -871,17 +889,20 @@
871889 		/* acquire vp resources: regs, irqs, clocks */
872890 		ret = vp_resources_init(mixer_ctx);
873891 		if (ret) {
874
-			DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
892
+			DRM_DEV_ERROR(mixer_ctx->dev,
893
+				      "vp_resources_init failed ret=%d\n", ret);
875894 			return ret;
876895 		}
877896 	}
878897 
879
-	return drm_iommu_attach_device(drm_dev, mixer_ctx->dev);
898
+	return exynos_drm_register_dma(drm_dev, mixer_ctx->dev,
899
+				       &mixer_ctx->dma_priv);
880900 }
881901 
882902 static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
883903 {
884
-	drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
904
+	exynos_drm_unregister_dma(mixer_ctx->drm_dev, mixer_ctx->dev,
905
+				  &mixer_ctx->dma_priv);
885906 }
886907 
887908 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
....@@ -930,7 +951,7 @@
930951 {
931952 	struct mixer_context *mixer_ctx = crtc->ctx;
932953 
933
-	DRM_DEBUG_KMS("win: %d\n", plane->index);
954
+	DRM_DEV_DEBUG_KMS(mixer_ctx->dev, "win: %d\n", plane->index);
934955 
935956 	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
936957 		return;
....@@ -947,7 +968,7 @@
947968 	struct mixer_context *mixer_ctx = crtc->ctx;
948969 	unsigned long flags;
949970 
950
-	DRM_DEBUG_KMS("win: %d\n", plane->index);
971
+	DRM_DEV_DEBUG_KMS(mixer_ctx->dev, "win: %d\n", plane->index);
951972 
952973 	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
953974 		return;
....@@ -968,7 +989,7 @@
968989 	exynos_crtc_handle_event(crtc);
969990 }
970991 
971
-static void mixer_enable(struct exynos_drm_crtc *crtc)
992
+static void mixer_atomic_enable(struct exynos_drm_crtc *crtc)
972993 {
973994 	struct mixer_context *ctx = crtc->ctx;
974995 
....@@ -997,7 +1018,7 @@
9971018 	set_bit(MXR_BIT_POWERED, &ctx->flags);
9981019 }
9991020 
1000
-static void mixer_disable(struct exynos_drm_crtc *crtc)
1021
+static void mixer_atomic_disable(struct exynos_drm_crtc *crtc)
10011022 {
10021023 	struct mixer_context *ctx = crtc->ctx;
10031024 	int i;
....@@ -1024,8 +1045,9 @@
10241045 	struct mixer_context *ctx = crtc->ctx;
10251046 	u32 w = mode->hdisplay, h = mode->vdisplay;
10261047 
1027
-	DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", w, h,
1028
-		mode->vrefresh, !!(mode->flags & DRM_MODE_FLAG_INTERLACE));
1048
+	DRM_DEV_DEBUG_KMS(ctx->dev, "xres=%d, yres=%d, refresh=%d, intl=%d\n",
1049
+			  w, h, drm_mode_vrefresh(mode),
1050
+			  !!(mode->flags & DRM_MODE_FLAG_INTERLACE));
10291051 
10301052 	if (ctx->mxr_ver == MXR_VER_128_0_0_184)
10311053 		return MODE_OK;
....@@ -1050,9 +1072,9 @@
10501072 	struct mixer_context *ctx = crtc->ctx;
10511073 	int width = mode->hdisplay, height = mode->vdisplay, i;
10521074 
1053
-	struct {
1075
+	static const struct {
10541076 		int hdisplay, vdisplay, htotal, vtotal, scan_val;
1055
-	} static const modes[] = {
1077
+	} modes[] = {
10561078 		{ 720, 480, 858, 525, MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD },
10571079 		{ 720, 576, 864, 625, MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD },
10581080 		{ 1280, 720, 1650, 750, MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD },
....@@ -1090,8 +1112,8 @@
10901112 }
10911113 
10921114 static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1093
-	.enable			= mixer_enable,
1094
-	.disable		= mixer_disable,
1115
+	.atomic_enable		= mixer_atomic_enable,
1116
+	.atomic_disable		= mixer_atomic_disable,
10951117 	.enable_vblank		= mixer_enable_vblank,
10961118 	.disable_vblank		= mixer_disable_vblank,
10971119 	.atomic_begin		= mixer_atomic_begin,
....@@ -1205,7 +1227,7 @@
12051227 
12061228 	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
12071229 	if (!ctx) {
1208
-		DRM_ERROR("failed to alloc mixer context.\n");
1230
+		DRM_DEV_ERROR(dev, "failed to alloc mixer context.\n");
12091231 		return -ENOMEM;
12101232 	}
12111233 
....@@ -1222,9 +1244,11 @@
12221244 
12231245 	platform_set_drvdata(pdev, ctx);
12241246 
1247
+	pm_runtime_enable(dev);
1248
+
12251249 	ret = component_add(&pdev->dev, &mixer_component_ops);
1226
-	if (!ret)
1227
-		pm_runtime_enable(dev);
1250
+	if (ret)
1251
+		pm_runtime_disable(dev);
12281252 
12291253 	return ret;
12301254 }
....@@ -1260,27 +1284,33 @@
12601284 
12611285 	ret = clk_prepare_enable(ctx->mixer);
12621286 	if (ret < 0) {
1263
-		DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
1287
+		DRM_DEV_ERROR(ctx->dev,
1288
+			      "Failed to prepare_enable the mixer clk [%d]\n",
1289
+			      ret);
12641290 		return ret;
12651291 	}
12661292 	ret = clk_prepare_enable(ctx->hdmi);
12671293 	if (ret < 0) {
1268
-		DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
1294
+		DRM_DEV_ERROR(dev,
1295
+			      "Failed to prepare_enable the hdmi clk [%d]\n",
1296
+			      ret);
12691297 		return ret;
12701298 	}
12711299 	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
12721300 		ret = clk_prepare_enable(ctx->vp);
12731301 		if (ret < 0) {
1274
-			DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
1275
-				  ret);
1302
+			DRM_DEV_ERROR(dev,
1303
+				      "Failed to prepare_enable the vp clk [%d]\n",
1304
+				      ret);
12761305 			return ret;
12771306 		}
12781307 		if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) {
12791308 			ret = clk_prepare_enable(ctx->sclk_mixer);
12801309 			if (ret < 0) {
1281
-				DRM_ERROR("Failed to prepare_enable the " \
1310
+				DRM_DEV_ERROR(dev,
1311
+					   "Failed to prepare_enable the " \
12821312 					   "sclk_mixer clk [%d]\n",
1283
-					  ret);
1313
+					   ret);
12841314 				return ret;
12851315 			}
12861316 		}