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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/gpu/drm/exynos/exynos_drm_scaler.c
....@@ -1,30 +1,27 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2017 Samsung Electronics Co.Ltd
34  * Author:
4
- *	Andrzej Pietrasiewicz <andrzej.p@samsung.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundationr
5
+ *	Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
96  */
107 
11
-#include <linux/kernel.h>
8
+#include <linux/clk.h>
129 #include <linux/component.h>
1310 #include <linux/err.h>
1411 #include <linux/interrupt.h>
1512 #include <linux/io.h>
16
-#include <linux/platform_device.h>
17
-#include <linux/clk.h>
13
+#include <linux/kernel.h>
1814 #include <linux/of_device.h>
15
+#include <linux/platform_device.h>
1916 #include <linux/pm_runtime.h>
2017 
21
-#include <drm/drmP.h>
18
+#include <drm/drm_fourcc.h>
2219 #include <drm/exynos_drm.h>
23
-#include "regs-scaler.h"
24
-#include "exynos_drm_fb.h"
20
+
2521 #include "exynos_drm_drv.h"
26
-#include "exynos_drm_iommu.h"
22
+#include "exynos_drm_fb.h"
2723 #include "exynos_drm_ipp.h"
24
+#include "regs-scaler.h"
2825 
2926 #define scaler_read(offset)		readl(scaler->regs + (offset))
3027 #define scaler_write(cfg, offset)	writel(cfg, scaler->regs + (offset))
....@@ -42,6 +39,7 @@
4239 struct scaler_context {
4340 	struct exynos_drm_ipp		ipp;
4441 	struct drm_device		*drm_dev;
42
+	void				*dma_priv;
4543 	struct device			*dev;
4644 	void __iomem			*regs;
4745 	struct clk			*clock[SCALER_MAX_CLK];
....@@ -49,56 +47,46 @@
4947 	const struct scaler_data	*scaler_data;
5048 };
5149 
52
-static u32 scaler_get_format(u32 drm_fmt)
53
-{
54
-	switch (drm_fmt) {
55
-	case DRM_FORMAT_NV12:
56
-		return SCALER_YUV420_2P_UV;
57
-	case DRM_FORMAT_NV21:
58
-		return SCALER_YUV420_2P_VU;
59
-	case DRM_FORMAT_YUV420:
60
-		return SCALER_YUV420_3P;
61
-	case DRM_FORMAT_YUYV:
62
-		return SCALER_YUV422_1P_YUYV;
63
-	case DRM_FORMAT_UYVY:
64
-		return SCALER_YUV422_1P_UYVY;
65
-	case DRM_FORMAT_YVYU:
66
-		return SCALER_YUV422_1P_YVYU;
67
-	case DRM_FORMAT_NV16:
68
-		return SCALER_YUV422_2P_UV;
69
-	case DRM_FORMAT_NV61:
70
-		return SCALER_YUV422_2P_VU;
71
-	case DRM_FORMAT_YUV422:
72
-		return SCALER_YUV422_3P;
73
-	case DRM_FORMAT_NV24:
74
-		return SCALER_YUV444_2P_UV;
75
-	case DRM_FORMAT_NV42:
76
-		return SCALER_YUV444_2P_VU;
77
-	case DRM_FORMAT_YUV444:
78
-		return SCALER_YUV444_3P;
79
-	case DRM_FORMAT_RGB565:
80
-		return SCALER_RGB_565;
81
-	case DRM_FORMAT_XRGB1555:
82
-		return SCALER_ARGB1555;
83
-	case DRM_FORMAT_ARGB1555:
84
-		return SCALER_ARGB1555;
85
-	case DRM_FORMAT_XRGB4444:
86
-		return SCALER_ARGB4444;
87
-	case DRM_FORMAT_ARGB4444:
88
-		return SCALER_ARGB4444;
89
-	case DRM_FORMAT_XRGB8888:
90
-		return SCALER_ARGB8888;
91
-	case DRM_FORMAT_ARGB8888:
92
-		return SCALER_ARGB8888;
93
-	case DRM_FORMAT_RGBX8888:
94
-		return SCALER_RGBA8888;
95
-	case DRM_FORMAT_RGBA8888:
96
-		return SCALER_RGBA8888;
97
-	default:
98
-		break;
99
-	}
50
+struct scaler_format {
51
+	u32	drm_fmt;
52
+	u32	internal_fmt;
53
+	u32	chroma_tile_w;
54
+	u32	chroma_tile_h;
55
+};
10056 
101
-	return 0;
57
+static const struct scaler_format scaler_formats[] = {
58
+	{ DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
59
+	{ DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
60
+	{ DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
61
+	{ DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
62
+	{ DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
63
+	{ DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
64
+	{ DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
65
+	{ DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
66
+	{ DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
67
+	{ DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
68
+	{ DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
69
+	{ DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
70
+	{ DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
71
+	{ DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
72
+	{ DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
73
+	{ DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 },
74
+	{ DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 },
75
+	{ DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 },
76
+	{ DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 },
77
+	{ DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 },
78
+	{ DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 },
79
+};
80
+
81
+static const struct scaler_format *scaler_get_format(u32 drm_fmt)
82
+{
83
+	int i;
84
+
85
+	for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
86
+		if (scaler_formats[i].drm_fmt == drm_fmt)
87
+			return &scaler_formats[i];
88
+
89
+	return NULL;
10290 }
10391 
10492 static inline int scaler_reset(struct scaler_context *scaler)
....@@ -152,11 +140,11 @@
152140 }
153141 
154142 static inline void scaler_set_src_fmt(struct scaler_context *scaler,
155
-	u32 src_fmt)
143
+	u32 src_fmt, u32 tile)
156144 {
157145 	u32 val;
158146 
159
-	val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt);
147
+	val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
160148 	scaler_write(val, SCALER_SRC_CFG);
161149 }
162150 
....@@ -188,15 +176,20 @@
188176 	scaler_write(val, SCALER_SRC_SPAN);
189177 }
190178 
191
-static inline void scaler_set_src_luma_pos(struct scaler_context *scaler,
192
-	struct drm_exynos_ipp_task_rect *src_pos)
179
+static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler,
180
+			struct drm_exynos_ipp_task_rect *src_pos,
181
+			const struct scaler_format *fmt)
193182 {
194183 	u32 val;
195184 
196185 	val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
197186 	val |=  SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
198187 	scaler_write(val, SCALER_SRC_Y_POS);
199
-	scaler_write(val, SCALER_SRC_C_POS); /* ATTENTION! */
188
+	val = SCALER_SRC_C_POS_SET_CH_POS(
189
+		(src_pos->x * fmt->chroma_tile_w / 16) << 2);
190
+	val |=  SCALER_SRC_C_POS_SET_CV_POS(
191
+		(src_pos->y * fmt->chroma_tile_h / 16) << 2);
192
+	scaler_write(val, SCALER_SRC_C_POS);
200193 }
201194 
202195 static inline void scaler_set_src_wh(struct scaler_context *scaler,
....@@ -366,11 +359,12 @@
366359 	struct scaler_context *scaler =
367360 			container_of(ipp, struct scaler_context, ipp);
368361 
369
-	u32 src_fmt = scaler_get_format(task->src.buf.fourcc);
370362 	struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
371
-
372
-	u32 dst_fmt = scaler_get_format(task->dst.buf.fourcc);
373363 	struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
364
+	const struct scaler_format *src_fmt, *dst_fmt;
365
+
366
+	src_fmt = scaler_get_format(task->src.buf.fourcc);
367
+	dst_fmt = scaler_get_format(task->dst.buf.fourcc);
374368 
375369 	pm_runtime_get_sync(scaler->dev);
376370 	if (scaler_reset(scaler)) {
....@@ -380,13 +374,14 @@
380374 
381375 	scaler->task = task;
382376 
383
-	scaler_set_src_fmt(scaler, src_fmt);
377
+	scaler_set_src_fmt(
378
+		scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0);
384379 	scaler_set_src_base(scaler, &task->src);
385380 	scaler_set_src_span(scaler, &task->src);
386
-	scaler_set_src_luma_pos(scaler, src_pos);
381
+	scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt);
387382 	scaler_set_src_wh(scaler, src_pos);
388383 
389
-	scaler_set_dst_fmt(scaler, dst_fmt);
384
+	scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt);
390385 	scaler_set_dst_base(scaler, &task->dst);
391386 	scaler_set_dst_span(scaler, &task->dst);
392387 	scaler_set_dst_luma_pos(scaler, dst_pos);
....@@ -455,9 +450,10 @@
455450 	struct exynos_drm_ipp *ipp = &scaler->ipp;
456451 
457452 	scaler->drm_dev = drm_dev;
458
-	drm_iommu_attach_device(drm_dev, dev);
453
+	ipp->drm_dev = drm_dev;
454
+	exynos_drm_register_dma(drm_dev, dev, &scaler->dma_priv);
459455 
460
-	exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
456
+	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
461457 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
462458 			DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
463459 			scaler->scaler_data->formats,
....@@ -472,11 +468,11 @@
472468 			void *data)
473469 {
474470 	struct scaler_context *scaler = dev_get_drvdata(dev);
475
-	struct drm_device *drm_dev = data;
476471 	struct exynos_drm_ipp *ipp = &scaler->ipp;
477472 
478
-	exynos_drm_ipp_unregister(drm_dev, ipp);
479
-	drm_iommu_detach_device(scaler->drm_dev, scaler->dev);
473
+	exynos_drm_ipp_unregister(dev, ipp);
474
+	exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev,
475
+				  &scaler->dma_priv);
480476 }
481477 
482478 static const struct component_ops scaler_component_ops = {
....@@ -506,10 +502,8 @@
506502 		return PTR_ERR(scaler->regs);
507503 
508504 	irq = platform_get_irq(pdev, 0);
509
-	if (irq < 0) {
510
-		dev_err(dev, "failed to get irq\n");
505
+	if (irq < 0)
511506 		return irq;
512
-	}
513507 
514508 	ret = devm_request_threaded_irq(dev, irq, NULL,	scaler_irq_handler,
515509 					IRQF_ONESHOT, "drm_scaler", scaler);
....@@ -617,6 +611,16 @@
617611 			  .v = { 65536 * 1 / 4, 65536 * 16 }) },
618612 };
619613 
614
+static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
615
+	{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
616
+	{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
617
+	{ IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
618
+	{ }
619
+};
620
+
621
+#define IPP_SRCDST_TILE_FORMAT(f, l)	\
622
+	IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l))
623
+
620624 static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
621625 	/* SCALER_YUV420_2P_UV */
622626 	{ IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
....@@ -680,6 +684,18 @@
680684 
681685 	/* SCALER_RGBA8888 */
682686 	{ IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
687
+
688
+	/* SCALER_YUV420_2P_UV TILE */
689
+	{ IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) },
690
+
691
+	/* SCALER_YUV420_2P_VU TILE */
692
+	{ IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
693
+
694
+	/* SCALER_YUV420_3P TILE */
695
+	{ IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) },
696
+
697
+	/* SCALER_YUV422_1P_YUYV TILE */
698
+	{ IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) },
683699 };
684700 
685701 static const struct scaler_data exynos5420_data = {