forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/exynos/exynos_drm_plane.c
....@@ -1,22 +1,17 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Copyright (C) 2011 Samsung Electronics Co.Ltd
34 * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation; either version 2 of the License, or (at your
8
- * option) any later version.
9
- *
105 */
116
12
-#include <drm/drmP.h>
137
148 #include <drm/drm_atomic.h>
159 #include <drm/drm_atomic_helper.h>
1610 #include <drm/drm_plane_helper.h>
1711 #include <drm/exynos_drm.h>
18
-#include "exynos_drm_drv.h"
12
+
1913 #include "exynos_drm_crtc.h"
14
+#include "exynos_drm_drv.h"
2015 #include "exynos_drm_fb.h"
2116 #include "exynos_drm_gem.h"
2217 #include "exynos_drm_plane.h"
....@@ -119,9 +114,10 @@
119114 exynos_state->crtc.w = actual_w;
120115 exynos_state->crtc.h = actual_h;
121116
122
- DRM_DEBUG_KMS("plane : offset_x/y(%d,%d), width/height(%d,%d)",
123
- exynos_state->crtc.x, exynos_state->crtc.y,
124
- exynos_state->crtc.w, exynos_state->crtc.h);
117
+ DRM_DEV_DEBUG_KMS(crtc->dev->dev,
118
+ "plane : offset_x/y(%d,%d), width/height(%d,%d)",
119
+ exynos_state->crtc.x, exynos_state->crtc.y,
120
+ exynos_state->crtc.w, exynos_state->crtc.h);
125121 }
126122
127123 static void exynos_drm_plane_reset(struct drm_plane *plane)
....@@ -131,16 +127,14 @@
131127
132128 if (plane->state) {
133129 exynos_state = to_exynos_plane_state(plane->state);
134
- if (exynos_state->base.fb)
135
- drm_framebuffer_put(exynos_state->base.fb);
130
+ __drm_atomic_helper_plane_destroy_state(plane->state);
136131 kfree(exynos_state);
137132 plane->state = NULL;
138133 }
139134
140135 exynos_state = kzalloc(sizeof(*exynos_state), GFP_KERNEL);
141136 if (exynos_state) {
142
- plane->state = &exynos_state->base;
143
- plane->state->plane = plane;
137
+ __drm_atomic_helper_plane_reset(plane, &exynos_state->base);
144138 plane->state->zpos = exynos_plane->config->zpos;
145139 }
146140 }
....@@ -183,6 +177,7 @@
183177 struct exynos_drm_plane_state *state)
184178 {
185179 struct drm_framebuffer *fb = state->base.fb;
180
+ struct drm_device *dev = fb->dev;
186181
187182 switch (fb->modifier) {
188183 case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
....@@ -194,7 +189,7 @@
194189 break;
195190
196191 default:
197
- DRM_ERROR("unsupported pixel format modifier");
192
+ DRM_DEV_ERROR(dev->dev, "unsupported pixel format modifier");
198193 return -ENOTSUPP;
199194 }
200195
....@@ -205,6 +200,7 @@
205200 exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
206201 struct exynos_drm_plane_state *state)
207202 {
203
+ struct drm_crtc *crtc = state->base.crtc;
208204 bool width_ok = false, height_ok = false;
209205
210206 if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)
....@@ -227,7 +223,7 @@
227223 if (width_ok && height_ok)
228224 return 0;
229225
230
- DRM_DEBUG_KMS("scaling mode is not supported");
226
+ DRM_DEV_DEBUG_KMS(crtc->dev->dev, "scaling mode is not supported");
231227 return -ENOTSUPP;
232228 }
233229
....@@ -300,6 +296,10 @@
300296 const struct exynos_drm_plane_config *config)
301297 {
302298 int err;
299
+ unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
300
+ BIT(DRM_MODE_BLEND_PREMULTI) |
301
+ BIT(DRM_MODE_BLEND_COVERAGE);
302
+ struct drm_plane *plane = &exynos_plane->base;
303303
304304 err = drm_universal_plane_init(dev, &exynos_plane->base,
305305 1 << dev->mode_config.num_crtc,
....@@ -308,7 +308,7 @@
308308 config->num_pixel_formats,
309309 NULL, config->type, NULL);
310310 if (err) {
311
- DRM_ERROR("failed to initialize plane\n");
311
+ DRM_DEV_ERROR(dev->dev, "failed to initialize plane\n");
312312 return err;
313313 }
314314
....@@ -320,5 +320,11 @@
320320 exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos,
321321 !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS));
322322
323
+ if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND)
324
+ drm_plane_create_blend_mode_property(plane, supported_modes);
325
+
326
+ if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND)
327
+ drm_plane_create_alpha_property(plane);
328
+
323329 return 0;
324330 }