forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/gpu/drm/armada/armada_hw.h
....@@ -1,10 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23 * Copyright (C) 2012 Russell King
34 * Rewritten from the dovefb driver, and Armada510 manuals.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
85 */
96 #ifndef ARMADA_HW_H
107 #define ARMADA_HW_H
....@@ -88,6 +85,16 @@
8885 ADV_VSYNC_H_OFF = 0xfff << 0,
8986 };
9087
88
+/* LCD_CFG_RDREG4F - Armada 510 only */
89
+enum {
90
+ CFG_SRAM_WAIT = BIT(11),
91
+ CFG_SMPN_FASTTX = BIT(10),
92
+ CFG_DMA_ARB = BIT(9),
93
+ CFG_DMA_WM_EN = BIT(8),
94
+ CFG_DMA_WM_MASK = 0xff,
95
+#define CFG_DMA_WM(x) ((x) & CFG_DMA_WM_MASK)
96
+};
97
+
9198 enum {
9299 CFG_565 = 0,
93100 CFG_1555 = 1,
....@@ -169,6 +176,10 @@
169176 SRAM_READ = 0 << 14,
170177 SRAM_WRITE = 2 << 14,
171178 SRAM_INIT = 3 << 14,
179
+ SRAM_GAMMA_YR = 0x0 << 8,
180
+ SRAM_GAMMA_UG = 0x1 << 8,
181
+ SRAM_GAMMA_VB = 0x2 << 8,
182
+ SRAM_PALETTE = 0x3 << 8,
172183 SRAM_HWC32_RAM1 = 0xc << 8,
173184 SRAM_HWC32_RAM2 = 0xd << 8,
174185 SRAM_HWC32_RAMR = SRAM_HWC32_RAM1,
....@@ -315,20 +326,5 @@
315326 GRA_FF_ALLEMPTY = 1 << 1,
316327 PWRDN_IRQ_LEVEL = 1 << 0,
317328 };
318
-
319
-static inline u32 armada_rect_hw_fp(struct drm_rect *r)
320
-{
321
- return (drm_rect_height(r) & 0xffff0000) | drm_rect_width(r) >> 16;
322
-}
323
-
324
-static inline u32 armada_rect_hw(struct drm_rect *r)
325
-{
326
- return drm_rect_height(r) << 16 | (drm_rect_width(r) & 0x0000ffff);
327
-}
328
-
329
-static inline u32 armada_rect_yx(struct drm_rect *r)
330
-{
331
- return (r)->y1 << 16 | ((r)->x1 & 0x0000ffff);
332
-}
333329
334330 #endif