modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/gpu/drm/arm/malidp_hw.h
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@@ -1,11 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *
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  * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
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- *
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- * This program is free software and is provided to you under the terms of the
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- * GNU General Public License version 2 as published by the Free Software
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- * Foundation, and any use by you of this program is subject to the terms
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- * of such GNU licence.
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  *
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  * ARM Mali DP hardware manipulation routines.
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  */
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@@ -36,6 +32,12 @@
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 	SE_MEMWRITE = BIT(5),
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 };
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+enum rotation_features {
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+	ROTATE_NONE,		/* does not support rotation at all */
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+	ROTATE_ANY,		/* supports rotation on any buffers */
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+	ROTATE_COMPRESSED,	/* supports rotation only on compressed buffers */
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+};
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+
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 struct malidp_format_id {
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 	u32 format;		/* DRM fourcc */
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 	u8 layer;		/* bitmask of layers supporting it */
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@@ -62,6 +64,10 @@
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 	u16 ptr;		/* address offset for the pointer register */
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 	u16 stride_offset;	/* offset to the first stride register. */
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 	s16 yuv2rgb_offset;	/* offset to the YUV->RGB matrix entries */
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+	u16 mmu_ctrl_offset;    /* offset to the MMU control register */
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+	enum rotation_features rot;	/* type of rotation supported */
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+	/* address offset for the AFBC decoder registers */
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+	u16 afbc_decoder_offset;
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 };
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 enum malidp_scaling_coeff_set {
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@@ -85,7 +91,10 @@
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 };
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 /* regmap features */
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-#define MALIDP_REGMAP_HAS_CLEARIRQ	(1 << 0)
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+#define MALIDP_REGMAP_HAS_CLEARIRQ				BIT(0)
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+#define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT			BIT(1)
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+#define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT		BIT(2)
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+#define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2			BIT(3)
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 struct malidp_hw_regmap {
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 	/* address offset of the DE register bank */
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@@ -171,7 +180,8 @@
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 	 * Calculate the required rotation memory given the active area
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 	 * and the buffer format.
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 	 */
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-	int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt);
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+	int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h,
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+			       u32 fmt, bool has_modifier);
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 	int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev,
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 				     struct malidp_se_config *se_config,
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@@ -241,6 +251,9 @@
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 	/* size of memory used for rotating layers, up to two banks available */
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 	u32 rotation_memory[2];
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+
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+	/* priority level of RQOS register used for driven the ARQOS signal */
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+	u32 arqos_value;
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 };
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 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
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@@ -311,7 +324,9 @@
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 void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
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 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
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-			   u8 layer_id, u32 format);
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+			   u8 layer_id, u32 format, bool has_modifier);
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+
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+int malidp_format_get_bpp(u32 fmt);
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 static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
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 {
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@@ -380,4 +395,18 @@
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 #define MALIDP_GAMMA_LUT_SIZE		4096
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+#define AFBC_SIZE_MASK		AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
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+#define AFBC_SIZE_16X16		AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
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+#define AFBC_YTR		AFBC_FORMAT_MOD_YTR
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+#define AFBC_SPARSE		AFBC_FORMAT_MOD_SPARSE
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+#define AFBC_CBR		AFBC_FORMAT_MOD_CBR
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+#define AFBC_SPLIT		AFBC_FORMAT_MOD_SPLIT
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+#define AFBC_TILED		AFBC_FORMAT_MOD_TILED
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+#define AFBC_SC			AFBC_FORMAT_MOD_SC
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+
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+#define AFBC_MOD_VALID_BITS	(AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \
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+				 AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
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+
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+extern const u64 malidp_format_modifiers[];
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+
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 #endif  /* __MALIDP_HW_H__ */