forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/edac/ie31200_edac.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Intel E3-1200
34  * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
....@@ -8,7 +9,7 @@
89  * Since the DRAM controller is on the cpu chip, we can use its PCI device
910  * id to identify these processors.
1011  *
11
- * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/)
12
+ * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
1213  *
1314  * 0108: Xeon E3-1200 Processor Family DRAM Controller
1415  * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
....@@ -19,11 +20,13 @@
1920  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
2021  * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
2122  * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23
+ * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
2224  *
2325  * Based on Intel specification:
24
- * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
26
+ * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
2527  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
26
- * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
28
+ * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
29
+ * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
2730  *
2831  * According to the above datasheet (p.16):
2932  * "
....@@ -59,6 +62,26 @@
5962 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
6063 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
6164 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
65
+
66
+/* Coffee Lake-S */
67
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
68
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1    0x3e0f
69
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e18
70
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e1f
71
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e30
72
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e31
73
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e32
74
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e33
75
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3ec2
76
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec6
77
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3eca
78
+
79
+/* Test if HB is for Skylake or later. */
80
+#define DEVICE_ID_SKYLAKE_OR_LATER(did)                                        \
81
+	(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) ||                        \
82
+	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) ||                        \
83
+	 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) ==                 \
84
+	  PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
6285 
6386 #define IE31200_DIMMS			4
6487 #define IE31200_RANKS			8
....@@ -336,7 +359,7 @@
336359 		return NULL;
337360 	}
338361 
339
-	window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
362
+	window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
340363 	if (!window)
341364 		ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
342365 			       (unsigned long long)u.mchbar);
....@@ -382,10 +405,10 @@
382405 	u32 addr_decode, mad_offset;
383406 
384407 	/*
385
-	 * Kaby Lake seems to work like Skylake. Please re-visit this logic
386
-	 * when adding new CPU support.
408
+	 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
409
+	 * this logic when adding new CPU support.
387410 	 */
388
-	bool skl = (pdev->device >= PCI_DEVICE_ID_INTEL_IE31200_HB_8);
411
+	bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
389412 
390413 	edac_dbg(0, "MC:\n");
391414 
....@@ -469,9 +492,7 @@
469492 
470493 			if (dimm_info[j][i].dual_rank) {
471494 				nr_pages = nr_pages / 2;
472
-				dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
473
-						     mci->n_layers, (i * 2) + 1,
474
-						     j, 0);
495
+				dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
475496 				dimm->nr_pages = nr_pages;
476497 				edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
477498 				dimm->grain = 8; /* just a guess */
....@@ -482,8 +503,7 @@
482503 				dimm->dtype = DEV_UNKNOWN;
483504 				dimm->edac_mode = EDAC_UNKNOWN;
484505 			}
485
-			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
486
-					     mci->n_layers, i * 2, j, 0);
506
+			dimm = edac_get_dimm(mci, i * 2, j, 0);
487507 			dimm->nr_pages = nr_pages;
488508 			edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
489509 			dimm->grain = 8; /* same guess */
....@@ -549,36 +569,26 @@
549569 }
550570 
551571 static const struct pci_device_id ie31200_pci_tbl[] = {
552
-	{
553
-		PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
554
-		IE31200},
555
-	{
556
-		PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
557
-		IE31200},
558
-	{
559
-		PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
560
-		IE31200},
561
-	{
562
-		PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
563
-		IE31200},
564
-	{
565
-		PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
566
-		IE31200},
567
-	{
568
-		PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
569
-		IE31200},
570
-	{
571
-		PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
572
-		IE31200},
573
-	{
574
-		PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
575
-		IE31200},
576
-	{
577
-		PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
578
-		IE31200},
579
-	{
580
-		0,
581
-	}            /* 0 terminated list. */
572
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_1),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
573
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_2),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
574
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_3),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
575
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_4),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
576
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_5),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
577
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_6),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
578
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_7),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
579
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_8),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
580
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_9),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
581
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
582
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
583
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
584
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
585
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
586
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
587
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
590
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
591
+	{ 0, } /* 0 terminated list. */
582592 };
583593 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
584594