modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/crypto/rockchip/rk_crypto_v3_ahash.c
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@@ -56,13 +56,17 @@
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 	CRYPTO_WRITE(rk_dev, CRYPTO_RST_CTL, tmp | tmp_mask);
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 	/* This is usually done in 20 clock cycles */
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-	ret = readl_poll_timeout_atomic(rk_dev->reg + CRYPTO_RST_CTL,
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-					tmp, !tmp, 0, pool_timeout_us);
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+	ret = read_poll_timeout_atomic(CRYPTO_READ, tmp, !tmp, 0, pool_timeout_us,
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+				       false, rk_dev, CRYPTO_RST_CTL);
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 	if (ret)
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 		dev_err(rk_dev->dev, "cipher reset pool timeout %ums.",
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 			pool_timeout_us);
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 	CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000);
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+
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+	/* clear dma int status */
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+	tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
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+	CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
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 }
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 static int rk_hash_mid_data_store(struct rk_crypto_dev *rk_dev, struct rk_hash_mid_data *mid_data)
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@@ -72,11 +76,13 @@
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 	CRYPTO_TRACE();
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-	ret = readl_poll_timeout_atomic(rk_dev->reg + CRYPTO_MID_VALID,
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+	ret = read_poll_timeout_atomic(CRYPTO_READ,
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 					reg_ctrl,
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 					reg_ctrl & CRYPTO_HASH_MID_IS_VALID,
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-					RK_POLL_PERIOD_US,
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-					RK_POLL_TIMEOUT_US);
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+					0,
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+					RK_POLL_TIMEOUT_US,
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+					false, rk_dev, CRYPTO_MID_VALID);
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+
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 	CRYPTO_WRITE(rk_dev, CRYPTO_MID_VALID_SWITCH,
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 		     CRYPTO_MID_VALID_ENABLE << CRYPTO_WRITE_MASK_SHIFT);
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 	if (ret) {
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@@ -362,11 +368,11 @@
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 	memset(ctx->priv, 0x00, sizeof(struct rk_hash_mid_data));
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370
 
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-	ret = readl_poll_timeout_atomic(rk_dev->reg + CRYPTO_HASH_VALID,
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-					reg_ctrl,
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-					reg_ctrl & CRYPTO_HASH_IS_VALID,
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-					RK_POLL_PERIOD_US,
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-					RK_POLL_TIMEOUT_US);
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+	ret = read_poll_timeout_atomic(CRYPTO_READ, reg_ctrl,
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+				       reg_ctrl & CRYPTO_HASH_IS_VALID,
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+				       RK_POLL_PERIOD_US,
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+				       RK_POLL_TIMEOUT_US, false,
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+				       rk_dev, CRYPTO_HASH_VALID);
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 	if (ret)
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 		goto exit;
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