hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/arch/riscv/include/asm/perf_event.h
....@@ -12,19 +12,14 @@
1212 #include <linux/ptrace.h>
1313 #include <linux/interrupt.h>
1414
15
+#ifdef CONFIG_RISCV_BASE_PMU
1516 #define RISCV_BASE_COUNTERS 2
1617
1718 /*
1819 * The RISCV_MAX_COUNTERS parameter should be specified.
1920 */
2021
21
-#ifdef CONFIG_RISCV_BASE_PMU
2222 #define RISCV_MAX_COUNTERS 2
23
-#endif
24
-
25
-#ifndef RISCV_MAX_COUNTERS
26
-#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU."
27
-#endif
2823
2924 /*
3025 * These are the indexes of bits in counteren register *minus* 1,
....@@ -82,4 +77,9 @@
8277 int irq;
8378 };
8479
80
+#endif
81
+#ifdef CONFIG_PERF_EVENTS
82
+#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
83
+#endif
84
+
8585 #endif /* _ASM_RISCV_PERF_EVENT_H */