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12 | 12 | #include <linux/ptrace.h> |
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13 | 13 | #include <linux/interrupt.h> |
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14 | 14 | |
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| 15 | +#ifdef CONFIG_RISCV_BASE_PMU |
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15 | 16 | #define RISCV_BASE_COUNTERS 2 |
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16 | 17 | |
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17 | 18 | /* |
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18 | 19 | * The RISCV_MAX_COUNTERS parameter should be specified. |
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19 | 20 | */ |
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20 | 21 | |
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21 | | -#ifdef CONFIG_RISCV_BASE_PMU |
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22 | 22 | #define RISCV_MAX_COUNTERS 2 |
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23 | | -#endif |
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24 | | - |
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25 | | -#ifndef RISCV_MAX_COUNTERS |
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26 | | -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." |
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27 | | -#endif |
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28 | 23 | |
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29 | 24 | /* |
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30 | 25 | * These are the indexes of bits in counteren register *minus* 1, |
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.. | .. |
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82 | 77 | int irq; |
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83 | 78 | }; |
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84 | 79 | |
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| 80 | +#endif |
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| 81 | +#ifdef CONFIG_PERF_EVENTS |
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| 82 | +#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs |
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| 83 | +#endif |
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| 84 | + |
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85 | 85 | #endif /* _ASM_RISCV_PERF_EVENT_H */ |
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