.. | .. |
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153 | 153 | tlbivax 0,r9 |
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154 | 154 | TLBSYNC |
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155 | 155 | |
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156 | | -/* |
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157 | | - * The mapping only needs to be cache-coherent on SMP, except on |
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158 | | - * Freescale e500mc derivatives where it's also needed for coherent DMA. |
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159 | | - */ |
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160 | | -#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) |
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161 | | -#define M_IF_NEEDED MAS2_M |
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162 | | -#else |
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163 | | -#define M_IF_NEEDED 0 |
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164 | | -#endif |
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165 | | - |
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166 | 156 | #if defined(ENTRY_MAPPING_BOOT_SETUP) |
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167 | 157 | |
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168 | | -/* 6. Setup KERNELBASE mapping in TLB1[0] */ |
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| 158 | +/* 6. Setup kernstart_virt_addr mapping in TLB1[0] */ |
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169 | 159 | lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ |
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170 | 160 | mtspr SPRN_MAS0,r6 |
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171 | 161 | lis r6,(MAS1_VALID|MAS1_IPROT)@h |
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172 | 162 | ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l |
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173 | 163 | mtspr SPRN_MAS1,r6 |
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174 | | - lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h |
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175 | | - ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l |
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| 164 | + lis r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h |
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| 165 | + ori r6,r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l |
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| 166 | + and r6,r6,r20 |
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| 167 | + ori r6,r6,MAS2_M_IF_NEEDED@l |
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176 | 168 | mtspr SPRN_MAS2,r6 |
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177 | 169 | mtspr SPRN_MAS3,r8 |
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178 | 170 | tlbwe |
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179 | 171 | |
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180 | | -/* 7. Jump to KERNELBASE mapping */ |
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181 | | - lis r6,(KERNELBASE & ~0xfff)@h |
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182 | | - ori r6,r6,(KERNELBASE & ~0xfff)@l |
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183 | | - rlwinm r7,r25,0,0x03ffffff |
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184 | | - add r6,r7,r6 |
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| 172 | +/* 7. Jump to kernstart_virt_addr mapping */ |
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| 173 | + mr r6,r20 |
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185 | 174 | |
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186 | 175 | #elif defined(ENTRY_MAPPING_KEXEC_SETUP) |
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187 | 176 | /* |
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