modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
..
..
@@ -34,53 +34,6 @@
34
34
 
35
35
 clockgen: global-utilities@e1000 {
36
36
 	compatible = "fsl,qoriq-clockgen-1.0";
37
-	ranges = <0x0 0xe1000 0x1000>;
38
37
 	reg = <0xe1000 0x1000>;
39
-	clock-frequency = <0>;
40
-	#address-cells = <1>;
41
-	#size-cells = <1>;
42
38
 	#clock-cells = <2>;
43
-
44
-	sysclk: sysclk {
45
-		#clock-cells = <0>;
46
-		compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
47
-		clock-output-names = "sysclk";
48
-	};
49
-	pll0: pll0@800 {
50
-		#clock-cells = <1>;
51
-		reg = <0x800 0x4>;
52
-		compatible = "fsl,qoriq-core-pll-1.0";
53
-		clocks = <&sysclk>;
54
-		clock-output-names = "pll0", "pll0-div2";
55
-	};
56
-	pll1: pll1@820 {
57
-		#clock-cells = <1>;
58
-		reg = <0x820 0x4>;
59
-		compatible = "fsl,qoriq-core-pll-1.0";
60
-		clocks = <&sysclk>;
61
-		clock-output-names = "pll1", "pll1-div2";
62
-	};
63
-	mux0: mux0@0 {
64
-		#clock-cells = <0>;
65
-		reg = <0x0 0x4>;
66
-		compatible = "fsl,qoriq-core-mux-1.0";
67
-		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68
-		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
69
-		clock-output-names = "cmux0";
70
-	};
71
-	mux1: mux1@20 {
72
-		#clock-cells = <0>;
73
-		reg = <0x20 0x4>;
74
-		compatible = "fsl,qoriq-core-mux-1.0";
75
-		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76
-		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
77
-		clock-output-names = "cmux1";
78
-	};
79
-	platform_pll: platform-pll@c00 {
80
-		#clock-cells = <1>;
81
-		reg = <0xc00 0x4>;
82
-		compatible = "fsl,qoriq-platform-pll-1.0";
83
-		clocks = <&sysclk>;
84
-		clock-output-names = "platform-pll", "platform-pll-div2";
85
-	};
86
39
 };