.. | .. |
---|
40 | 40 | d-cache-size = <32768>; |
---|
41 | 41 | dcr-controller; |
---|
42 | 42 | dcr-access-method = "native"; |
---|
43 | | - status = "ok"; |
---|
| 43 | + status = "okay"; |
---|
44 | 44 | }; |
---|
45 | 45 | cpu@1 { |
---|
46 | 46 | device_type = "cpu"; |
---|
.. | .. |
---|
248 | 248 | }; |
---|
249 | 249 | }; |
---|
250 | 250 | |
---|
251 | | - PCIE0: pciex@10100000000 { |
---|
| 251 | + PCIE0: pcie@10100000000 { |
---|
252 | 252 | device_type = "pci"; |
---|
253 | 253 | #interrupt-cells = <1>; |
---|
254 | 254 | #size-cells = <2>; |
---|
.. | .. |
---|
288 | 288 | 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>; |
---|
289 | 289 | }; |
---|
290 | 290 | |
---|
291 | | - PCIE1: pciex@20100000000 { |
---|
| 291 | + PCIE1: pcie@20100000000 { |
---|
292 | 292 | device_type = "pci"; |
---|
293 | 293 | #interrupt-cells = <1>; |
---|
294 | 294 | #size-cells = <2>; |
---|
.. | .. |
---|
328 | 328 | 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>; |
---|
329 | 329 | }; |
---|
330 | 330 | |
---|
331 | | - PCIE2: pciex@18100000000 { |
---|
| 331 | + PCIE2: pcie@18100000000 { |
---|
332 | 332 | device_type = "pci"; |
---|
333 | 333 | #interrupt-cells = <1>; |
---|
334 | 334 | #size-cells = <2>; |
---|
.. | .. |
---|
368 | 368 | 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>; |
---|
369 | 369 | }; |
---|
370 | 370 | |
---|
371 | | - PCIE3: pciex@28100000000 { |
---|
| 371 | + PCIE3: pcie@28100000000 { |
---|
372 | 372 | device_type = "pci"; |
---|
373 | 373 | #interrupt-cells = <1>; |
---|
374 | 374 | #size-cells = <2>; |
---|