forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/arch/arm64/boot/dts/ti/k3-am65.dtsi
....@@ -2,12 +2,14 @@
22 /*
33 * Device Tree Source for AM6 SoC Family
44 *
5
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
5
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
66 */
77
88 #include <dt-bindings/gpio/gpio.h>
99 #include <dt-bindings/interrupt-controller/irq.h>
1010 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
+#include <dt-bindings/pinctrl/k3.h>
12
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
1113
1214 / {
1315 model = "Texas Instruments K3 AM654 SoC";
....@@ -15,6 +17,21 @@
1517 interrupt-parent = <&gic500>;
1618 #address-cells = <2>;
1719 #size-cells = <2>;
20
+
21
+ aliases {
22
+ serial0 = &wkup_uart0;
23
+ serial1 = &mcu_uart0;
24
+ serial2 = &main_uart0;
25
+ serial3 = &main_uart1;
26
+ serial4 = &main_uart2;
27
+ i2c0 = &wkup_i2c0;
28
+ i2c1 = &mcu_i2c0;
29
+ i2c2 = &main_i2c0;
30
+ i2c3 = &main_i2c1;
31
+ i2c4 = &main_i2c2;
32
+ i2c5 = &main_i2c3;
33
+ ethernet0 = &cpsw_port1;
34
+ };
1835
1936 chosen { };
2037
....@@ -44,7 +61,7 @@
4461 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
4562 };
4663
47
- cbass_main: interconnect@100000 {
64
+ cbass_main: bus@100000 {
4865 compatible = "simple-bus";
4966 #address-cells = <2>;
5067 #size-cells = <2>;
....@@ -53,26 +70,44 @@
5370 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
5471 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
5572 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74
+ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
5675 /* MCUSS Range */
5776 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
5877 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
79
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
80
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
81
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
5982 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
6083 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
6184 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
62
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
85
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
86
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
87
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
88
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
89
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
90
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
6391
64
- cbass_mcu: interconnect@28380000 {
92
+ cbass_mcu: bus@28380000 {
6593 compatible = "simple-bus";
6694 #address-cells = <2>;
6795 #size-cells = <2>;
6896 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
6997 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
98
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
99
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
100
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
101
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
70102 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
71103 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
72104 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
73
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
105
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
106
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
107
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
108
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
74109
75
- cbass_wakeup: interconnect@42040000 {
110
+ cbass_wakeup: bus@42040000 {
76111 compatible = "simple-bus";
77112 #address-cells = <1>;
78113 #size-cells = <1>;
....@@ -85,3 +120,5 @@
85120
86121 /* Now include the peripherals for each bus segments */
87122 #include "k3-am65-main.dtsi"
123
+#include "k3-am65-mcu.dtsi"
124
+#include "k3-am65-wakeup.dtsi"