forked from ~ljy/RK356X_SDK_RELEASE

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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/arch/arm/boot/dts/sunxi-h3-h5.dtsi
....@@ -86,6 +86,7 @@
8686 			#clock-cells = <0>;
8787 			compatible = "fixed-clock";
8888 			clock-frequency = <24000000>;
89
+			clock-accuracy = <50000>;
8990 			clock-output-names = "osc24M";
9091 		};
9192 
....@@ -93,15 +94,8 @@
9394 			#clock-cells = <0>;
9495 			compatible = "fixed-clock";
9596 			clock-frequency = <32768>;
96
-			clock-output-names = "osc32k";
97
-		};
98
-
99
-		iosc: internal-osc-clk {
100
-			#clock-cells = <0>;
101
-			compatible = "fixed-clock";
102
-			clock-frequency = <16000000>;
103
-			clock-accuracy = <300000000>;
104
-			clock-output-names = "iosc";
97
+			clock-accuracy = <50000>;
98
+			clock-output-names = "ext_osc32k";
10599 		};
106100 	};
107101 
....@@ -115,15 +109,16 @@
115109 		compatible = "simple-bus";
116110 		#address-cells = <1>;
117111 		#size-cells = <1>;
112
+		dma-ranges;
118113 		ranges;
119114 
120115 		display_clocks: clock@1000000 {
121116 			/* compatible is in per SoC .dtsi file */
122
-			reg = <0x01000000 0x100000>;
123
-			clocks = <&ccu CLK_DE>,
124
-				 <&ccu CLK_BUS_DE>;
125
-			clock-names = "mod",
126
-				      "bus";
117
+			reg = <0x01000000 0x10000>;
118
+			clocks = <&ccu CLK_BUS_DE>,
119
+				 <&ccu CLK_DE>;
120
+			clock-names = "bus",
121
+				      "mod";
127122 			resets = <&ccu RST_BUS_DE>;
128123 			#clock-cells = <1>;
129124 			#reset-cells = <1>;
....@@ -150,12 +145,6 @@
150145 					};
151146 				};
152147 			};
153
-		};
154
-
155
-		syscon: syscon@1c00000 {
156
-			compatible = "allwinner,sun8i-h3-system-controller",
157
-				"syscon";
158
-			reg = <0x01c00000 0x1000>;
159148 		};
160149 
161150 		dma: dma-controller@1c02000 {
....@@ -239,6 +228,27 @@
239228 			#size-cells = <0>;
240229 		};
241230 
231
+		sid: eeprom@1c14000 {
232
+			/* compatible is in per SoC .dtsi file */
233
+			reg = <0x1c14000 0x400>;
234
+			#address-cells = <1>;
235
+			#size-cells = <1>;
236
+
237
+			ths_calibration: thermal-sensor-calibration@34 {
238
+				reg = <0x34 4>;
239
+			};
240
+		};
241
+
242
+		msgbox: mailbox@1c17000 {
243
+			compatible = "allwinner,sun8i-h3-msgbox",
244
+				     "allwinner,sun6i-a31-msgbox";
245
+			reg = <0x01c17000 0x1000>;
246
+			clocks = <&ccu CLK_BUS_MSGBOX>;
247
+			resets = <&ccu RST_BUS_MSGBOX>;
248
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
249
+			#mbox-cells = <1>;
250
+		};
251
+
242252 		usb_otg: usb@1c19000 {
243253 			compatible = "allwinner,sun8i-h3-musb";
244254 			reg = <0x01c19000 0x400>;
....@@ -249,6 +259,7 @@
249259 			phys = <&usbphy 0>;
250260 			phy-names = "usb";
251261 			extcon = <&usbphy 0>;
262
+			dr_mode = "otg";
252263 			status = "disabled";
253264 		};
254265 
....@@ -375,7 +386,7 @@
375386 		ccu: clock@1c20000 {
376387 			/* compatible is in per SoC .dtsi file */
377388 			reg = <0x01c20000 0x400>;
378
-			clocks = <&osc24M>, <&osc32k>;
389
+			clocks = <&osc24M>, <&rtc 0>;
379390 			clock-names = "hosc", "losc";
380391 			#clock-cells = <1>;
381392 			#reset-cells = <1>;
....@@ -386,14 +397,21 @@
386397 			reg = <0x01c20800 0x400>;
387398 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
388399 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
389
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
400
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
390401 			clock-names = "apb", "hosc", "losc";
391402 			gpio-controller;
392403 			#gpio-cells = <3>;
393404 			interrupt-controller;
394405 			#interrupt-cells = <3>;
395406 
396
-			emac_rgmii_pins: emac0 {
407
+			csi_pins: csi-pins {
408
+				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
409
+				       "PE6", "PE7", "PE8", "PE9", "PE10",
410
+				       "PE11";
411
+				function = "csi";
412
+			};
413
+
414
+			emac_rgmii_pins: emac-rgmii-pins {
397415 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
398416 				       "PD5", "PD7", "PD8", "PD9", "PD10",
399417 				       "PD12", "PD13", "PD15", "PD16", "PD17";
....@@ -401,22 +419,22 @@
401419 				drive-strength = <40>;
402420 			};
403421 
404
-			i2c0_pins: i2c0 {
422
+			i2c0_pins: i2c0-pins {
405423 				pins = "PA11", "PA12";
406424 				function = "i2c0";
407425 			};
408426 
409
-			i2c1_pins: i2c1 {
427
+			i2c1_pins: i2c1-pins {
410428 				pins = "PA18", "PA19";
411429 				function = "i2c1";
412430 			};
413431 
414
-			i2c2_pins: i2c2 {
432
+			i2c2_pins: i2c2-pins {
415433 				pins = "PE12", "PE13";
416434 				function = "i2c2";
417435 			};
418436 
419
-			mmc0_pins: mmc0 {
437
+			mmc0_pins: mmc0-pins {
420438 				pins = "PF0", "PF1", "PF2", "PF3",
421439 				       "PF4", "PF5";
422440 				function = "mmc0";
....@@ -424,7 +442,7 @@
424442 				bias-pull-up;
425443 			};
426444 
427
-			mmc1_pins: mmc1 {
445
+			mmc1_pins: mmc1-pins {
428446 				pins = "PG0", "PG1", "PG2", "PG3",
429447 				       "PG4", "PG5";
430448 				function = "mmc1";
....@@ -432,7 +450,7 @@
432450 				bias-pull-up;
433451 			};
434452 
435
-			mmc2_8bit_pins: mmc2_8bit {
453
+			mmc2_8bit_pins: mmc2-8bit-pins {
436454 				pins = "PC5", "PC6", "PC8",
437455 				       "PC9", "PC10", "PC11",
438456 				       "PC12", "PC13", "PC14",
....@@ -442,54 +460,59 @@
442460 				bias-pull-up;
443461 			};
444462 
445
-			spdif_tx_pins_a: spdif {
463
+			spdif_tx_pin: spdif-tx-pin {
446464 				pins = "PA17";
447465 				function = "spdif";
448466 			};
449467 
450
-			spi0_pins: spi0 {
468
+			spi0_pins: spi0-pins {
451469 				pins = "PC0", "PC1", "PC2", "PC3";
452470 				function = "spi0";
453471 			};
454472 
455
-			spi1_pins: spi1 {
473
+			spi1_pins: spi1-pins {
456474 				pins = "PA15", "PA16", "PA14", "PA13";
457475 				function = "spi1";
458476 			};
459477 
460
-			uart0_pins_a: uart0 {
478
+			uart0_pa_pins: uart0-pa-pins {
461479 				pins = "PA4", "PA5";
462480 				function = "uart0";
463481 			};
464482 
465
-			uart1_pins: uart1 {
483
+			uart1_pins: uart1-pins {
466484 				pins = "PG6", "PG7";
467485 				function = "uart1";
468486 			};
469487 
470
-			uart1_rts_cts_pins: uart1_rts_cts {
488
+			uart1_rts_cts_pins: uart1-rts-cts-pins {
471489 				pins = "PG8", "PG9";
472490 				function = "uart1";
473491 			};
474492 
475
-			uart2_pins: uart2 {
493
+			uart2_pins: uart2-pins {
476494 				pins = "PA0", "PA1";
477495 				function = "uart2";
478496 			};
479497 
480
-			uart3_pins: uart3 {
498
+			uart2_rts_cts_pins: uart2-rts-cts-pins {
499
+				pins = "PA2", "PA3";
500
+				function = "uart2";
501
+			};
502
+
503
+			uart3_pins: uart3-pins {
481504 				pins = "PA13", "PA14";
482505 				function = "uart3";
483506 			};
484507 
485
-			uart3_rts_cts_pins: uart3_rts_cts {
508
+			uart3_rts_cts_pins: uart3-rts-cts-pins {
486509 				pins = "PA15", "PA16";
487510 				function = "uart3";
488511 			};
489512 		};
490513 
491514 		timer@1c20c00 {
492
-			compatible = "allwinner,sun4i-a10-timer";
515
+			compatible = "allwinner,sun8i-a23-timer";
493516 			reg = <0x01c20c00 0xa0>;
494517 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
495518 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
....@@ -543,6 +566,16 @@
543566 			};
544567 		};
545568 
569
+		mbus: dram-controller@1c62000 {
570
+			compatible = "allwinner,sun8i-h3-mbus";
571
+			reg = <0x01c62000 0x1000>;
572
+			clocks = <&ccu CLK_MBUS>;
573
+			#address-cells = <1>;
574
+			#size-cells = <1>;
575
+			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
576
+			#interconnect-cells = <1>;
577
+		};
578
+
546579 		spi0: spi@1c68000 {
547580 			compatible = "allwinner,sun8i-h3-spi";
548581 			reg = <0x01c68000 0x1000>;
....@@ -579,6 +612,7 @@
579612 			compatible = "allwinner,sun6i-a31-wdt";
580613 			reg = <0x01c20ca0 0x20>;
581614 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
615
+			clocks = <&osc24M>;
582616 		};
583617 
584618 		spdif: spdif@1c21000 {
....@@ -744,6 +778,20 @@
744778 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
745779 		};
746780 
781
+		csi: camera@1cb0000 {
782
+			compatible = "allwinner,sun8i-h3-csi";
783
+			reg = <0x01cb0000 0x1000>;
784
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
785
+			clocks = <&ccu CLK_BUS_CSI>,
786
+				 <&ccu CLK_CSI_SCLK>,
787
+				 <&ccu CLK_DRAM_CSI>;
788
+			clock-names = "bus", "mod", "ram";
789
+			resets = <&ccu RST_BUS_CSI>;
790
+			pinctrl-names = "default";
791
+			pinctrl-0 = <&csi_pins>;
792
+			status = "disabled";
793
+		};
794
+
747795 		hdmi: hdmi@1ee0000 {
748796 			compatible = "allwinner,sun8i-h3-dw-hdmi",
749797 				     "allwinner,sun8i-a83t-dw-hdmi";
....@@ -756,7 +804,7 @@
756804 			resets = <&ccu RST_BUS_HDMI1>;
757805 			reset-names = "ctrl";
758806 			phys = <&hdmi_phy>;
759
-			phy-names = "hdmi-phy";
807
+			phy-names = "phy";
760808 			status = "disabled";
761809 
762810 			ports {
....@@ -781,7 +829,7 @@
781829 			compatible = "allwinner,sun8i-h3-hdmi-phy";
782830 			reg = <0x01ef0000 0x10000>;
783831 			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
784
-				 <&ccu 6>;
832
+				 <&ccu CLK_PLL_VIDEO>;
785833 			clock-names = "bus", "mod", "pll-0";
786834 			resets = <&ccu RST_BUS_HDMI0>;
787835 			reset-names = "phy";
....@@ -789,17 +837,20 @@
789837 		};
790838 
791839 		rtc: rtc@1f00000 {
792
-			compatible = "allwinner,sun6i-a31-rtc";
793
-			reg = <0x01f00000 0x54>;
840
+			/* compatible is in per SoC .dtsi file */
841
+			reg = <0x01f00000 0x400>;
794842 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
795843 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
844
+			clock-output-names = "osc32k", "osc32k-out", "iosc";
845
+			clocks = <&osc32k>;
846
+			#clock-cells = <1>;
796847 		};
797848 
798849 		r_ccu: clock@1f01400 {
799850 			compatible = "allwinner,sun8i-h3-r-ccu";
800851 			reg = <0x01f01400 0x100>;
801
-			clocks = <&osc24M>, <&osc32k>, <&iosc>,
802
-				 <&ccu 9>;
852
+			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
853
+				 <&ccu CLK_PLL_PERIPH0>;
803854 			clock-names = "hosc", "losc", "iosc", "pll-periph";
804855 			#clock-cells = <1>;
805856 			#reset-cells = <1>;
....@@ -811,7 +862,7 @@
811862 		};
812863 
813864 		ir: ir@1f02000 {
814
-			compatible = "allwinner,sun5i-a13-ir";
865
+			compatible = "allwinner,sun6i-a31-ir";
815866 			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
816867 			clock-names = "apb", "ir";
817868 			resets = <&r_ccu RST_APB0_IR>;
....@@ -837,22 +888,37 @@
837888 			compatible = "allwinner,sun8i-h3-r-pinctrl";
838889 			reg = <0x01f02c00 0x400>;
839890 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
840
-			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
891
+			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
841892 			clock-names = "apb", "hosc", "losc";
842893 			gpio-controller;
843894 			#gpio-cells = <3>;
844895 			interrupt-controller;
845896 			#interrupt-cells = <3>;
846897 
847
-			ir_pins_a: ir {
898
+			r_ir_rx_pin: r-ir-rx-pin {
848899 				pins = "PL11";
849900 				function = "s_cir_rx";
850901 			};
851902 
852
-			r_i2c_pins: r-i2c {
903
+			r_i2c_pins: r-i2c-pins {
853904 				pins = "PL0", "PL1";
854905 				function = "s_i2c";
855906 			};
907
+
908
+			r_pwm_pin: r-pwm-pin {
909
+				pins = "PL10";
910
+				function = "s_pwm";
911
+			};
912
+		};
913
+
914
+		r_pwm: pwm@1f03800 {
915
+			compatible = "allwinner,sun8i-h3-pwm";
916
+			reg = <0x01f03800 0x8>;
917
+			pinctrl-names = "default";
918
+			pinctrl-0 = <&r_pwm_pin>;
919
+			clocks = <&osc24M>;
920
+			#pwm-cells = <3>;
921
+			status = "disabled";
856922 		};
857923 	};
858924 };