forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
....@@ -4,11 +4,16 @@
44 Each UFS controller instance should have its own node.
55
66 Required properties:
7
-- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
8
- also list one or more of the following:
9
- "qcom,msm8994-ufshc"
10
- "qcom,msm8996-ufshc"
11
- "qcom,ufshc"
7
+- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
8
+
9
+ For Qualcomm SoCs must contain, as below, an
10
+ SoC-specific compatible along with "qcom,ufshc" and
11
+ the appropriate jedec string:
12
+ "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13
+ "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14
+ "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15
+ "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16
+ "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
1217 - interrupts : <interrupt mapping for UFS host controller IRQ>
1318 - reg : <registers mapping>
1419
....@@ -28,11 +33,16 @@
2833 - vcc-max-microamp : specifies max. load that can be drawn from vcc supply
2934 - vccq-max-microamp : specifies max. load that can be drawn from vccq supply
3035 - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
31
-- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
3236
3337 - clocks : List of phandle and clock specifier pairs
3438 - clock-names : List of clock input name strings sorted in the same
3539 order as the clocks property.
40
+ "ref_clk" indicates reference clock frequency.
41
+ UFS host supplies reference clock to UFS device and UFS device
42
+ specification allows host to provide one of the 4 frequencies (19.2 MHz,
43
+ 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
44
+ parsed and used to update the reference clock setting in device.
45
+ Defaults to 26 MHz(as per specification) if not specified by host.
3646 - freq-table-hz : Array of <min max> operating frequencies stored in the same
3747 order as the clocks property. If this property is not
3848 defined or a value in the array is "0" then it is assumed
....@@ -41,8 +51,12 @@
4151 -lanes-per-direction : number of lanes available per direction - either 1 or 2.
4252 Note that it is assume same number of lanes is used both
4353 directions at once. If not specified, default is 2 lanes per direction.
54
+- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose
55
+ PHY reset from the UFS controller.
4456 - resets : reset node register
4557 - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
58
+- reset-gpios : A phandle and gpio specifier denoting the GPIO connected
59
+ to the RESET pin of the UFS memory device.
4660
4761 Note: If above properties are not defined it can be assumed that the supply
4862 regulators or clocks are always on.
....@@ -54,7 +68,6 @@
5468 interrupts = <0 28 0>;
5569
5670 vdd-hba-supply = <&xxx_reg0>;
57
- vdd-hba-fixed-regulator;
5871 vcc-supply = <&xxx_reg1>;
5972 vcc-supply-1p8;
6073 vccq-supply = <&xxx_reg2>;
....@@ -70,4 +83,5 @@
7083 reset-names = "rst";
7184 phys = <&ufsphy1>;
7285 phy-names = "ufsphy";
86
+ #reset-cells = <1>;
7387 };