.. | .. |
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4 | 4 | Each UFS controller instance should have its own node. |
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5 | 5 | |
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6 | 6 | Required properties: |
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7 | | -- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may |
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8 | | - also list one or more of the following: |
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9 | | - "qcom,msm8994-ufshc" |
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10 | | - "qcom,msm8996-ufshc" |
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11 | | - "qcom,ufshc" |
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| 7 | +- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0" |
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| 8 | + |
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| 9 | + For Qualcomm SoCs must contain, as below, an |
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| 10 | + SoC-specific compatible along with "qcom,ufshc" and |
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| 11 | + the appropriate jedec string: |
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| 12 | + "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" |
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| 13 | + "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" |
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| 14 | + "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" |
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| 15 | + "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" |
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| 16 | + "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" |
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12 | 17 | - interrupts : <interrupt mapping for UFS host controller IRQ> |
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13 | 18 | - reg : <registers mapping> |
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14 | 19 | |
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.. | .. |
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28 | 33 | - vcc-max-microamp : specifies max. load that can be drawn from vcc supply |
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29 | 34 | - vccq-max-microamp : specifies max. load that can be drawn from vccq supply |
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30 | 35 | - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply |
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31 | | -- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator |
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32 | 36 | |
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33 | 37 | - clocks : List of phandle and clock specifier pairs |
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34 | 38 | - clock-names : List of clock input name strings sorted in the same |
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35 | 39 | order as the clocks property. |
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| 40 | + "ref_clk" indicates reference clock frequency. |
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| 41 | + UFS host supplies reference clock to UFS device and UFS device |
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| 42 | + specification allows host to provide one of the 4 frequencies (19.2 MHz, |
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| 43 | + 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is |
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| 44 | + parsed and used to update the reference clock setting in device. |
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| 45 | + Defaults to 26 MHz(as per specification) if not specified by host. |
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36 | 46 | - freq-table-hz : Array of <min max> operating frequencies stored in the same |
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37 | 47 | order as the clocks property. If this property is not |
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38 | 48 | defined or a value in the array is "0" then it is assumed |
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.. | .. |
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41 | 51 | -lanes-per-direction : number of lanes available per direction - either 1 or 2. |
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42 | 52 | Note that it is assume same number of lanes is used both |
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43 | 53 | directions at once. If not specified, default is 2 lanes per direction. |
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| 54 | +- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose |
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| 55 | + PHY reset from the UFS controller. |
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44 | 56 | - resets : reset node register |
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45 | 57 | - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. |
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| 58 | +- reset-gpios : A phandle and gpio specifier denoting the GPIO connected |
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| 59 | + to the RESET pin of the UFS memory device. |
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46 | 60 | |
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47 | 61 | Note: If above properties are not defined it can be assumed that the supply |
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48 | 62 | regulators or clocks are always on. |
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.. | .. |
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54 | 68 | interrupts = <0 28 0>; |
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55 | 69 | |
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56 | 70 | vdd-hba-supply = <&xxx_reg0>; |
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57 | | - vdd-hba-fixed-regulator; |
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58 | 71 | vcc-supply = <&xxx_reg1>; |
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59 | 72 | vcc-supply-1p8; |
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60 | 73 | vccq-supply = <&xxx_reg2>; |
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.. | .. |
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70 | 83 | reset-names = "rst"; |
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71 | 84 | phys = <&ufsphy1>; |
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72 | 85 | phy-names = "ufsphy"; |
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| 86 | + #reset-cells = <1>; |
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73 | 87 | }; |
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