forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
....@@ -1,10 +1,13 @@
11 Microsemi Ocelot reset controller
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33 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
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-SoC MIPS core.
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+SoC core.
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+
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+The reset registers are both present in the MSCC vcoreiii MIPS and
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+microchip Sparx5 armv8 SoC's.
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69 Required Properties:
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- - compatible: "mscc,ocelot-chip-reset"
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+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
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912 Example:
1013 reset@1070008 {