modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/pci/pci.txt
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@@ -1,12 +1,12 @@
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 PCI bus bridges have standardized Device Tree bindings:
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 PCI Bus Binding to: IEEE Std 1275-1994
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-http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
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+https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
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5
 
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 And for the interrupt mapping part:
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 Open Firmware Recommended Practice: Interrupt Mapping
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-http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
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+https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
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 Additionally to the properties specified in the above standards a host bridge
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 driver implementation may support the following properties:
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@@ -24,3 +24,61 @@
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    unsupported link speed, for instance, trying to do training for
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    unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'
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    for gen2, and '1' for gen1. Any other values are invalid.
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+- reset-gpios:
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+   If present this property specifies PERST# GPIO. Host drivers can parse the
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+   GPIO and apply fundamental reset to endpoints.
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+- supports-clkreq:
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+   If present this property specifies that CLKREQ signal routing exists from
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+   root port to downstream device and host bridge drivers can do programming
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+   which depends on CLKREQ signal existence. For example, programming root port
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+   not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
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+
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+PCI-PCI Bridge properties
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+-------------------------
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+
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+PCIe root ports and switch ports may be described explicitly in the device
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+tree, as children of the host bridge node. Even though those devices are
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+discoverable by probing, it might be necessary to describe properties that
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+aren't provided by standard PCIe capabilities.
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+
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+Required properties:
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+
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+- reg:
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+   Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
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+   document, it is a five-cell address encoded as (phys.hi phys.mid
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+   phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
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+   0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
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+
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+   The bus number is defined by firmware, through the standard bridge
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+   configuration mechanism. If this port is a switch port, then firmware
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+   allocates the bus number and writes it into the Secondary Bus Number
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+   register of the bridge directly above this port. Otherwise, the bus
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+   number of a root port is the first number in the bus-range property,
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+   defaulting to zero.
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+
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+   If firmware leaves the ARI Forwarding Enable bit set in the bridge
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+   above this port, then phys.hi contains the 8-bit function number as
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+   0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
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+   recommends that firmware only leaves ARI enabled when it knows that the
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+   OS is ARI-aware.
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+
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+Optional properties:
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+
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+- external-facing:
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+   When present, the port is external-facing. All bridges and endpoints
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+   downstream of this port are external to the machine. The OS can, for
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+   example, use this information to identify devices that cannot be
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+   trusted with relaxed DMA protection, as users could easily attach
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+   malicious devices to this port.
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+
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+Example:
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+
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+pcie@10000000 {
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+	compatible = "pci-host-ecam-generic";
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+	...
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+	pcie@0008 {
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+		/* Root port 00:01.0 is external-facing */
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+		reg = <0x00000800 0 0 0 0>;
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+		external-facing;
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+	};
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+};