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6 | 6 | The device node has additional properties: |
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7 | 7 | |
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8 | 8 | Required properties: |
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9 | | - - compatible : Should contain "altr,socfpga-stmmac" along with |
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10 | | - "snps,dwmac" and any applicable more detailed |
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| 9 | + - compatible : For Cyclone5/Arria5 SoCs it should contain |
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| 10 | + "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs |
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| 11 | + "altr,socfpga-stmmac-a10-s10". |
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| 12 | + Along with "snps,dwmac" and any applicable more detailed |
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11 | 13 | designware version numbers documented in stmmac.txt |
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12 | 14 | - altr,sysmgr-syscon : Should be the phandle to the system manager node that |
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13 | 15 | encompasses the glue register, the register offset, and the register shift. |
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| 16 | + On Cyclone5/Arria5, the register shift represents the PHY mode bits, while |
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| 17 | + on the Arria10/Stratix10/Agilex platforms, the register shift represents |
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| 18 | + bit for each emac to enable/disable signals from the FPGA fabric to the |
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| 19 | + EMAC modules. |
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14 | 20 | - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock |
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15 | 21 | for ptp ref clk. This affects all emacs as the clock is common. |
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16 | 22 | |
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