forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
....@@ -6,11 +6,17 @@
66 The device node has additional properties:
77
88 Required properties:
9
- - compatible : Should contain "altr,socfpga-stmmac" along with
10
- "snps,dwmac" and any applicable more detailed
9
+ - compatible : For Cyclone5/Arria5 SoCs it should contain
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+ "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
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+ "altr,socfpga-stmmac-a10-s10".
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+ Along with "snps,dwmac" and any applicable more detailed
1113 designware version numbers documented in stmmac.txt
1214 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
1315 encompasses the glue register, the register offset, and the register shift.
16
+ On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
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+ on the Arria10/Stratix10/Agilex platforms, the register shift represents
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+ bit for each emac to enable/disable signals from the FPGA fabric to the
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+ EMAC modules.
1420 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
1521 for ptp ref clk. This affects all emacs as the clock is common.
1622