modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/Documentation/devicetree/bindings/net/nixge.txt
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@@ -1,16 +1,52 @@
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 * NI XGE Ethernet controller
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 Required properties:
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-- compatible: Should be "ni,xge-enet-2.00"
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-- reg: Address and length of the register set for the device
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+- compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
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+              older device trees with DMA engines co-located in the address map,
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+              with the one reg entry to describe the whole device.
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+- reg: Address and length of the register set for the device. It contains the
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+       information of registers in the same order as described by reg-names.
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+- reg-names: Should contain the reg names
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+	"dma":  DMA engine control and status region
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+        "ctrl": MDIO and PHY control and status region
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 - interrupts: Should contain tx and rx interrupt
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 - interrupt-names: Should be "rx" and "tx"
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 - phy-mode: See ethernet.txt file in the same directory.
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-- phy-handle: See ethernet.txt file in the same directory.
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 - nvmem-cells: Phandle of nvmem cell containing the MAC address
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 - nvmem-cell-names: Should be "address"
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+Optional properties:
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+- mdio subnode to indicate presence of MDIO controller
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+- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
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+  Use instead of phy-handle.
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+- phy-handle: See ethernet.txt file in the same directory.
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+
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 Examples (10G generic PHY):
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+	nixge0: ethernet@40000000 {
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+		compatible = "ni,xge-enet-3.00";
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+		reg = <0x40000000 0x4000
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+		       0x41002000 0x2000>;
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+		reg-names = "dma", "ctrl";
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+
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+		nvmem-cells = <&eth1_addr>;
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+		nvmem-cell-names = "address";
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+
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+		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupt-names = "rx", "tx";
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+		interrupt-parent = <&intc>;
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+
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+		phy-mode = "xgmii";
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+		phy-handle = <&ethernet_phy1>;
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+
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+		mdio {
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+			ethernet_phy1: ethernet-phy@4 {
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+				compatible = "ethernet-phy-ieee802.3-c45";
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+				reg = <4>;
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+			};
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+		};
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+	};
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+
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+Examples (10G generic PHY, no MDIO):
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 	nixge0: ethernet@40000000 {
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 		compatible = "ni,xge-enet-2.00";
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 		reg = <0x40000000 0x6000>;
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@@ -24,9 +60,33 @@
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 		phy-mode = "xgmii";
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 		phy-handle = <&ethernet_phy1>;
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+	};
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-		ethernet_phy1: ethernet-phy@4 {
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-			compatible = "ethernet-phy-ieee802.3-c45";
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-			reg = <4>;
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+Examples (1G generic fixed-link + MDIO):
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+	nixge0: ethernet@40000000 {
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+		compatible = "ni,xge-enet-2.00";
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+		reg = <0x40000000 0x6000>;
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+
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+		nvmem-cells = <&eth1_addr>;
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+		nvmem-cell-names = "address";
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+
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+		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupt-names = "rx", "tx";
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+		interrupt-parent = <&intc>;
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+
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+		phy-mode = "xgmii";
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+
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+		fixed-link {
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+			speed = <1000>;
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+			pause;
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+			link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>;
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 		};
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+
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+		mdio {
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+			ethernet_phy1: ethernet-phy@4 {
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+				compatible = "ethernet-phy-ieee802.3-c22";
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+				reg = <4>;
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+			};
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+		};
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+
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 	};